miegl/b210-k7-fpga
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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf
-9
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@@ -1,9 +0,0 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc
-7
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@@ -1,7 +0,0 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}