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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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top/b200/coregen/b200_clk_gen.asy
-33
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@@ -1,33 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 b200_clk_gen
RECTANGLE Normal 32 32 576 1088
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk_in1_p
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName clk_in1_n
PINATTR Polarity IN
LINE Normal 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 608 80 576 80
PIN 608 80 RIGHT 36
PINATTR PinName clk_out1
PINATTR Polarity OUT
LINE Normal 608 176 576 176
PIN 608 176 RIGHT 36
PINATTR PinName clk_out2
PINATTR Polarity OUT
LINE Normal 608 272 576 272
PIN 608 272 RIGHT 36
PINATTR PinName clk_out3
PINATTR Polarity OUT
LINE Normal 608 976 576 976
PIN 608 976 RIGHT 36
PINATTR PinName locked
PINATTR Polarity OUT