miegl/b210-k7-fpga
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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
-17
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@@ -1,17 +0,0 @@
#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
NET "DATA<*" S;
NET "DATA<*" KEEP;
top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
-6
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@@ -1,6 +0,0 @@
#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]