Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,21 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 b200_chipscope_ila
-RECTANGLE Normal 32 32 288 704
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName control[35:0]
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Wide 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName data[63:0]
-PINATTR Polarity IN
-LINE Wide 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName trig0[7:0]
-PINATTR Polarity IN
-