Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd

top/b200/coregen/b200_chipscope_icon.xco

@@ -1,56 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.4
-# Date: Tue Feb 19 22:27:58 2013
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fgg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
-# END Select
-# BEGIN Parameters
-CSET component_name=b200_chipscope_icon
-CSET constraint_type=external
-CSET enable_jtag_bufg=true
-CSET example_design=false
-CSET number_control_ports=1
-CSET use_ext_bscan=false
-CSET use_softbscan=false
-CSET use_unused_bscan=false
-CSET user_scan_chain=USER1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-12-18T02:47:25Z
-# END Extra information
-GENERATE
-# CRC: 729764e8