Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1 +0,0 @@
-iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall | grep -v timescale
				`@@ -1 +0,0 @@`
				`iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall \| grep -v timescale`