Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,15 +0,0 @@
-#
-# Copyright 2012 Ettus Research LLC
-#
-
-##################################################
-# ZYNQ FIFO interface sources
-##################################################
-ZYNQ_FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/zynq_fifo/, \
-zf_arbiter.v \
-zf_stream_to_host.v \
-zf_host_to_stream.v \
-zf_slave_readback.v \
-zf_slave_settings.v \
-zynq_fifo_top.v \
-))