Removed copy of FPGA source files.
Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
@@ -1,948 +0,0 @@
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-- Company: ZPU4 generic memory interface CPU
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-- Engineer: Øyvind Harboe
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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library work;
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use work.zpu_config.all;
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use work.zpupkg.all;
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entity zpu_core is
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Port ( clk : in std_logic;
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areset : in std_logic;
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enable : in std_logic;
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mem_req : out std_logic;
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mem_we : out std_logic;
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mem_ack : in std_logic;
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mem_read : in std_logic_vector(wordSize-1 downto 0);
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mem_write : out std_logic_vector(wordSize-1 downto 0);
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out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
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mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
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interrupt : in std_logic;
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break : out std_logic;
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zpu_status : out std_logic_vector(63 downto 0));
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end zpu_core;
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architecture behave of zpu_core is
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type InsnType is
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(
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State_AddTop,
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State_Dup,
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State_DupStackB,
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State_Pop,
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State_Popdown,
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State_Add,
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State_Or,
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State_And,
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State_Store,
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State_AddSP,
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State_Shift,
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State_Nop,
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State_Im,
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State_LoadSP,
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State_StoreSP,
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State_Emulate,
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State_Load,
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State_PushPC,
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State_PushSP,
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State_PopPC,
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State_PopPCRel,
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State_Not,
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State_Flip,
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State_PopSP,
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State_Neqbranch,
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State_Eq,
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State_Loadb,
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State_Mult,
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State_Lessthan,
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State_Lessthanorequal,
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State_Ulessthanorequal,
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State_Ulessthan,
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State_Pushspadd,
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State_Call,
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State_Callpcrel,
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State_Sub,
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State_Break,
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State_Storeb,
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State_Interrupt,
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State_InsnFetch
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);
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type StateType is
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(
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State_Idle, -- using first state first on the list out of paranoia
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State_Load2,
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State_Popped,
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State_LoadSP2,
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State_LoadSP3,
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State_AddSP2,
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State_Fetch,
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State_Execute,
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State_Decode,
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State_Decode2,
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State_Resync,
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State_StoreSP2,
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State_Resync2,
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State_Resync3,
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State_Loadb2,
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State_Storeb2,
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State_Mult2,
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State_Mult3,
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State_Mult5,
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State_Mult6,
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State_Mult4,
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State_BinaryOpResult
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);
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signal pc : std_logic_vector(maxAddrBitIncIO downto 0);
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signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal stackA : std_logic_vector(wordSize-1 downto 0);
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signal binaryOpResult : std_logic_vector(wordSize-1 downto 0);
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signal multResult2 : std_logic_vector(wordSize-1 downto 0);
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signal multResult3 : std_logic_vector(wordSize-1 downto 0);
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signal multResult : std_logic_vector(wordSize-1 downto 0);
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signal multA : std_logic_vector(wordSize-1 downto 0);
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signal multB : std_logic_vector(wordSize-1 downto 0);
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signal stackB : std_logic_vector(wordSize-1 downto 0);
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signal idim_flag : std_logic;
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signal busy : std_logic;
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signal mem_readEnable : std_logic;
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signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal mem_delayReadEnable : std_logic;
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signal mem_busy : std_logic;
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signal decodeWord : std_logic_vector(wordSize-1 downto 0);
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signal state : StateType;
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signal insn : InsnType;
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type InsnArray is array(0 to wordBytes-1) of InsnType;
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signal decodedOpcode : InsnArray;
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type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
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signal opcode : OpcodeArray;
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signal begin_inst : std_logic;
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signal trace_opcode : std_logic_vector(7 downto 0);
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signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0);
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signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0);
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signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
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signal out_mem_req : std_logic;
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signal inInterrupt : std_logic;
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-- state machine.
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begin
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zpu_status(maxAddrBitIncIO downto 0) <= trace_pc;
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zpu_status(31) <= '1';
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zpu_status(39 downto 32) <= trace_opcode;
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zpu_status(40) <= '1' when (state = State_Idle) else '0';
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zpu_status(62) <= '1';
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traceFileGenerate:
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if Generate_Trace generate
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trace_file: trace port map (
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clk => clk,
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begin_inst => begin_inst,
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pc => trace_pc,
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opcode => trace_opcode,
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sp => trace_sp,
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memA => trace_topOfStack,
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memB => trace_topOfStackB,
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busy => busy,
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intsp => (others => 'U')
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);
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end generate;
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-- the memory subsystem will tell us one cycle later whether or
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-- not it is busy
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out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
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out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
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mem_req <= out_mem_req;
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incSp <= sp + 1;
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incIncSp <= sp + 2;
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decSp <= sp - 1;
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mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy
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opcodeControl:
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process(clk, areset)
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variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
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variable spOffset : std_logic_vector(4 downto 0);
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variable tSpOffset : std_logic_vector(4 downto 0);
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variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0);
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variable tNextState : InsnType;
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variable tDecodedOpcode : InsnArray;
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variable tMultResult : std_logic_vector(wordSize*2-1 downto 0);
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begin
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if areset = '1' then
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state <= State_Idle;
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break <= '0';
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sp <= spStart(maxAddrBitIncIO downto minAddrBit);
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pc <= (others => '0');
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idim_flag <= '0';
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begin_inst <= '0';
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mem_we <= '0';
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multA <= (others => '0');
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multB <= (others => '0');
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mem_writeMask <= (others => '1');
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out_mem_req <= '0';
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mem_addr <= (others => DontCareValue);
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mem_write <= (others => DontCareValue);
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inInterrupt <= '0';
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elsif (clk'event and clk = '1') then
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-- we must multiply unconditionally to get pipelined multiplication
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tMultResult := multA * multB;
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multResult3 <= multResult2;
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multResult2 <= multResult;
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multResult <= tMultResult(wordSize-1 downto 0);
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spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4);
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spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0);
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nextPC := pc + 1;
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-- prepare trace snapshot
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trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0)));
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trace_pc <= pc;
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trace_sp <= sp;
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trace_topOfStack <= stackA;
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trace_topOfStackB <= stackB;
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begin_inst <= '0';
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-- we terminate the requeset as soon as we get acknowledge
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if mem_ack = '1' then
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out_mem_req <= '0';
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mem_we <= '0';
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end if;
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if interrupt='0' then
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inInterrupt <= '0'; -- no longer in an interrupt
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end if;
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case state is
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when State_Idle =>
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if enable='1' then
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state <= State_Resync;
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end if;
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-- Initial state of ZPU, fetch top of stack + first instruction
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when State_Resync =>
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if mem_busy='0' then
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mem_addr <= sp;
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out_mem_req <= '1';
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state <= State_Resync2;
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end if;
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when State_Resync2 =>
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if mem_busy='0' then
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stackA <= mem_read;
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mem_addr <= incSp;
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out_mem_req <= '1';
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state <= State_Resync3;
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end if;
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when State_Resync3 =>
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if mem_busy='0' then
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stackB <= mem_read;
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mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
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out_mem_req <= '1';
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state <= State_Decode;
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end if;
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when State_Decode =>
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if mem_busy='0' then
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decodeWord <= mem_read;
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state <= State_Decode2;
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end if;
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when State_Decode2 =>
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-- decode 4 instructions in parallel
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for i in 0 to wordBytes-1 loop
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tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
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tSpOffset(4):=not tOpcode(4);
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tSpOffset(3 downto 0):=tOpcode(3 downto 0);
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opcode(i) <= tOpcode;
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if (tOpcode(7 downto 7)=OpCode_Im) then
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tNextState:=State_Im;
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elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
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if tSpOffset = 0 then
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tNextState := State_Pop;
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elsif tSpOffset=1 then
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tNextState := State_PopDown;
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else
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tNextState :=State_StoreSP;
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end if;
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elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
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if tSpOffset = 0 then
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tNextState :=State_Dup;
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elsif tSpOffset = 1 then
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tNextState :=State_DupStackB;
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else
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tNextState :=State_LoadSP;
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end if;
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elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
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tNextState :=State_Emulate;
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if tOpcode(5 downto 0)=OpCode_Neqbranch then
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tNextState :=State_Neqbranch;
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elsif tOpcode(5 downto 0)=OpCode_Eq then
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tNextState :=State_Eq;
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elsif tOpcode(5 downto 0)=OpCode_Lessthan then
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tNextState :=State_Lessthan;
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elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
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--tNextState :=State_Lessthanorequal;
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elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
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tNextState :=State_Ulessthan;
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elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
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--tNextState :=State_Ulessthanorequal;
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elsif tOpcode(5 downto 0)=OpCode_Loadb then
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tNextState :=State_Loadb;
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elsif tOpcode(5 downto 0)=OpCode_Mult then
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tNextState :=State_Mult;
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elsif tOpcode(5 downto 0)=OpCode_Storeb then
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tNextState :=State_Storeb;
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elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
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tNextState :=State_Pushspadd;
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elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
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tNextState :=State_Callpcrel;
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elsif tOpcode(5 downto 0)=OpCode_Call then
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--tNextState :=State_Call;
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elsif tOpcode(5 downto 0)=OpCode_Sub then
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tNextState :=State_Sub;
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elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
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--tNextState :=State_PopPCRel;
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end if;
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elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
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if tSpOffset = 0 then
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tNextState := State_Shift;
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elsif tSpOffset = 1 then
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tNextState := State_AddTop;
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else
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tNextState :=State_AddSP;
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end if;
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else
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case tOpcode(3 downto 0) is
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when OpCode_Nop =>
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tNextState :=State_Nop;
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when OpCode_PushSP =>
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tNextState :=State_PushSP;
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when OpCode_PopPC =>
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tNextState :=State_PopPC;
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when OpCode_Add =>
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tNextState :=State_Add;
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when OpCode_Or =>
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tNextState :=State_Or;
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when OpCode_And =>
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tNextState :=State_And;
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when OpCode_Load =>
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tNextState :=State_Load;
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when OpCode_Not =>
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tNextState :=State_Not;
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when OpCode_Flip =>
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tNextState :=State_Flip;
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when OpCode_Store =>
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tNextState :=State_Store;
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when OpCode_PopSP =>
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tNextState :=State_PopSP;
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when others =>
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tNextState := State_Break;
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end case;
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end if;
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tDecodedOpcode(i) := tNextState;
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end loop;
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insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0)));
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-- once we wrap, we need to fetch
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tDecodedOpcode(0) := State_InsnFetch;
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decodedOpcode <= tDecodedOpcode;
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state <= State_Execute;
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-- Each instruction must:
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--
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-- 1. set idim_flag
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-- 2. increase pc if applicable
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-- 3. set next state if appliable
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-- 4. do it's operation
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when State_Execute =>
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insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0)));
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case insn is
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when State_InsnFetch =>
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state <= State_Fetch;
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when State_Im =>
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if mem_busy='0' then
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begin_inst <= '1';
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idim_flag <= '1';
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pc <= pc + 1;
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if idim_flag='1' then
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stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
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stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
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else
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out_mem_req <= '1';
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mem_we <= '1';
|
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mem_addr <= incSp;
|
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mem_write <= stackB;
|
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stackB <= stackA;
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sp <= decSp;
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for i in wordSize-1 downto 7 loop
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stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6);
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end loop;
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stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
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end if;
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else
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insn <= insn;
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end if;
|
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when State_StoreSP =>
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if mem_busy='0' then
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begin_inst <= '1';
|
||||
idim_flag <= '0';
|
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state <= State_StoreSP2;
|
||||
|
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out_mem_req <= '1';
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mem_we <= '1';
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mem_addr <= sp+spOffset;
|
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mem_write <= stackA;
|
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stackA <= stackB;
|
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sp <= incSp;
|
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else
|
||||
insn <= insn;
|
||||
end if;
|
||||
|
||||
|
||||
when State_LoadSP =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
state <= State_LoadSP2;
|
||||
|
||||
sp <= decSp;
|
||||
out_mem_req <= '1';
|
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mem_we <= '1';
|
||||
mem_addr <= incSp;
|
||||
mem_write <= stackB;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Emulate =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
sp <= decSp;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
mem_addr <= incSp;
|
||||
mem_write <= stackB;
|
||||
stackA <= (others => DontCareValue);
|
||||
stackA(maxAddrBitIncIO downto 0) <= pc + 1;
|
||||
stackB <= stackA;
|
||||
|
||||
-- The emulate address is:
|
||||
-- 98 7654 3210
|
||||
-- 0000 00aa aaa0 0000
|
||||
pc <= (others => '0');
|
||||
pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0);
|
||||
state <= State_Fetch;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Callpcrel =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
stackA <= (others => DontCareValue);
|
||||
stackA(maxAddrBitIncIO downto 0) <= pc + 1;
|
||||
|
||||
pc <= pc + stackA(maxAddrBitIncIO downto 0);
|
||||
state <= State_Fetch;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Call =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
stackA <= (others => DontCareValue);
|
||||
stackA(maxAddrBitIncIO downto 0) <= pc + 1;
|
||||
pc <= stackA(maxAddrBitIncIO downto 0);
|
||||
state <= State_Fetch;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_AddSP =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
state <= State_AddSP2;
|
||||
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= sp+spOffset;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_PushSP =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
sp <= decSp;
|
||||
stackA <= (others => '0');
|
||||
stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
|
||||
stackB <= stackA;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
mem_addr <= incSp;
|
||||
mem_write <= stackB;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_PopPC =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= stackA(maxAddrBitIncIO downto 0);
|
||||
sp <= incSp;
|
||||
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
mem_addr <= incSp;
|
||||
mem_write <= stackB;
|
||||
state <= State_Resync;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_PopPCRel =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= stackA(maxAddrBitIncIO downto 0) + pc;
|
||||
sp <= incSp;
|
||||
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
mem_addr <= incSp;
|
||||
mem_write <= stackB;
|
||||
state <= State_Resync;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Add =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
stackA <= stackA + stackB;
|
||||
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= incIncSp;
|
||||
sp <= incSp;
|
||||
state <= State_Popped;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Sub =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
binaryOpResult <= stackB - stackA;
|
||||
state <= State_BinaryOpResult;
|
||||
when State_Pop =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
mem_addr <= incIncSp;
|
||||
out_mem_req <= '1';
|
||||
sp <= incSp;
|
||||
stackA <= stackB;
|
||||
state <= State_Popped;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_PopDown =>
|
||||
if mem_busy='0' then
|
||||
-- PopDown leaves top of stack unchanged
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
mem_addr <= incIncSp;
|
||||
out_mem_req <= '1';
|
||||
sp <= incSp;
|
||||
state <= State_Popped;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Or =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
stackA <= stackA or stackB;
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= incIncSp;
|
||||
sp <= incSp;
|
||||
state <= State_Popped;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_And =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
stackA <= stackA and stackB;
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= incIncSp;
|
||||
sp <= incSp;
|
||||
state <= State_Popped;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Eq =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
binaryOpResult <= (others => '0');
|
||||
if (stackA=stackB) then
|
||||
binaryOpResult(0) <= '1';
|
||||
end if;
|
||||
state <= State_BinaryOpResult;
|
||||
when State_Ulessthan =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
binaryOpResult <= (others => '0');
|
||||
if (stackA<stackB) then
|
||||
binaryOpResult(0) <= '1';
|
||||
end if;
|
||||
state <= State_BinaryOpResult;
|
||||
when State_Ulessthanorequal =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
binaryOpResult <= (others => '0');
|
||||
if (stackA<=stackB) then
|
||||
binaryOpResult(0) <= '1';
|
||||
end if;
|
||||
state <= State_BinaryOpResult;
|
||||
when State_Lessthan =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
binaryOpResult <= (others => '0');
|
||||
if (signed(stackA)<signed(stackB)) then
|
||||
binaryOpResult(0) <= '1';
|
||||
end if;
|
||||
state <= State_BinaryOpResult;
|
||||
when State_Lessthanorequal =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
binaryOpResult <= (others => '0');
|
||||
if (signed(stackA)<=signed(stackB)) then
|
||||
binaryOpResult(0) <= '1';
|
||||
end if;
|
||||
state <= State_BinaryOpResult;
|
||||
when State_Load =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
state <= State_Load2;
|
||||
|
||||
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
|
||||
out_mem_req <= '1';
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
|
||||
when State_Dup =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
sp <= decSp;
|
||||
stackB <= stackA;
|
||||
mem_write <= stackB;
|
||||
mem_addr <= incSp;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_DupStackB =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
sp <= decSp;
|
||||
stackA <= stackB;
|
||||
stackB <= stackA;
|
||||
mem_write <= stackB;
|
||||
mem_addr <= incSp;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Store =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
|
||||
mem_write <= stackB;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
sp <= incIncSp;
|
||||
state <= State_Resync;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_PopSP =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
mem_write <= stackB;
|
||||
mem_addr <= incSp;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
sp <= stackA(maxAddrBitIncIO downto minAddrBit);
|
||||
state <= State_Resync;
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Nop =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
when State_Not =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
stackA <= not stackA;
|
||||
when State_Flip =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
for i in 0 to wordSize-1 loop
|
||||
stackA(i) <= stackA(wordSize-1-i);
|
||||
end loop;
|
||||
when State_AddTop =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
stackA <= stackA + stackB;
|
||||
when State_Shift =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
|
||||
stackA(0) <= '0';
|
||||
when State_Pushspadd =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
pc <= pc + 1;
|
||||
|
||||
stackA <= (others => '0');
|
||||
stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
|
||||
when State_Neqbranch =>
|
||||
-- branches are almost always taken as they form loops
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
sp <= incIncSp;
|
||||
if (stackB/=0) then
|
||||
pc <= stackA(maxAddrBitIncIO downto 0) + pc;
|
||||
else
|
||||
pc <= pc + 1;
|
||||
end if;
|
||||
-- need to fetch stack again.
|
||||
state <= State_Resync;
|
||||
when State_Mult =>
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
|
||||
multA <= stackA;
|
||||
multB <= stackB;
|
||||
state <= State_Mult2;
|
||||
when State_Break =>
|
||||
report "Break instruction encountered" severity failure;
|
||||
break <= '1';
|
||||
|
||||
when State_Loadb =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
state <= State_Loadb2;
|
||||
|
||||
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
|
||||
out_mem_req <= '1';
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
when State_Storeb =>
|
||||
if mem_busy='0' then
|
||||
begin_inst <= '1';
|
||||
idim_flag <= '0';
|
||||
state <= State_Storeb2;
|
||||
|
||||
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
|
||||
out_mem_req <= '1';
|
||||
else
|
||||
insn <= insn;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
-- sp <= (others => DontCareValue);
|
||||
report "Illegal instruction" severity failure;
|
||||
break <= '1';
|
||||
end case;
|
||||
|
||||
|
||||
when State_StoreSP2 =>
|
||||
if mem_busy='0' then
|
||||
mem_addr <= incSp;
|
||||
out_mem_req <= '1';
|
||||
state <= State_Popped;
|
||||
end if;
|
||||
when State_LoadSP2 =>
|
||||
if mem_busy='0' then
|
||||
state <= State_LoadSP3;
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= sp+spOffset+1;
|
||||
end if;
|
||||
when State_LoadSP3 =>
|
||||
if mem_busy='0' then
|
||||
pc <= pc + 1;
|
||||
state <= State_Execute;
|
||||
stackB <= stackA;
|
||||
stackA <= mem_read;
|
||||
end if;
|
||||
when State_AddSP2 =>
|
||||
if mem_busy='0' then
|
||||
pc <= pc + 1;
|
||||
state <= State_Execute;
|
||||
stackA <= stackA + mem_read;
|
||||
end if;
|
||||
when State_Load2 =>
|
||||
if mem_busy='0' then
|
||||
stackA <= mem_read;
|
||||
pc <= pc + 1;
|
||||
state <= State_Execute;
|
||||
end if;
|
||||
when State_Loadb2 =>
|
||||
if mem_busy='0' then
|
||||
stackA <= (others => '0');
|
||||
stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8);
|
||||
pc <= pc + 1;
|
||||
state <= State_Execute;
|
||||
end if;
|
||||
when State_Storeb2 =>
|
||||
if mem_busy='0' then
|
||||
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
|
||||
mem_write <= mem_read;
|
||||
mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
pc <= pc + 1;
|
||||
sp <= incIncSp;
|
||||
state <= State_Resync;
|
||||
end if;
|
||||
when State_Fetch =>
|
||||
if mem_busy='0' then
|
||||
if interrupt='1' and inInterrupt='0' and idim_flag='0' then
|
||||
-- We got an interrupt
|
||||
inInterrupt <= '1';
|
||||
|
||||
sp <= decSp;
|
||||
out_mem_req <= '1';
|
||||
mem_we <= '1';
|
||||
mem_addr <= incSp;
|
||||
mem_write <= stackB;
|
||||
stackA <= (others => DontCareValue);
|
||||
stackA(maxAddrBitIncIO downto 0) <= pc;
|
||||
stackB <= stackA;
|
||||
|
||||
pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address
|
||||
|
||||
report "ZPU jumped to interrupt!" severity note;
|
||||
else
|
||||
mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
|
||||
out_mem_req <= '1';
|
||||
state <= State_Decode;
|
||||
end if;
|
||||
end if;
|
||||
when State_Mult2 =>
|
||||
state <= State_Mult3;
|
||||
when State_Mult3 =>
|
||||
state <= State_Mult4;
|
||||
when State_Mult4 =>
|
||||
state <= State_Mult5;
|
||||
when State_Mult5 =>
|
||||
stackA <= multResult3;
|
||||
state <= State_Mult6;
|
||||
when State_Mult6 =>
|
||||
if mem_busy='0' then
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= incIncSp;
|
||||
sp <= incSp;
|
||||
state <= State_Popped;
|
||||
end if;
|
||||
when State_BinaryOpResult =>
|
||||
if mem_busy='0' then
|
||||
-- NB!!!! we know that the memory isn't busy at this point!!!!
|
||||
out_mem_req <= '1';
|
||||
mem_addr <= incIncSp;
|
||||
sp <= incSp;
|
||||
stackA <= binaryOpResult;
|
||||
state <= State_Popped;
|
||||
end if;
|
||||
when State_Popped =>
|
||||
if mem_busy='0' then
|
||||
pc <= pc + 1;
|
||||
stackB <= mem_read;
|
||||
state <= State_Execute;
|
||||
end if;
|
||||
when others =>
|
||||
-- sp <= (others => DontCareValue);
|
||||
report "Illegal state" severity failure;
|
||||
break <= '1';
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
end behave;
|
||||
Reference in New Issue
Block a user