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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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lib/wishbone/settings_readback.v
-40
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@@ -1,40 +0,0 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
//
// Use this module in conjunction with settings_bus.v to add stateful reads
// to the settings bis. This enables you to do things like have registers reset atomicly
// as they are read. It also pipelines the address path to ease timing.
//
module settings_readback
#(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
(
input wb_clk,
input wb_rst,
input [AWIDTH-1:0] wb_adr_i,
input wb_stb_i,
input wb_we_i,
input [DWIDTH-1:0] rb_data,
output reg [RB_ADDRW-1:0] rb_addr,
output [DWIDTH-1:0] wb_dat_o,
output reg rb_rd_stb
);
always @(posedge wb_clk)
if (wb_stb_i && ~wb_we_i) begin
rb_addr <= wb_adr_i[RB_ADDRW+1:2];
rb_rd_stb <= 1'b1;
end else begin
rb_rd_stb <= 1'b0;
end
assign wb_dat_o = rb_data;
endmodule // settings_readback