Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,19 +0,0 @@
-#
-# Copyright 2010-2012 Ettus Research LLC
-#
-
-##################################################
-# Wishbone Perifs
-##################################################
-WISHBONE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wishbone/, \
-simple_uart_rx.v \
-simple_uart_tx.v \
-simple_uart.v \
-wb_1master.v \
-settings_bus.v \
-settings_readback.v \
-i2c_master_top.v \
-i2c_master_bit_ctrl.v \
-i2c_master_byte_ctrl.v \
-axi_stream_to_wb.v \
-))