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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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lib/timing/Makefile.srcs
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#
# Copyright 2013 Ettus Research LLC
#
##################################################
# Timing Sources
##################################################
TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
time_compare.v \
timekeeper.v \
pps.v\
))
lib/timing/pps.v
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//
// Copyright 2014 Ettus Research LLC
//
module pps_generator
#(parameter CLK_FREQ=0, DUTY=25)
(input clk, input reset, output pps);
reg[31:0] count;
always @(posedge clk) begin
if (reset) begin
count <= 32'b1;
end else if (count >= CLK_FREQ) begin
count <= 32'b1;
end else begin
count <= count + 1'b1;
end
end
assign pps = (count < CLK_FREQ * DUTY / 100);
endmodule //pps_generator
lib/timing/time_compare.v
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//
// Copyright 2011-2012 Ettus Research LLC
//
// 64 bits worth of ticks
//
// Not concerned with clock wrapping, human race will likely have extermintated it's self by this time.
//
module time_compare
(
input clk,
input reset,
input [63:0] time_now,
input [63:0] trigger_time,
output now,
output early,
output late,
output too_early);
/*
reg [63:0] time_diff;
always @(posedge clk) begin
if (reset) begin
time_diff <= 64'b0;
now <= 1'b0;
late <= 1'b0;
early <= 1'b0;
end
else begin
time_diff <= trigger_time - time_now;
now <= ~(|time_diff);
late <= time_diff[63];
early <= ~now & ~late;
end
end
//assign now = ~(|time_diff);
//assign late = time_diff[63];
//assign early = ~now & ~late;
assign too_early = 0; //not implemented
*/
assign now = time_now == trigger_time;
assign late = time_now > trigger_time;
assign early = ~now & ~late;
assign too_early = 0; //not implemented
endmodule // time_compare
lib/timing/time_transfer_tb.v
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//
// Copyright 2011 Ettus Research LLC
//
`timescale 1ns / 1ps
module time_transfer_tb();
reg clk = 0, rst = 1;
always #5 clk = ~clk;
initial
begin
@(negedge clk);
@(negedge clk);
rst <= 0;
end
initial $dumpfile("time_transfer_tb.vcd");
initial $dumpvars(0,time_transfer_tb);
initial #100000000 $finish;
wire exp_time, pps, pps_rcv;
wire [63:0] vita_time_rcv;
reg [63:0] vita_time = 0;
reg [63:0] counter = 0;
localparam PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
always @(posedge clk)
if(counter == PPS_PERIOD)
counter <= 0;
else
counter <= counter + 1;
assign pps = (counter == (PPS_PERIOD-1));
always @(posedge clk)
vita_time <= vita_time + 1;
time_sender time_sender
(.clk(clk),.rst(rst),
.vita_time(vita_time),
.send_sync(pps),
.exp_time_out(exp_time) );
time_receiver time_receiver
(.clk(clk),.rst(rst),
.vita_time(vita_time_rcv),
.sync_rcvd(pps_rcv),
.exp_time_in(exp_time) );
wire [31:0] delta = vita_time - vita_time_rcv;
endmodule // time_transfer_tb
lib/timing/timekeeper.v
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//
// Copyright 2013-2014 Ettus Research LLC
//
module timekeeper
#(parameter BASE = 0)
(input clk, input reset, input pps,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
output reg [63:0] vita_time, output reg [63:0] vita_time_lastpps);
//////////////////////////////////////////////////////////////////////////
// timer settings for this module
//////////////////////////////////////////////////////////////////////////
wire [63:0] time_at_next_event;
wire set_time_pps, set_time_now;
wire cmd_trigger;
setting_reg #(.my_addr(BASE), .width()) sr_time_hi
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(time_at_next_event[63:32]), .changed());
setting_reg #(.my_addr(BASE+1), .width()) sr_time_lo
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(time_at_next_event[31:0]), .changed());
setting_reg #(.my_addr(BASE+2), .width(2)) sr_ctrl
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out({set_time_pps, set_time_now}), .changed(cmd_trigger));
//////////////////////////////////////////////////////////////////////////
// PPS edge detection logic
//////////////////////////////////////////////////////////////////////////
reg pps_del, pps_del2;
always @(posedge clk)
{pps_del2,pps_del} <= {pps_del, pps};
wire pps_edge = !pps_del2 & pps_del;
//////////////////////////////////////////////////////////////////////////
// arm the trigger to latch a new time when the ctrl register is written
//////////////////////////////////////////////////////////////////////////
reg armed;
wire time_event = armed && ((set_time_now) || (set_time_pps && pps_edge));
always @(posedge clk) begin
if (reset) armed <= 1'b0;
else if (cmd_trigger) armed <= 1'b1;
else if (time_event) armed <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////
// vita time tracker - update every tick or when we get an "event"
//////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if(reset)
vita_time <= 64'h0;
else if (time_event)
vita_time <= time_at_next_event;
else
vita_time <= vita_time + 64'h1;
//////////////////////////////////////////////////////////////////////////
// track the time at last pps so host can detect the pps
//////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if(reset)
vita_time_lastpps <= 64'h0;
else if(pps_edge)
if(time_event)
vita_time_lastpps <= time_at_next_event;
else
vita_time_lastpps <= vita_time + 64'h1;
endmodule // timekeeper