Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,26 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-
-
-
-
-module delay_line
-  #(parameter WIDTH=32)
-   (input clk,
-    input [3:0] delay,
-    input [WIDTH-1:0] din,
-    output [WIDTH-1:0] dout);
-    
-   genvar 	       i;
-   generate
-      for (i=0;i<WIDTH;i=i+1)
-	begin : gen_delay
-	   SRL16E
-	     srl16e(.Q(dout[i]),
-		    .A0(delay[0]),.A1(delay[1]),.A2(delay[2]),.A3(delay[3]),
-		    .CE(1),.CLK(clk),.D(din[i]));
-	end
-   endgenerate
-
-endmodule // delay_line