Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,27 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-
-
-
-module srl
-  #(parameter WIDTH=18)
-    (input clk,
-     input rst,
-     input write,
-     input [WIDTH-1:0] in,
-     input [3:0] addr,
-     output [WIDTH-1:0] out);
-   
-   genvar 		i;
-   generate
-      for (i=0;i<WIDTH;i=i+1)
-	begin : gen_srl
-	   SRL16E
-	     srl16e(.Q(out[i]),
-		    .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
-		    .CE(write|rst),.CLK(clk),.D(in[i]));
-	end
-   endgenerate
-
-endmodule // srl