Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,23 +0,0 @@
-// -*- verilog -*-
-//
-//  USRP - Universal Software Radio Peripheral
-//
-//  Copyright (C) 2003 Matt Ettus
-//
-
-//
-
-
-// Sign extension "macro"
-// bits_out should be greater than bits_in
-
-module sign_extend (in,out);
-	parameter bits_in=0;  // FIXME Quartus insists on a default
-	parameter bits_out=0;
-	
-	input [bits_in-1:0] in;
-	output [bits_out-1:0] out;
-	
-	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
-	
-endmodule