miegl/b210-k7-fpga
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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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lib/dsp/round_sd.v
-23
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@@ -1,23 +0,0 @@
module round_sd
#(parameter WIDTH_IN=18,
parameter WIDTH_OUT=16,
parameter DISABLE_SD=0)
(input clk, input reset,
input [WIDTH_IN-1:0] in, input strobe_in,
output [WIDTH_OUT-1:0] out, output strobe_out);
localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
wire [ERR_WIDTH-1:0] err;
wire [WIDTH_IN-1:0] err_ext, sum;
sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
(.clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : 0), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out));
round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
endmodule // round_sd