Removed copy of FPGA source files.
Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
@@ -1,177 +0,0 @@
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//
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// Copyright 2011 Ettus Research LLC
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//
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// Final halfband decimator
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// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
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// Strobe in cannot come faster than every 2nd clock cycle
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// These taps designed by halfgen4 from ldoolittle
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// myfilt = round(2^18 * halfgen4(.7/4,8))
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module hb_dec
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#(parameter WIDTH=24)
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(input clk,
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input rst,
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input bypass,
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input run,
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input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block
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input stb_in,
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input [WIDTH-1:0] data_in,
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output reg stb_out,
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output reg [WIDTH-1:0] data_out);
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localparam INTWIDTH = 17;
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localparam ACCWIDTH = WIDTH + 3;
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// Round off inputs to 17 bits because of 18 bit multipliers
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wire [INTWIDTH-1:0] data_rnd;
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wire stb_rnd;
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round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
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(.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
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// Control
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reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
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wire write_odd, write_even, do_mult;
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reg odd;
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reg [2:0] phase, phase_d1;
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reg stb_out_int;
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wire clear, do_acc;
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assign do_mult = 1;
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always @(posedge clk)
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if(rst | ~run)
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odd <= 0;
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else if(stb_rnd)
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odd <= ~odd;
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assign write_odd = stb_rnd & odd;
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assign write_even = stb_rnd & ~odd;
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always @(posedge clk)
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if(rst | ~run)
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phase <= 0;
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else if(stb_rnd & odd)
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phase <= 1;
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else if(phase == 4)
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phase <= 0;
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else if(phase != 0)
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phase <= phase + 1;
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always @(posedge clk)
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phase_d1 <= phase;
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reg [15:0] stb_out_pre;
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always @(posedge clk)
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if(rst)
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stb_out_pre <= 0;
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else
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stb_out_pre <= {stb_out_pre[14:0],(stb_rnd & odd)};
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always @*
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case(phase)
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1 : begin addr_odd_a = 0; addr_odd_b = 15; end
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2 : begin addr_odd_a = 1; addr_odd_b = 14; end
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3 : begin addr_odd_a = 2; addr_odd_b = 13; end
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4 : begin addr_odd_a = 3; addr_odd_b = 12; end
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default : begin addr_odd_a = 0; addr_odd_b = 15; end
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endcase // case(phase)
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always @*
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case(phase)
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1 : begin addr_odd_c = 4; addr_odd_d = 11; end
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2 : begin addr_odd_c = 5; addr_odd_d = 10; end
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3 : begin addr_odd_c = 6; addr_odd_d = 9; end
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4 : begin addr_odd_c = 7; addr_odd_d = 8; end
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default : begin addr_odd_c = 4; addr_odd_d = 11; end
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endcase // case(phase)
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assign do_acc = |stb_out_pre[6:3];
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assign clear = stb_out_pre[3];
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// Data
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wire [INTWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
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reg [INTWIDTH:0] sum1, sum2; // these are 18-bit inputs to mult
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reg [WIDTH:0] final_sum;
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wire [WIDTH-1:0] final_sum_clip;
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reg [17:0] coeff1, coeff2;
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wire [35:0] prod1, prod2;
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always @* // Outer coeffs
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case(phase_d1)
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1 : coeff1 = -107;
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2 : coeff1 = 445;
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3 : coeff1 = -1271;
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4 : coeff1 = 2959;
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default : coeff1 = -107;
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endcase // case(phase)
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always @* // Inner coeffs
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case(phase_d1)
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1 : coeff2 = -6107;
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2 : coeff2 = 11953;
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3 : coeff2 = -24706;
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4 : coeff2 = 82359;
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default : coeff2 = -6107;
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endcase // case(phase)
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srl #(.WIDTH(INTWIDTH)) srl_odd_a
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(.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_a),.out(data_odd_a));
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srl #(.WIDTH(INTWIDTH)) srl_odd_b
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(.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_b),.out(data_odd_b));
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srl #(.WIDTH(INTWIDTH)) srl_odd_c
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(.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_c),.out(data_odd_c));
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srl #(.WIDTH(INTWIDTH)) srl_odd_d
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(.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_d),.out(data_odd_d));
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always @(posedge clk) sum1 <= {data_odd_a[INTWIDTH-1],data_odd_a} + {data_odd_b[INTWIDTH-1],data_odd_b};
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always @(posedge clk) sum2 <= {data_odd_c[INTWIDTH-1],data_odd_c} + {data_odd_d[INTWIDTH-1],data_odd_d};
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wire [INTWIDTH-1:0] data_even;
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reg [3:0] addr_even;
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always @(posedge clk)
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case(cpi)
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// 1 is an error
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2 : addr_even <= 9; // Maximum speed (overall decim by 4)
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3, 4, 5, 6, 7 : addr_even <= 8;
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default : addr_even <= 7;
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endcase // case(cpi)
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srl #(.WIDTH(INTWIDTH)) srl_even
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(.clk(clk),.write(write_even),.in(data_rnd),.addr(addr_even),.out(data_even));
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MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
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MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
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reg [35:0] sum_of_prod;
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always @(posedge clk) sum_of_prod <= prod1 + prod2; // Can't overflow
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wire [ACCWIDTH-1:0] acc_out;
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acc #(.IWIDTH(ACCWIDTH-2),.OWIDTH(ACCWIDTH))
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acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod[35:38-ACCWIDTH]),.out(acc_out));
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wire [ACCWIDTH-1:0] data_even_signext;
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localparam SHIFT_FACTOR = 6;
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sign_extend #(.bits_in(INTWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) signext_data_even
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(.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
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assign data_even_signext[SHIFT_FACTOR-1:0] = 0;
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always @(posedge clk) final_sum <= acc_out + data_even_signext;
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clip #(.bits_in(WIDTH+1), .bits_out(WIDTH)) clip (.in(final_sum), .out(final_sum_clip));
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// Output MUX to allow for bypass
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wire selected_stb = bypass ? stb_in : stb_out_pre[8];
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always @(posedge clk)
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begin
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stb_out <= selected_stb;
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if(selected_stb)
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data_out <= bypass ? data_in : final_sum_clip;
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end
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endmodule // hb_dec
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