Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,24 +0,0 @@
-// -*- verilog -*-
-//
-//  USRP - Universal Software Radio Peripheral
-//
-//  Copyright (C) 2008 Matt Ettus
-//
-
-//
-
-// Clipping "macro", keeps the bottom bits
-
-module clip
-  #(parameter bits_in=0,
-    parameter bits_out=0)
-    (input [bits_in-1:0] in,
-     output [bits_out-1:0] out);
-   
-   wire 		   overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]);   
-   assign 		   out = overflow ? 
-			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
-			   in[bits_out-1:0];
-   
-endmodule // clip
-