Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,12 +0,0 @@
-
-module add2_and_clip
-  #(parameter WIDTH=16)
-    (input [WIDTH-1:0] in1,
-     input [WIDTH-1:0] in2,
-     output [WIDTH-1:0] sum);
-
-   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
-   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip
-     (.in(sum_int),.out(sum));
-   
-endmodule // add2_and_clip