Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,33 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-
-
-
-module acc
-  #(parameter IWIDTH=16, OWIDTH=30)
-    (input clk,
-     input clear,
-     input acc,
-     input [IWIDTH-1:0] in,
-     output reg [OWIDTH-1:0] out);
-
-   wire [OWIDTH-1:0] in_signext;
-   sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) 
-     acc_signext (.in(in),.out(in_signext));
-   
-   //  CLEAR & ~ACC  -->  clears the accumulator
-   //  CLEAR & ACC -->    loads the accumulator
-   //  ~CLEAR & ACC -->   accumulates
-   //  ~CLEAR & ~ACC -->  hold
-   
-   wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
-   wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
-   wire [OWIDTH-1:0] sum_int = addend1 + addend2;
-
-   always @(posedge clk)
-     out <= sum_int;
-   
-endmodule // acc
-
-