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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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lib/control/reset_sync.v
-28
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@@ -1,28 +0,0 @@
//
// Copyright 2011 Ettus Research LLC
//
module reset_sync
(input clk,
input reset_in,
output reset_out);
reg reset_int;
reg reset_out_tmp;
//synthesis attribute async_reg of reset_out_tmp is "true";
//synthesis attribute async_reg of reset_int is "true";
always @(posedge clk or posedge reset_in)
if(reset_in)
{reset_out_tmp,reset_int} <= 2'b11;
else
{reset_out_tmp,reset_int} <= {reset_int,1'b0};
assign reset_out = reset_out_tmp;
endmodule // reset_sync