Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,25 +0,0 @@
-//
-// Copyright 2013 Ettus Research LLC
-//
-
-
-
-module por_gen
-  (input clk,
-   output reset_out);
-
-   reg 		por_rst;
-   reg [7:0] 	por_counter = 8'h0;
-
-   always @(posedge clk)
-     if (por_counter != 8'h55)
-       begin
-          por_counter <= por_counter + 8'h1;
-          por_rst <= 1'b1;
-       end
-     else
-       por_rst <= 1'b0;
-
-   assign reset_out = por_rst;
-
-endmodule // por_gen