Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,28 +0,0 @@
-#
-# Copyright 2013 Ettus Research LLC
-#
-
-##################################################
-# Control Lib Sources
-##################################################
-CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
-reset_sync.v \
-por_gen.v \
-gpio_atr.v \
-simple_spi_core.v \
-simple_i2c_core.v \
-setting_reg.v \
-settings_bus_crossclock.v \
-radio_ctrl_proc.v \
-ram_2port.v \
-axi_crossbar.v \
-axi_slave_mux.v \
-axi_fifo_header.v \
-arb_qualify_master.v \
-axi_forwarding_cam.v \
-axi_test_vfifo.v \
-dram_2port.v \
-cvita_uart.v \
-serial_to_settings.v \
-filter_bad_sid.v \
-))