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fpga: x440: fix refactored rf_core_full

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Original-commit: f1fab29e4444476378faa8d435c1f76faa5a702c
This commit is contained in:
Max Köhler
2025-02-13 07:58:10 -06:00
committed by Wade Fife
parent 3ed06cc861
commit 7446db939c
1 changed files with 12 additions and 5 deletions
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top/x400/rf/full/rf_core_full.sv
+12 -5
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@@ -53,8 +53,8 @@ module rf_core_full # (
// DAC // DAC
output wire [32*RADIO_SPC-1:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1], output wire [32*RADIO_SPC-1:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1],
input wire [NUM_ADC_CHANNELS-1:0] dac_data_out_tready, input wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tready,
output wire [NUM_ADC_CHANNELS-1:0] dac_data_out_tvalid, output wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tvalid,
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// User Data Interfaces // User Data Interfaces
@@ -68,8 +68,8 @@ module rf_core_full # (
// DAC // DAC
input wire [32*RADIO_SPC-1:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1], input wire [32*RADIO_SPC-1:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1],
output wire [NUM_ADC_CHANNELS-1:0] dac_data_in_tready, output wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tready,
input wire [NUM_ADC_CHANNELS-1:0] dac_data_in_tvalid, input wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tvalid,
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Miscellaneous // Miscellaneous
@@ -77,7 +77,7 @@ module rf_core_full # (
// Invert I/Q control signals from RFDC to DSP chain. // Invert I/Q control signals from RFDC to DSP chain.
input wire [NUM_ADC_CHANNELS-1:0] invert_adc_iq_rclk, input wire [NUM_ADC_CHANNELS-1:0] invert_adc_iq_rclk,
input wire [NUM_ADC_CHANNELS-1:0] invert_dac_iq_rclk, input wire [NUM_DAC_CHANNELS-1:0] invert_dac_iq_rclk,
// Control/status vectors from/to RFDC. // Control/status vectors from/to RFDC.
// Notice these are all in the s_axi_config_clk domain. // Notice these are all in the s_axi_config_clk domain.
@@ -146,6 +146,13 @@ module rf_core_full # (
// ADC Post-Processing // ADC Post-Processing
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// There is no tready going to the ADC (one has to be always ready for ADC
// data), but it is still a component of the axi_status vector as a generic
// AXI stream status. Report 1'b1 to the status vector consistent with being
// always ready.
assign adc_data_in_i_tready = '1;
assign adc_data_in_q_tready = '1;
// ADC Data from the RFDC arrives here with separate I and Q // ADC Data from the RFDC arrives here with separate I and Q
// streams. It gets combined to a single stream. // streams. It gets combined to a single stream.
for (genvar adc_num = 0; adc_num < (NUM_ADC_CHANNELS); adc_num++) for (genvar adc_num = 0; adc_num < (NUM_ADC_CHANNELS); adc_num++)