fpga: lib: Add zero-length option to axi_fifo
Original-commit: 6ea4e4808e09e55bb2ba05e787e79ec3c5fe4340
This commit is contained in:
Wade Fife
+131
-62
@@ -1,71 +1,140 @@
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//
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// Copyright 2012-2014 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi_fifo
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//
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// Description:
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//
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// General FIFO block
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//
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// Parameters:
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//
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// WIDTH : Width of tdata in bits
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// SIZE : Log base 2 of the depth of the FIFO. In other words, the size of
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// the FIFO is 2**SIZE elements deep. The implementation changes
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// depending on the FIFO size, as described below.
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//
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// SIZE < 0 : No FIFO (data passes through without any buffer)
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// SIZE == 0 : Uses a single stage flop (axi_fifo_flop)
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// SIZE == 1 : Uses a two-stage flop (axi_fifo_flop2). Best choice for single
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// stage pipelining. Breaks combinatorial paths on the AXI stream
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// data / control lines at the cost of additional registers. Maps
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// to SLICELs (i.e. does not use distributed RAM).
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// SIZE <= 5 : Uses SRL32 to efficient maps a 32 deep FIFO to SLICEMs
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// (axi_fifo_short). Not recommended for pipelining as most
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// devices have twice as many SLICELs as SLICEMs.
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// SIZE > 5 : Uses BRAM FIFO (axi_fifo_bram)
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//
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// General FIFO block
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// Size == 0: Uses a single stage flop (axi_fifo_flop).
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// Size == 1: Uses a two stage flop (axi_fifo_flop2). Best choice for single stage pipelining.
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// Breaks combinatorial paths on the AXI stream data / control lines at the cost of
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// additional registers. Maps to SLICELs (i.e. does not use distributed RAM).
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// Size <= 5: Uses SRL32 to efficient maps a 32 deep FIFO to SLICEMs (axi_fifo_short). Not
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// recommended for pipelining as most devices have twice as many SLICELs as SLICEMs.
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// Size > 5: Uses BRAM fifo (axi_fifo_bram)
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`default_nettype none
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module axi_fifo #(
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parameter WIDTH = 32,
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parameter SIZE = 5
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) (
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input wire clk,
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input wire reset,
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input wire clear,
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input wire [WIDTH-1:0] i_tdata,
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input wire i_tvalid,
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output wire i_tready,
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output wire [WIDTH-1:0] o_tdata,
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output wire o_tvalid,
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input wire o_tready,
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output wire [ 15:0] space,
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output wire [ 15:0] occupied
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);
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module axi_fifo
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#(parameter WIDTH=32, SIZE=5)
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(input clk, input reset, input clear,
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input [WIDTH-1:0] i_tdata,
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input i_tvalid,
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output i_tready,
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output [WIDTH-1:0] o_tdata,
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output o_tvalid,
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input o_tready,
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output [15:0] space,
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output [15:0] occupied);
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generate
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if(SIZE==0)
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begin
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axi_fifo_flop #(.WIDTH(WIDTH)) fifo_flop
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(space[0]), .occupied(occupied[0]));
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assign space[15:1] = 15'd0;
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assign occupied[15:1] = 15'd0;
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end
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else if(SIZE==1)
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begin
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axi_fifo_flop2 #(.WIDTH(WIDTH)) fifo_flop2
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(space[1:0]), .occupied(occupied[1:0]));
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assign space[15:2] = 14'd0;
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assign occupied[15:2] = 14'd0;
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end
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else if(SIZE<=5)
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begin
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axi_fifo_short #(.WIDTH(WIDTH)) fifo_short
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(space[5:0]), .occupied(occupied[5:0]));
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assign space[15:6] = 10'd0;
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assign occupied[15:6] = 10'd0;
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end
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else
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begin
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axi_fifo_bram #(.WIDTH(WIDTH), .SIZE(SIZE)) fifo_bram
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(space), .occupied(occupied));
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end
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if (SIZE < 0) begin : gen_no_fifo
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assign o_tdata = i_tdata;
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assign o_tvalid = i_tvalid;
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assign i_tready = o_tready;
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end
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if (SIZE == 0) begin : gen_fifo_flop
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axi_fifo_flop #(
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.WIDTH(WIDTH)
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) fifo_flop (
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.clk (clk),
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.reset (reset),
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.clear (clear),
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.i_tdata (i_tdata),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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.o_tdata (o_tdata),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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.space (space[0]),
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.occupied(occupied[0])
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);
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assign space[15:1] = 15'd0;
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assign occupied[15:1] = 15'd0;
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end
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else if (SIZE == 1) begin : gen_fifo_flop2
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axi_fifo_flop2 #(
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.WIDTH(WIDTH)
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) fifo_flop2 (
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.clk (clk),
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.reset (reset),
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.clear (clear),
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.i_tdata (i_tdata),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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.o_tdata (o_tdata),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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.space (space[1:0]),
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.occupied(occupied[1:0])
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);
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assign space[15:2] = 14'd0;
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assign occupied[15:2] = 14'd0;
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end
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else if (SIZE <= 5) begin : gen_fifo_short
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axi_fifo_short #(
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.WIDTH(WIDTH)
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) fifo_short (
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.clk (clk),
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.reset (reset),
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.clear (clear),
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.i_tdata (i_tdata),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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.o_tdata (o_tdata),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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.space (space[5:0]),
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.occupied(occupied[5:0])
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);
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assign space[15:6] = 10'd0;
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assign occupied[15:6] = 10'd0;
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end
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else begin : gen_fifo_bram
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axi_fifo_bram #(
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.WIDTH(WIDTH),
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.SIZE (SIZE)
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) fifo_bram (
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.clk (clk),
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.reset (reset),
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.clear (clear),
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.i_tdata (i_tdata),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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.o_tdata (o_tdata),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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.space (space),
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.occupied(occupied)
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);
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end
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endgenerate
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endmodule // axi_fifo
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`default_nettype wire
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