fpga: x400: Change NUM_DRAM_BANKS to 2 on X410 X4_400 image
This was set to 1 in UHD 4.7, but it must be 2 for all channels to have sufficient bandwidth. Original-commit: b012c18fd653714e84b1d4a86e27ff90fe13ae04
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@@ -1,15 +1,15 @@
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# General parameters
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# General parameters
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# -----------------------------------------
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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version: '1.0' # File version
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chdr_width: 128 # Bit width of the CHDR bus for this image
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chdr_width: 128 # Bit width of the CHDR bus for this image
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device: 'x410' # USRP type
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device: 'x410' # USRP type
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image_core_name: 'usrp_x410_fpga_X4_400'# Name to use for the RFNoC Image Core files
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image_core_name: 'usrp_x410_fpga_X4_400' # Name to use for the RFNoC Image Core files
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default_target: 'X410' # Default make target
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default_target: 'X410' # Default make target
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inherit:
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inherit:
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- 'yaml_include/x410_radio_base.yml'
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- 'yaml_include/x410_radio_base.yml'
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- 'yaml_include/x4xx_x4_base.yml'
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- 'yaml_include/x4xx_x4_base.yml'
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@@ -17,7 +17,7 @@ inherit:
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parameters:
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parameters:
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RF_BW: 400
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RF_BW: 400
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ENABLE_DRAM: True
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ENABLE_DRAM: True
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NUM_DRAM_BANKS: 1
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NUM_DRAM_BANKS: 2
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NUM_DRAM_CHANS: 4
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NUM_DRAM_CHANS: 4
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DRAM_WIDTH: 128
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DRAM_WIDTH: 128
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