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fpga: Align build process for all targets

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- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
2024-06-11 10:20:08 +02:00
committed by Joerg Hofrichter
parent ba5e431c5c
commit 6ef3795e42
37 changed files with 527 additions and 9597 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/make/viv_design_builder.mak
+2
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@@ -20,6 +20,8 @@ SIMULATION = 0
# -------------------------------------------------------------------
BUILD_VIVADO_DESIGN = \
@ \
$(if $(BUILD_DIR),,$(error "BUILD_DIR" is not defined! Use rfnoc_image_builder to create valid commands)) \
$(if $(IMAGE_CORE_NAME),,$(error "IMAGE_CORE_NAME" is not defined! Use rfnoc_image_builder to create valid commands)) \
export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \
export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \
export VIV_TOP_MODULE=$(2); \
tools/make/viv_preamble.mak
+2 -11
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@@ -32,17 +32,6 @@ MAKEFILE_DIR = $(abspath .)
IP_BUILD_DIR ?= $(abspath ./build-ip/$(subst /,,$(PART_ID)))
BUILD_BASE_DIR ?= $(abspath .)
ifdef ARTIFACT_DIR
BUILD_DIR = $(abspath $(ARTIFACT_DIR))
else
ifdef NAME
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
else
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
endif
endif
# -------------------------------------------------------------------
# Git Hash Retrieval
# -------------------------------------------------------------------
@@ -80,7 +69,9 @@ endif
# Intermediate build dirs
# -------------------------------------------------------------------
.build_dirs:
ifdef BUILD_DIR
@mkdir -p $(BUILD_DIR)
endif
@mkdir -p $(IP_BUILD_DIR)
.prereqs: .check_tool .build_dirs
top/e31x/Makefile
+60 -28
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@@ -4,10 +4,18 @@
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP E3XX FPGA Help
##USRP E31X FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
## rfnoc_image_builder -y <image core file> -t <target> -n <image core name>
##
## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
## environment, and run Vivado to build a bitfile.
##
## There exist some special make targets which can be called directly like this:
##
## make <Targets> <Options>
##
##Output:
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
@@ -37,20 +45,18 @@ ifndef TARGET
endif
TOP ?= e31x
DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
# post_build($1=Device, $2=Option)
# post_build($1=Device)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream file..."; \
cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
cp $(BUILD_DIR)/e31x.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Exporting build report..."; \
cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(1)";
else
post_build = @echo "Skipping bitfile export."
@@ -59,50 +65,76 @@ endif
##
##Supported Targets
##-----------------
##Reminder: Targets are built by calling
##
## $ rfnoc_image_builder -y <image core file.yml> -t <target name> -n <image core name>
##
##The following table lists all valid combinations:
##
##--------------------------|---------------|-------------------------|------------------
## Default Image core file | Target | Image core name | Description
##--------------------------|---------------|-------------------------|------------------
##e310_rfnoc_image_core.yml | E310_SG1 | usrp_e310_sg1_fpga | E310 speedgrade 1
##e310_rfnoc_image_core.yml | E310_SG1_IDLE | usrp_e310_sg1_idle_fpga | E310 speedgrade 1, idle image
##e310_rfnoc_image_core.yml | E310_SG3 | usrp_e310_sg3_fpga | E310 speedgrade 3
##e310_rfnoc_image_core.yml | E310_SG3_IDLE | usrp_e310_sg3_idle_fpga | E310 speedgrade 3, idle image
##
##Of course, a custom YAML file may be used.
##
all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 ##(Default target)
##E310_SG1_IP: Build IP for E310_SG1 only.
E310_SG1_IP:
+$(call vivado_ip,E310_SG1,E310_SG1=1)
##E310_SG3_IP: Build IP for E310_SG3 only.
E310_SG3_IP:
+$(call vivado_ip,E310_SG3,E310_SG3=1)
check-variables:
ifndef IMAGE_CORE_NAME
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
endif
ifndef BUILD_DIR
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
endif
##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
E310_SG1_IDLE E3XX_idle: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
E310_SG1_IDLE E3XX_idle: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
$(call post_build,$@,E310_SG1_IDLE)
$(call post_build,$@)
##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
E310_SG3_IDLE E3XX_idle_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
$(call post_build,$@,E310_SG3_IDLE)
$(call post_build,$@)
##E310_SG1: Build USRP E3XX (Speed Grade 1).
E310_SG1 E310: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
E310_SG1 E310: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
$(call post_build,$@,E310_SG1)
$(call post_build,$@)
##E310_SG3: Build USRP E3XX (Speed Grade 3).
E310_SG3 E310_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
E310_SG3 E310_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
$(call post_build,$@,E310_SG3)
$(call post_build,$@)
$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
-mkdir -p $(BUILD_OUTPUT_DIR)
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
##
##Other Make Targets (these should be called directly)
##----------------------------------------------------
##E310_SG1_IP: Build IP for E310_SG1 only. Use the -j option to build multiple IP blocks simultaneously.
E310_SG1_IP:
+$(call vivado_ip,E310_SG1,E310_SG1=1)
##E310_SG3_IP: Build IP for E310_SG3 only. Use the -j option to build multiple IP blocks simultaneously.
E310_SG3_IP:
+$(call vivado_ip,E310_SG3,E310_SG3=1)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-E3*
@rm -rf $(BUILD_BASE_DIR)/build-E3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-E3*
@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
help: ##Show this help message.
top/e31x/Makefile.e31x.inc
+14 -18
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@@ -5,7 +5,7 @@
##################################################
# Project Setup
##################################################
TOP_MODULE = <Input arg>
# TOP_MODULE = <Input arg>
# NAME = <Input arg>
# PART_ID = <Input arg>
# ARCH = <Input arg>
@@ -32,22 +32,15 @@ include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/io_cap_gen/Makefile.srcs
include $(LIB_DIR)/rfnoc/Makefile.srcs
# For the sake of convenience, we include the Makefile.srcs for the DDC, DUC,
# radio, replay and FIFO blocks. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
ifdef BUILD_DIR
include $(BUILD_DIR)/Makefile.inc
endif
##################################################
# Sources
@@ -88,7 +81,6 @@ $(FIFO_SRCS) \
$(AURORA_PHY_SRCS) \
$(BD_SRCS) \
$(RADIO_SRCS) \
$(RFNOC_SRCS) \
$(TIMING_SRCS) \
$(VITA_SRCS) \
$(CAT_CAP_GEN_SRCS) \
@@ -99,25 +91,29 @@ $(LIB_IP_XCI_SRCS) \
$(LIB_HLS_IP_SRCS) \
$(EXTRAM_SRCS) \
$(CAP_GEN_GENERIC_SRCS) \
$(RFNOC_SRCS) \
$(RFNOC_OOT_SRCS)\
$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_EXAMPLE_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS) \
$(abspath $(MB_XDC))
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
top/e31x/e310_rfnoc_image_core.v
-572
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@@ -1,572 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_image_core (for e31x)
//
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: e310_rfnoc_image_core.yml
//
`default_nettype none
module rfnoc_image_core #(
parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) (
// Clocks
input wire chdr_aclk,
input wire ctrl_aclk,
input wire core_arst,
input wire radio_clk,
input wire dram_clk,
// Basic
input wire [ 15:0] device_id,
// IO ports /////////////////////////
// ctrlport
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [ 19:0] m_ctrlport_req_addr,
output wire [ 31:0] m_ctrlport_req_data,
output wire [ 3:0] m_ctrlport_req_byte_en,
output wire m_ctrlport_req_has_time,
output wire [ 63:0] m_ctrlport_req_time,
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 31:0] m_ctrlport_resp_data,
// time
input wire [ 63:0] radio_time,
// radio
input wire [ 63:0] radio_rx_data,
input wire [ 1:0] radio_rx_stb,
output wire [ 1:0] radio_rx_running,
output wire [ 63:0] radio_tx_data,
input wire [ 1:0] radio_tx_stb,
output wire [ 1:0] radio_tx_running,
// dram
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
output wire [ 23:0] m_axi_awsize,
output wire [ 15:0] m_axi_awburst,
output wire [ 7:0] m_axi_awlock,
output wire [ 31:0] m_axi_awcache,
output wire [ 23:0] m_axi_awprot,
output wire [ 31:0] m_axi_awqos,
output wire [ 31:0] m_axi_awregion,
output wire [ 7:0] m_axi_awuser,
output wire [ 7:0] m_axi_awvalid,
input wire [ 7:0] m_axi_awready,
output wire [4191:0] m_axi_wdata,
output wire [ 511:0] m_axi_wstrb,
output wire [ 7:0] m_axi_wlast,
output wire [ 7:0] m_axi_wuser,
output wire [ 7:0] m_axi_wvalid,
input wire [ 7:0] m_axi_wready,
input wire [ 7:0] m_axi_bid,
input wire [ 15:0] m_axi_bresp,
input wire [ 7:0] m_axi_buser,
input wire [ 7:0] m_axi_bvalid,
output wire [ 7:0] m_axi_bready,
output wire [ 7:0] m_axi_arid,
output wire [ 383:0] m_axi_araddr,
output wire [ 63:0] m_axi_arlen,
output wire [ 23:0] m_axi_arsize,
output wire [ 15:0] m_axi_arburst,
output wire [ 7:0] m_axi_arlock,
output wire [ 31:0] m_axi_arcache,
output wire [ 31:0] m_axi_arprot,
output wire [ 31:0] m_axi_arqos,
output wire [ 31:0] m_axi_arregion,
output wire [ 7:0] m_axi_aruser,
output wire [ 7:0] m_axi_arvalid,
input wire [ 7:0] m_axi_arready,
input wire [ 7:0] m_axi_rid,
input wire [4191:0] m_axi_rdata,
input wire [ 15:0] m_axi_rresp,
input wire [ 7:0] m_axi_rlast,
input wire [ 7:0] m_axi_ruser,
input wire [ 7:0] m_axi_rvalid,
output wire [ 7:0] m_axi_rready,
// Transport Adapters ///////////////
// Transport 0 (dma)
input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast,
input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
);
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
//---------------------------------------------------------------------------
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
chdr_crossbar_nxn #(
.PORT_W (PORT_W),
.NPORTS (3),
.CHDR_WIDTHS ({EP1_W, EP0_W, DMA_W}),
.DEFAULT_PORT (0),
.ROUTES ({ 3'b111,
3'b111,
3'b111 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (1),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
.s_axis_tdata ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata }),
.s_axis_tlast ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast }),
.s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}),
.s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}),
.m_axis_tdata ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata }),
.m_axis_tlast ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast }),
.m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}),
.m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}),
.ext_rtcfg_stb (1'h0),
.ext_rtcfg_addr (16'h0),
.ext_rtcfg_data (32'h0),
.ext_rtcfg_ack ()
);
//---------------------------------------------------------------------------
// Stream Endpoints
//---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep0_tdata),
.s_axis_chdr_tlast (xb_to_ep0_tlast),
.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
.s_axis_chdr_tready (xb_to_ep0_tready),
.m_axis_chdr_tdata (ep0_to_xb_tdata),
.m_axis_chdr_tlast (ep0_to_xb_tlast),
.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
.m_axis_chdr_tready (ep0_to_xb_tready),
.s_axis_data_tdata ({s_ep0_in0_tdata}),
.s_axis_data_tlast ({s_ep0_in0_tlast}),
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
.s_axis_data_tready ({s_ep0_in0_tready}),
.m_axis_data_tdata ({m_ep0_out0_tdata}),
.m_axis_data_tlast ({m_ep0_out0_tlast}),
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
.m_axis_data_tready ({m_ep0_out0_tready}),
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep1_tdata),
.s_axis_chdr_tlast (xb_to_ep1_tlast),
.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
.s_axis_chdr_tready (xb_to_ep1_tready),
.m_axis_chdr_tdata (ep1_to_xb_tdata),
.m_axis_chdr_tlast (ep1_to_xb_tlast),
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
.m_axis_chdr_tready (ep1_to_xb_tready),
.s_axis_data_tdata ({s_ep1_in0_tdata}),
.s_axis_data_tlast ({s_ep1_in0_tlast}),
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
.s_axis_data_tready ({s_ep1_in0_tready}),
.m_axis_data_tdata ({m_ep1_out0_tdata}),
.m_axis_data_tlast ({m_ep1_out0_tlast}),
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
.m_axis_data_tready ({m_ep1_out0_tready}),
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
//---------------------------------------------------------------------------
// Control Crossbar
//---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
wire m_core_ctrl_tready, s_core_ctrl_tready;
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
axis_ctrl_crossbar_nxn #(
.WIDTH (32),
.NPORTS (3),
.TOPOLOGY ("TORUS"),
.INGRESS_BUFF_SIZE(5),
.ROUTER_BUFF_SIZE (5),
.ROUTING_ALLOC ("WORMHOLE"),
.SWITCH_ALLOC ("PRIO")
) ctrl_xb_i (
.clk (rfnoc_ctrl_clk),
.reset (rfnoc_ctrl_rst),
.s_axis_tdata ({m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.deadlock_detected()
);
//---------------------------------------------------------------------------
// RFNoC Core Kernel
//---------------------------------------------------------------------------
wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #(
.PROTOVER (PROTOVER),
.DEVICE_TYPE (16'hE310),
.DEVICE_FAMILY ("7SERIES"),
.SAFE_START_CLKS (0),
.NUM_BLOCKS (1),
.NUM_STREAM_ENDPOINTS(2),
.NUM_ENDPOINTS_CTRL (1),
.NUM_TRANSPORTS (1),
.NUM_EDGES (4),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL ({
{10'd03, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd03, 6'd01},
{10'd03, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd03, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
.ctrl_aclk (ctrl_aclk),
.ctrl_aclk_locked (1'b1),
.core_arst (core_arst),
.core_chdr_clk (rfnoc_chdr_clk),
.core_chdr_rst (rfnoc_chdr_rst),
.core_ctrl_clk (rfnoc_ctrl_clk),
.core_ctrl_rst (rfnoc_ctrl_rst),
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
.s_axis_ctrl_tready (s_core_ctrl_tready),
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
.m_axis_ctrl_tready (m_core_ctrl_tready),
.device_id (device_id),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
//---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [32*RADIO_NIPC*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*RADIO_NIPC*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (RADIO_NIPC),
.ITEM_W (32),
.MTU (BLOCK_MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
.radio_time (radio0_radio_time),
.radio_rx_data (radio0_radio_rx_data),
.radio_rx_stb (radio0_radio_rx_stb),
.radio_rx_running (radio0_radio_rx_running),
.radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
//---------------------------------------------------------------------------
// Static Router
//---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready;
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready;
assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
assign m_ep1_out0_tready = s_radio0_in_1_tready;
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
assign m_radio0_out_1_tready = s_ep1_in0_tready;
//---------------------------------------------------------------------------
// Unused Ports
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
//---------------------------------------------------------------------------
// IO Port Connection
//---------------------------------------------------------------------------
// Master/Slave Connections:
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
assign m_ctrlport_req_addr = radio0_m_ctrlport_req_addr;
assign m_ctrlport_req_data = radio0_m_ctrlport_req_data;
assign m_ctrlport_req_byte_en = radio0_m_ctrlport_req_byte_en;
assign m_ctrlport_req_has_time = radio0_m_ctrlport_req_has_time;
assign m_ctrlport_req_time = radio0_m_ctrlport_req_time;
assign radio0_m_ctrlport_resp_ack = m_ctrlport_resp_ack;
assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
assign radio0_radio_rx_data = radio_rx_data;
assign radio0_radio_rx_stb = radio_rx_stb;
assign radio_rx_running = radio0_radio_rx_running;
assign radio_tx_data = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb;
assign radio_tx_running = radio0_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
endmodule
`default_nettype wire
top/e31x/e310_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for e31x)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: e310_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/e31x/e310_rfnoc_image_core.yml
+3 -1
View File
@@ -8,8 +8,10 @@ license: >- # License information used in file heade
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'e310' # USRP type
image_core_name: 'e310' # Name to use for the RFNoC Image Core files
default_target: 'E310_SG3'
image_core_name: 'usrp_e310_sg3_fpga' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/e320/Makefile
+52 -24
View File
@@ -4,10 +4,18 @@
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP E3XX FPGA Help
##USRP E32X FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
## rfnoc_image_builder -y <image core file> -t <target>
##
## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
## environment, and run Vivado to build a bitfile.
##
## There exist some special make targets which can be called directly like this:
##
## make <Targets> <Options>
##
##Output:
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
@@ -40,21 +48,19 @@ ifndef TARGET
endif
TOP ?= e320
DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
# post_build($1=Device, $2=Option)
# post_build($1=Target)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream file..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/e320.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_DIR)/e320.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Exporting build report..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(1)";
else
post_build = @echo "Skipping bitfile export."
endif
@@ -62,42 +68,64 @@ endif
##
##Supported Targets
##-----------------
##
##Reminder: Targets are built by calling
##
## $ rfnoc_image_builder -y <image core file.yml> -t <target>
##
##The default image core file is called e320_rfnoc_image_core.yml.
##Of course, a custom YAML file may be used.
##
##Example:
## $ rfnoc_image_builder -y e320_rfnoc_image_core.yml --target E320_XG
##will build the E320_XG target (10-Gigabit Ethernet on the SFP+ port).
##
##The following targets are supported:
all: E320_1G E320_XG ##(Default target)
##E320_IP: Build IP for E320 only.
E320_IP:
+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
check-variables:
ifndef IMAGE_CORE_NAME
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
endif
ifndef BUILD_DIR
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
endif
##E320_1G: 1GigE on SFP+ Port.
E320_1G: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
E320_1G: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
$(call vivado_build,E320,$(1G_DEFS) E320=1)
$(call post_build,E320,1G)
$(call post_build,E320_1G)
##E320_XG: 10GigE on SFP+ Port.
E320_XG: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
E320_XG: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
$(call vivado_build,E320,$(XG_DEFS) E320=1)
$(call post_build,E320,XG)
$(call post_build,E320_XG)
##E320_AA: Aurora on SFP+ Port.
E320_AA: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
E320_AA: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
$(call vivado_build,E320,$(AA_DEFS) E320=1)
$(call post_build,E320,AA)
$(call post_build,E320_AA)
$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
-mkdir -p $(BUILD_OUTPUT_DIR)
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
##
##Other Make Targets (these should be called directly)
##----------------------------------------------------
##E320_IP: Build IP for E320 only. Use the -j option to build multiple IP blocks simultaneously.
E320_IP:
+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
@rm -rf $(BUILD_BASE_DIR)/build-E3*_* $(BUILD_BASE_DIR)/build-e3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
@rm -rf $(BUILD_OUTPUT_DIR)
@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR) $(BUILD_DIR)
help: ##Show this help message.
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
top/e320/Makefile.e320.inc
+11 -16
View File
@@ -5,7 +5,7 @@
##################################################
# Project Setup
##################################################
TOP_MODULE = <Input arg>
# TOP_MODULE = <Input arg>
# NAME = <Input arg>
# PART_ID = <Input arg>
# ARCH = <Input arg>
@@ -36,21 +36,15 @@ include $(LIB_DIR)/rfnoc/Makefile.srcs
include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
ifdef BUILD_DIR
include $(BUILD_DIR)/Makefile.inc
endif
##################################################
# Sources
@@ -117,23 +111,24 @@ $(CAP_GEN_GENERIC_SRCS) \
$(RFNOC_SRCS) \
$(RFNOC_OOT_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
$(RFNOC_BLOCK_RADIO_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
$(abspath $(MB_XDC))
$(abspath $(MB_XDC)) \
$(RFNOC_IMAGE_CORE_SRCS)
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e320.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
top/e320/e320_rfnoc_image_core.v
-1090
View File
File diff suppressed because it is too large Load Diff
top/e320/e320_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for e320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: e320_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/e320/e320_rfnoc_image_core.yml
+4 -1
View File
@@ -8,7 +8,10 @@ license: >- # License information used in file heade
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'e320'
default_target: 'E320_1G'
default_target: 'E320_1G' # Target. This controls which transports are instantiated.
image_core_name: 'usrp_e320_fpga_1G' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/n3xx/Makefile
+69 -34
View File
@@ -8,7 +8,15 @@
##USRP N3XX FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
## rfnoc_image_builder -y <image core file> -t <target>
##
## NOTE: For building N3x0 bitfiles, do not run make directly! Instead, use
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
## environment, and run Vivado to build a bitfile.
##
## There exist some special make targets which can be called directly like this:
##
## make <Targets> <Options>
##
##Output:
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
@@ -75,9 +83,9 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream file..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/n3xx.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_DIR)/n3xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Exporting build report..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
@@ -86,106 +94,120 @@ endif
##
##Supported Targets
##-----------------
##
##Reminder: Targets are built by calling
##
## $ rfnoc_image_builder -y <image core file.yml> -t <target>
##
##The default image core file is called e320_rfnoc_image_core.yml.
##Of course, a custom YAML file may be used.
##
##Example:
## $ rfnoc_image_builder -y n310_rfnoc_image_core.yml -t N310_XG
##will build the N310_XG target (10-Gigabit Ethernet on both SFP+ ports).
##
##UHD provides a default image core YAML file for every device type called
##n300_rfnoc_image_core.yml, n310_rfnoc_image_core.yml, and n320_rfnoc_image_core.yml,
##respectively.
##For the '-t' argument, combine of the following targets with an appropriate
##image core file:
##
all: N300_HG N300_XG N310_HG N310_XG N320_HG N320_XG ##(Default target)
##N300_IP: Build IP for N300 only.
N300_IP:
+$(call vivado_ip,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
##N310_IP: Build IP for N310/N320.
##N320_IP: Build IP for N310/N320.
N310_IP N320_IP: N3X0_IP
N3X0_IP:
+$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
check-variables:
ifndef IMAGE_CORE_NAME
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
endif
ifndef BUILD_DIR
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
endif
##N310_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
N310_WX: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_WX.dts
N310_WX: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_WX.dts
$(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,WX)
##N310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N310_HG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HG.dts
N310_HG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HG.dts
$(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,HG)
##N310_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N310_XG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XG.dts
N310_XG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XG.dts
$(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,XG)
##N310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
N310_HA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HA.dts
N310_HA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HA.dts
$(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,HA)
##N310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
N310_XA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XA.dts
N310_XA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XA.dts
$(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,XA)
##N310_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N310_AA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_AA.dts
N310_AA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_AA.dts
$(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS))
$(call post_build,N310,AA)
##N300_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
N300_WX: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_WX.dts
N300_WX: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_WX.dts
$(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,WX)
##N300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N300_HG: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HG.dts
N300_HG: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HG.dts
$(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,HG)
##N300_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N300_XG: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XG.dts
N300_XG: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XG.dts
$(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,XG)
##N300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
N300_HA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HA.dts
N300_HA: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HA.dts
$(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,HA)
##N300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
N300_XA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XA.dts
N300_XA: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XA.dts
$(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,XA)
##N300_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N300_AA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_AA.dts
N300_AA: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_AA.dts
$(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS))
$(call post_build,N300,AA)
##N320_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
N320_WX: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_WX.dts
N320_WX: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_WX.dts
$(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,WX)
##N320_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N320_HG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_HG.dts
N320_HG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_HG.dts
$(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,HG)
##N320_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N320_XG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XG.dts
N320_XG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XG.dts
$(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,XG)
##N320_XQ: WR on SFP+ Port0, 10Gig on QSFP+ Port0,1.
N320_XQ: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XQ.dts
N320_XQ: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XQ.dts
$(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,XQ)
##N320_AQ: 10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3.
N320_AQ: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AQ.dts
N320_AQ: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AQ.dts
$(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,AQ)
##N320_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N320_AA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AA.dts
N320_AA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AA.dts
$(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS))
$(call post_build,N320,AA)
@@ -193,15 +215,28 @@ $(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
-mkdir -p $(BUILD_OUTPUT_DIR)
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
##
##Other Make Targets (these should be called directly)
##----------------------------------------------------
##N310_IP: Build IP for N310/N320. Use the -j option to build multiple IP blocks simultaneously.
##N320_IP: Build IP for N310/N320. Use the -j option to build multiple IP blocks simultaneously.
N310_IP N320_IP: N3X0_IP
N3X0_IP:
+$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
##N300_IP: Build IP for N300 only. Use the -j option to build multiple IP blocks simultaneously.
N300_IP:
+$(call vivado_ip,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-N3*_*
@rm -rf $(BUILD_BASE_DIR)/build-N3*_* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-N3*_*
@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
help: ##Show this help message.
top/n3xx/Makefile.n3xx.inc
+11 -16
View File
@@ -40,22 +40,15 @@ include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs
include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, Replay, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
ifdef BUILD_DIR
include $(BUILD_DIR)/Makefile.inc
endif
##################################################
# Sources
@@ -139,23 +132,25 @@ $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
$(WHITE_RABBIT_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
$(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS) \
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
top/n3xx/n300_bist_rfnoc_image_core.v
-984
View File
@@ -1,984 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_image_core (for n300)
//
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n300_bist_rfnoc_image_core.yml
//
`default_nettype none
module rfnoc_image_core #(
parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) (
// Clocks
input wire chdr_aclk,
input wire ctrl_aclk,
input wire core_arst,
input wire radio_clk,
input wire dram_clk,
input wire ce_clk,
// Basic
input wire [ 15:0] device_id,
// IO ports /////////////////////////
// ctrlport_radio0
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// dram
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
output wire [ 23:0] m_axi_awsize,
output wire [ 15:0] m_axi_awburst,
output wire [ 7:0] m_axi_awlock,
output wire [ 31:0] m_axi_awcache,
output wire [ 23:0] m_axi_awprot,
output wire [ 31:0] m_axi_awqos,
output wire [ 31:0] m_axi_awregion,
output wire [ 7:0] m_axi_awuser,
output wire [ 7:0] m_axi_awvalid,
input wire [ 7:0] m_axi_awready,
output wire [4191:0] m_axi_wdata,
output wire [ 511:0] m_axi_wstrb,
output wire [ 7:0] m_axi_wlast,
output wire [ 7:0] m_axi_wuser,
output wire [ 7:0] m_axi_wvalid,
input wire [ 7:0] m_axi_wready,
input wire [ 7:0] m_axi_bid,
input wire [ 15:0] m_axi_bresp,
input wire [ 7:0] m_axi_buser,
input wire [ 7:0] m_axi_bvalid,
output wire [ 7:0] m_axi_bready,
output wire [ 7:0] m_axi_arid,
output wire [ 383:0] m_axi_araddr,
output wire [ 63:0] m_axi_arlen,
output wire [ 23:0] m_axi_arsize,
output wire [ 15:0] m_axi_arburst,
output wire [ 7:0] m_axi_arlock,
output wire [ 31:0] m_axi_arcache,
output wire [ 31:0] m_axi_arprot,
output wire [ 31:0] m_axi_arqos,
output wire [ 31:0] m_axi_arregion,
output wire [ 7:0] m_axi_aruser,
output wire [ 7:0] m_axi_arvalid,
input wire [ 7:0] m_axi_arready,
input wire [ 7:0] m_axi_rid,
input wire [4191:0] m_axi_rdata,
input wire [ 15:0] m_axi_rresp,
input wire [ 7:0] m_axi_rlast,
input wire [ 7:0] m_axi_ruser,
input wire [ 7:0] m_axi_rvalid,
output wire [ 7:0] m_axi_rready,
// Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast,
input wire s_eth0_tvalid,
output wire s_eth0_tready,
output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast,
output wire m_eth0_tvalid,
input wire m_eth0_tready,
// Transport 1 (eth1)
input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast,
input wire s_eth1_tvalid,
output wire s_eth1_tready,
output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast,
output wire m_eth1_tvalid,
input wire m_eth1_tready,
// Transport 2 (dma)
input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast,
input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
);
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
//---------------------------------------------------------------------------
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready;
wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready;
wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready;
chdr_crossbar_nxn #(
.PORT_W (PORT_W),
.NPORTS (7),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0),
.ROUTES ({ 7'b1111111,
7'b1111111,
7'b1111111,
7'b1111111,
7'b1111100,
7'b1111010,
7'b1111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
.s_axis_tdata ({ep5_to_xb_tdata , ep4_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }),
.s_axis_tlast ({ep5_to_xb_tlast , ep4_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }),
.s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
.s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
.m_axis_tdata ({xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }),
.m_axis_tlast ({xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }),
.m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
.m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
.ext_rtcfg_stb (1'h0),
.ext_rtcfg_addr (16'h0),
.ext_rtcfg_data (32'h0),
.ext_rtcfg_ack ()
);
//---------------------------------------------------------------------------
// Stream Endpoints
//---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep0_tdata),
.s_axis_chdr_tlast (xb_to_ep0_tlast),
.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
.s_axis_chdr_tready (xb_to_ep0_tready),
.m_axis_chdr_tdata (ep0_to_xb_tdata),
.m_axis_chdr_tlast (ep0_to_xb_tlast),
.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
.m_axis_chdr_tready (ep0_to_xb_tready),
.s_axis_data_tdata ({s_ep0_in0_tdata}),
.s_axis_data_tlast ({s_ep0_in0_tlast}),
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
.s_axis_data_tready ({s_ep0_in0_tready}),
.m_axis_data_tdata ({m_ep0_out0_tdata}),
.m_axis_data_tlast ({m_ep0_out0_tlast}),
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
.m_axis_data_tready ({m_ep0_out0_tready}),
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep1_tdata),
.s_axis_chdr_tlast (xb_to_ep1_tlast),
.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
.s_axis_chdr_tready (xb_to_ep1_tready),
.m_axis_chdr_tdata (ep1_to_xb_tdata),
.m_axis_chdr_tlast (ep1_to_xb_tlast),
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
.m_axis_chdr_tready (ep1_to_xb_tready),
.s_axis_data_tdata ({s_ep1_in0_tdata}),
.s_axis_data_tlast ({s_ep1_in0_tlast}),
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
.s_axis_data_tready ({s_ep1_in0_tready}),
.m_axis_data_tdata ({m_ep1_out0_tdata}),
.m_axis_data_tlast ({m_ep1_out0_tlast}),
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
.m_axis_data_tready ({m_ep1_out0_tready}),
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 16384;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (2),
.CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (EP4_MTU),
.REPORT_STRM_ERRS (1)
) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep4_tdata),
.s_axis_chdr_tlast (xb_to_ep4_tlast),
.s_axis_chdr_tvalid (xb_to_ep4_tvalid),
.s_axis_chdr_tready (xb_to_ep4_tready),
.m_axis_chdr_tdata (ep4_to_xb_tdata),
.m_axis_chdr_tlast (ep4_to_xb_tlast),
.m_axis_chdr_tvalid (ep4_to_xb_tvalid),
.m_axis_chdr_tready (ep4_to_xb_tready),
.s_axis_data_tdata ({s_ep4_in0_tdata}),
.s_axis_data_tlast ({s_ep4_in0_tlast}),
.s_axis_data_tvalid ({s_ep4_in0_tvalid}),
.s_axis_data_tready ({s_ep4_in0_tready}),
.m_axis_data_tdata ({m_ep4_out0_tdata}),
.m_axis_data_tlast ({m_ep4_out0_tlast}),
.m_axis_data_tvalid ({m_ep4_out0_tvalid}),
.m_axis_data_tready ({m_ep4_out0_tready}),
.s_axis_ctrl_tdata (s_ep4_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep4_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep4_ctrl_tready),
.m_axis_ctrl_tdata (m_ep4_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep4_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep4_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 16384;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (3),
.CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (EP5_MTU),
.REPORT_STRM_ERRS (1)
) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep5_tdata),
.s_axis_chdr_tlast (xb_to_ep5_tlast),
.s_axis_chdr_tvalid (xb_to_ep5_tvalid),
.s_axis_chdr_tready (xb_to_ep5_tready),
.m_axis_chdr_tdata (ep5_to_xb_tdata),
.m_axis_chdr_tlast (ep5_to_xb_tlast),
.m_axis_chdr_tvalid (ep5_to_xb_tvalid),
.m_axis_chdr_tready (ep5_to_xb_tready),
.s_axis_data_tdata ({s_ep5_in0_tdata}),
.s_axis_data_tlast ({s_ep5_in0_tlast}),
.s_axis_data_tvalid ({s_ep5_in0_tvalid}),
.s_axis_data_tready ({s_ep5_in0_tready}),
.m_axis_data_tdata ({m_ep5_out0_tdata}),
.m_axis_data_tlast ({m_ep5_out0_tlast}),
.m_axis_data_tvalid ({m_ep5_out0_tvalid}),
.m_axis_data_tready ({m_ep5_out0_tready}),
.s_axis_ctrl_tdata (s_ep5_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep5_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep5_ctrl_tready),
.m_axis_ctrl_tdata (m_ep5_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep5_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep5_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
//---------------------------------------------------------------------------
// Control Crossbar
//---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
wire m_core_ctrl_tready, s_core_ctrl_tready;
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
wire [31:0] m_fifo0_ctrl_tdata, s_fifo0_ctrl_tdata;
wire m_fifo0_ctrl_tlast, s_fifo0_ctrl_tlast;
wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid;
wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready;
axis_ctrl_crossbar_nxn #(
.WIDTH (32),
.NPORTS (4),
.TOPOLOGY ("TORUS"),
.INGRESS_BUFF_SIZE(5),
.ROUTER_BUFF_SIZE (5),
.ROUTING_ALLOC ("WORMHOLE"),
.SWITCH_ALLOC ("PRIO")
) ctrl_xb_i (
.clk (rfnoc_ctrl_clk),
.reset (rfnoc_ctrl_rst),
.s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.deadlock_detected()
);
//---------------------------------------------------------------------------
// RFNoC Core Kernel
//---------------------------------------------------------------------------
wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #(
.PROTOVER (PROTOVER),
.DEVICE_TYPE (16'h1300),
.DEVICE_FAMILY ("7SERIES"),
.SAFE_START_CLKS (0),
.NUM_BLOCKS (2),
.NUM_STREAM_ENDPOINTS(4),
.NUM_ENDPOINTS_CTRL (1),
.NUM_TRANSPORTS (3),
.NUM_EDGES (8),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL ({
{10'd06, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd06, 6'd01},
{10'd06, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd05, 6'd01},
{10'd05, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
.ctrl_aclk (ctrl_aclk),
.ctrl_aclk_locked (1'b1),
.core_arst (core_arst),
.core_chdr_clk (rfnoc_chdr_clk),
.core_chdr_rst (rfnoc_chdr_rst),
.core_ctrl_clk (rfnoc_ctrl_clk),
.core_ctrl_rst (rfnoc_ctrl_rst),
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
.s_axis_ctrl_tready (s_core_ctrl_tready),
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
.m_axis_ctrl_tready (m_core_ctrl_tready),
.device_id (device_id),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
//---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (BLOCK_MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
.radio_time (radio0_radio_time),
.radio_rx_data (radio0_radio_rx_data),
.radio_rx_stb (radio0_radio_rx_stb),
.radio_rx_running (radio0_radio_rx_running),
.radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
//-----------------------------------
// fifo0
//-----------------------------------
wire fifo0_mem_clk;
wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
wire [ 23:0] fifo0_m_axi_awsize;
wire [ 15:0] fifo0_m_axi_awburst;
wire [ 7:0] fifo0_m_axi_awlock;
wire [ 31:0] fifo0_m_axi_awcache;
wire [ 23:0] fifo0_m_axi_awprot;
wire [ 31:0] fifo0_m_axi_awqos;
wire [ 31:0] fifo0_m_axi_awregion;
wire [ 7:0] fifo0_m_axi_awuser;
wire [ 7:0] fifo0_m_axi_awvalid;
wire [ 7:0] fifo0_m_axi_awready;
wire [4191:0] fifo0_m_axi_wdata;
wire [ 511:0] fifo0_m_axi_wstrb;
wire [ 7:0] fifo0_m_axi_wlast;
wire [ 7:0] fifo0_m_axi_wuser;
wire [ 7:0] fifo0_m_axi_wvalid;
wire [ 7:0] fifo0_m_axi_wready;
wire [ 7:0] fifo0_m_axi_bid;
wire [ 15:0] fifo0_m_axi_bresp;
wire [ 7:0] fifo0_m_axi_buser;
wire [ 7:0] fifo0_m_axi_bvalid;
wire [ 7:0] fifo0_m_axi_bready;
wire [ 7:0] fifo0_m_axi_arid;
wire [ 383:0] fifo0_m_axi_araddr;
wire [ 63:0] fifo0_m_axi_arlen;
wire [ 23:0] fifo0_m_axi_arsize;
wire [ 15:0] fifo0_m_axi_arburst;
wire [ 7:0] fifo0_m_axi_arlock;
wire [ 31:0] fifo0_m_axi_arcache;
wire [ 31:0] fifo0_m_axi_arprot;
wire [ 31:0] fifo0_m_axi_arqos;
wire [ 31:0] fifo0_m_axi_arregion;
wire [ 7:0] fifo0_m_axi_aruser;
wire [ 7:0] fifo0_m_axi_arvalid;
wire [ 7:0] fifo0_m_axi_arready;
wire [ 7:0] fifo0_m_axi_rid;
wire [4191:0] fifo0_m_axi_rdata;
wire [ 15:0] fifo0_m_axi_rresp;
wire [ 7:0] fifo0_m_axi_rlast;
wire [ 7:0] fifo0_m_axi_ruser;
wire [ 7:0] fifo0_m_axi_rvalid;
wire [ 7:0] fifo0_m_axi_rready;
rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4),
.MEM_DATA_W (64),
.MEM_ADDR_W (31),
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (),
.MTU (BLOCK_MTU)
) b_fifo0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.mem_clk (fifo0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.axi_rst (fifo0_axi_rst),
.m_axi_awid (fifo0_m_axi_awid),
.m_axi_awaddr (fifo0_m_axi_awaddr),
.m_axi_awlen (fifo0_m_axi_awlen),
.m_axi_awsize (fifo0_m_axi_awsize),
.m_axi_awburst (fifo0_m_axi_awburst),
.m_axi_awlock (fifo0_m_axi_awlock),
.m_axi_awcache (fifo0_m_axi_awcache),
.m_axi_awprot (fifo0_m_axi_awprot),
.m_axi_awqos (fifo0_m_axi_awqos),
.m_axi_awregion (fifo0_m_axi_awregion),
.m_axi_awuser (fifo0_m_axi_awuser),
.m_axi_awvalid (fifo0_m_axi_awvalid),
.m_axi_awready (fifo0_m_axi_awready),
.m_axi_wdata (fifo0_m_axi_wdata),
.m_axi_wstrb (fifo0_m_axi_wstrb),
.m_axi_wlast (fifo0_m_axi_wlast),
.m_axi_wuser (fifo0_m_axi_wuser),
.m_axi_wvalid (fifo0_m_axi_wvalid),
.m_axi_wready (fifo0_m_axi_wready),
.m_axi_bid (fifo0_m_axi_bid),
.m_axi_bresp (fifo0_m_axi_bresp),
.m_axi_buser (fifo0_m_axi_buser),
.m_axi_bvalid (fifo0_m_axi_bvalid),
.m_axi_bready (fifo0_m_axi_bready),
.m_axi_arid (fifo0_m_axi_arid),
.m_axi_araddr (fifo0_m_axi_araddr),
.m_axi_arlen (fifo0_m_axi_arlen),
.m_axi_arsize (fifo0_m_axi_arsize),
.m_axi_arburst (fifo0_m_axi_arburst),
.m_axi_arlock (fifo0_m_axi_arlock),
.m_axi_arcache (fifo0_m_axi_arcache),
.m_axi_arprot (fifo0_m_axi_arprot),
.m_axi_arqos (fifo0_m_axi_arqos),
.m_axi_arregion (fifo0_m_axi_arregion),
.m_axi_aruser (fifo0_m_axi_aruser),
.m_axi_arvalid (fifo0_m_axi_arvalid),
.m_axi_arready (fifo0_m_axi_arready),
.m_axi_rid (fifo0_m_axi_rid),
.m_axi_rdata (fifo0_m_axi_rdata),
.m_axi_rresp (fifo0_m_axi_rresp),
.m_axi_rlast (fifo0_m_axi_rlast),
.m_axi_ruser (fifo0_m_axi_ruser),
.m_axi_rvalid (fifo0_m_axi_rvalid),
.m_axi_rready (fifo0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
//---------------------------------------------------------------------------
// Static Router
//---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready;
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready;
assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
assign m_ep1_out0_tready = s_radio0_in_1_tready;
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
assign m_radio0_out_1_tready = s_ep1_in0_tready;
assign s_fifo0_in_0_tdata = m_ep4_out0_tdata;
assign s_fifo0_in_0_tlast = m_ep4_out0_tlast;
assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid;
assign m_ep4_out0_tready = s_fifo0_in_0_tready;
assign s_ep4_in0_tdata = m_fifo0_out_0_tdata;
assign s_ep4_in0_tlast = m_fifo0_out_0_tlast;
assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid;
assign m_fifo0_out_0_tready = s_ep4_in0_tready;
assign s_fifo0_in_1_tdata = m_ep5_out0_tdata;
assign s_fifo0_in_1_tlast = m_ep5_out0_tlast;
assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid;
assign m_ep5_out0_tready = s_fifo0_in_1_tready;
assign s_ep5_in0_tdata = m_fifo0_out_1_tdata;
assign s_ep5_in0_tlast = m_fifo0_out_1_tlast;
assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid;
assign m_fifo0_out_1_tready = s_ep5_in0_tready;
//---------------------------------------------------------------------------
// Unused Ports
//---------------------------------------------------------------------------
assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}};
assign s_fifo0_in_2_tlast = 1'b0;
assign s_fifo0_in_2_tvalid = 1'b0;
assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}};
assign s_fifo0_in_3_tlast = 1'b0;
assign s_fifo0_in_3_tvalid = 1'b0;
assign m_fifo0_out_2_tready = 1'b1;
assign m_fifo0_out_3_tready = 1'b1;
//---------------------------------------------------------------------------
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
assign fifo0_mem_clk = dram_clk;
//---------------------------------------------------------------------------
// IO Port Connection
//---------------------------------------------------------------------------
// Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr;
assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data;
assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en;
assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time;
assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time;
assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack;
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
assign m_axi_awlen = fifo0_m_axi_awlen;
assign m_axi_awsize = fifo0_m_axi_awsize;
assign m_axi_awburst = fifo0_m_axi_awburst;
assign m_axi_awlock = fifo0_m_axi_awlock;
assign m_axi_awcache = fifo0_m_axi_awcache;
assign m_axi_awprot = fifo0_m_axi_awprot;
assign m_axi_awqos = fifo0_m_axi_awqos;
assign m_axi_awregion = fifo0_m_axi_awregion;
assign m_axi_awuser = fifo0_m_axi_awuser;
assign m_axi_awvalid = fifo0_m_axi_awvalid;
assign fifo0_m_axi_awready = m_axi_awready;
assign m_axi_wdata = fifo0_m_axi_wdata;
assign m_axi_wstrb = fifo0_m_axi_wstrb;
assign m_axi_wlast = fifo0_m_axi_wlast;
assign m_axi_wuser = fifo0_m_axi_wuser;
assign m_axi_wvalid = fifo0_m_axi_wvalid;
assign fifo0_m_axi_wready = m_axi_wready;
assign fifo0_m_axi_bid = m_axi_bid;
assign fifo0_m_axi_bresp = m_axi_bresp;
assign fifo0_m_axi_buser = m_axi_buser;
assign fifo0_m_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = fifo0_m_axi_bready;
assign m_axi_arid = fifo0_m_axi_arid;
assign m_axi_araddr = fifo0_m_axi_araddr;
assign m_axi_arlen = fifo0_m_axi_arlen;
assign m_axi_arsize = fifo0_m_axi_arsize;
assign m_axi_arburst = fifo0_m_axi_arburst;
assign m_axi_arlock = fifo0_m_axi_arlock;
assign m_axi_arcache = fifo0_m_axi_arcache;
assign m_axi_arprot = fifo0_m_axi_arprot;
assign m_axi_arqos = fifo0_m_axi_arqos;
assign m_axi_arregion = fifo0_m_axi_arregion;
assign m_axi_aruser = fifo0_m_axi_aruser;
assign m_axi_arvalid = fifo0_m_axi_arvalid;
assign fifo0_m_axi_arready = m_axi_arready;
assign fifo0_m_axi_rid = m_axi_rid;
assign fifo0_m_axi_rdata = m_axi_rdata;
assign fifo0_m_axi_rresp = m_axi_rresp;
assign fifo0_m_axi_rlast = m_axi_rlast;
assign fifo0_m_axi_ruser = m_axi_ruser;
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
endmodule
`default_nettype wire
top/n3xx/n300_bist_rfnoc_image_core.vh
-19
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n300_bist_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n300_bist_rfnoc_image_core.yml
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@@ -8,8 +8,10 @@ license: >- # License information used in file heade
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'n300'
image_core_name: 'n300_bist' # Name to use for the RFNoC Image Core files
default_target: 'N300_AA'
image_core_name: 'usrp_n300_fpga_AA' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/n3xx/n300_rfnoc_image_core.v
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top/n3xx/n300_rfnoc_image_core.vh
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n300_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n300_rfnoc_image_core.yml
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@@ -9,6 +9,9 @@ version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'n300'
default_target: 'N300_HG'
image_core_name: 'usrp_n300_fpga_HG' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/n3xx/n310_bist_rfnoc_image_core.v
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n310)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n310_bist_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n310_bist_rfnoc_image_core.yml
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@@ -8,8 +8,10 @@ license: >- # License information used in file heade
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this block
device: 'n310'
image_core_name: 'n310_bist' # Name to use for the RFNoC Image Core files
default_target: 'N310_AA'
image_core_name: 'usrp_n310_fpga_AA' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/n3xx/n310_rfnoc_image_core.v
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n310)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n310_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n310_rfnoc_image_core.yml
+3
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@@ -9,6 +9,9 @@ version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'n310'
default_target: 'N310_HG'
image_core_name: 'usrp_n310_fpga_HG' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/n3xx/n320_bist_rfnoc_image_core.v
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n320_bist_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n320_bist_rfnoc_image_core.yml
+3 -1
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@@ -8,8 +8,10 @@ license: >- # License information used in file heade
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this block
device: 'n320'
image_core_name: 'n320_bist' # Name to use for the RFNoC Image Core files
default_target: 'N320_AA'
image_core_name: 'usrp_n320_fpga_AA' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/n3xx/n320_rfnoc_image_core.v
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: n320_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n320_rfnoc_image_core.yml
+3
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@@ -9,6 +9,9 @@ version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'n320'
default_target: 'N320_HG'
image_core_name: 'usrp_n320_fpga_HG' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------
top/x300/Makefile
+77 -28
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@@ -7,7 +7,15 @@
##USRP X3X0 FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
## rfnoc_image_builder -y <image core file> [-t <target>]
##
## NOTE: For building X3x0 bitfiles, do not run make directly! Instead, use
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
## environment, and run Vivado to build a bitfile.
##
## There exist some special make targets which can be called directly like this:
##
## make <Targets> <Options>
##
##Output:
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
@@ -28,8 +36,6 @@ BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
# The image core name is something like 'usrp_x310_fpga_XG'
IMAGE_CORE_NAME ?= usrp_fpga
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
@@ -60,13 +66,13 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream files..."; \
cp $(ARTIFACT_DIR)/x300.bin $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bin; \
cp $(ARTIFACT_DIR)/x300.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
cp $(BUILD_DIR)/x300.bin $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bin; \
cp $(BUILD_DIR)/x300.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Generating LVBITX..."; \
$(CREATE_LVBITX) --input-bin=$(ARTIFACT_DIR)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
$(CREATE_LVBITX) --input-bin=$(BUILD_DIR)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
cp -f x3x0_base.lvbitx $(BUILD_OUTPUT_DIR)/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
echo "Exporting build report..."; \
cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
@@ -75,76 +81,119 @@ endif
##
##Supported Targets
##-----------------
##all: X300_HG X310_HG X300_XG X310_XG (Default target)
all: X300_HG X310_HG X300_XG X310_XG
##
##Reminder: Targets are built by calling
##
## $ rfnoc_image_builder -y <image core file.yml> [-t <target>]
##
##The default <image core file.yml> is one of:
##
##- x300_HG_rfnoc_image_core.yml
##- x300_XG_rfnoc_image_core.yml
##- x310_HG_rfnoc_image_core.yml
##- x310_XG_rfnoc_image_core.yml
##
##Of course, a custom YAML file may be used.
##
##When building a bitfile for X310, use a x310_*.yml file, otherwise, for X300,
##use a x300_*.yml file.
##
##When building an XG bitfile (dual 10-Gigabit Ethernet), use the
##*_XG_rfnoc_image_core.yml file. When building an HG bitfile (1-Gigabit and
##10 Gigabit Ethernet), use a *_HG_rfnoc_image_core.yml file. In these cases,
##using '--target' is not necessary, but it doesn't do any harm, either.
##
##For all other targets, choose a suitable target image core YAML file depending
##on the device type (x310_*.yml or x300_*.yml) and provide the '--target' option
##to override the default from the YAML file.
##
##Example:
## $ rfnoc_image_builder -y x310_XG_rfnoc_image_core.yml -t X310_XA
##will build the X310_XA target.
##
##X300_IP: Build IP for X300 only.
X300_IP:
+$(call vivado_ip,X300,$(HG_DEFS) X300=1)
##X310_IP: Build IP for X310 only.
X310_IP:
+$(call vivado_ip,X310,$(HG_DEFS) X310=1)
check-variables:
ifndef IMAGE_CORE_NAME
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
endif
ifndef BUILD_DIR
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
endif
##X310_1G: 1GigE on both SFP+ ports.
X310_1G: X310_IP
X310_1G: check-variables X310_IP
$(call vivado_build,X310,$(GIGE_DEFS) X310=1)
$(call post_build,X310,1G)
##X300_1G: 1GigE on both SFP+ ports.
X300_1G: X300_IP
X300_1G: check-variables X300_IP
$(call vivado_build,X300,$(GIGE_DEFS) X300=1)
$(call post_build,X300,1G)
##X310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
X310_HG: X310_IP
X310_HG: check-variables X310_IP
$(call vivado_build,X310,$(HG_DEFS) X310=1)
$(call post_build,X310,HG)
##X300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
X300_HG: X300_IP
X300_HG: check-variables X300_IP
$(call vivado_build,X300,$(HG_DEFS) X300=1)
$(call post_build,X300,HG)
##X310_XG: 10GigE on both SFP+ ports.
X310_XG: X310_IP
X310_XG: check-variables X310_IP
$(call vivado_build,X310,$(XG_DEFS) X310=1)
$(call post_build,X310,XG)
##X300_XG: 10GigE on both SFP+ ports.
X300_XG: X300_IP
X300_XG: check-variables X300_IP
$(call vivado_build,X300,$(XG_DEFS) X300=1)
$(call post_build,X300,XG)
##X310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
X310_HA: X310_IP
X310_HA: check-variables X310_IP
$(call vivado_build,X310,$(HA_DEFS) X310=1)
$(call post_build,X310,HA)
##X300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
X300_HA: X300_IP
X300_HA: check-variables X300_IP
$(call vivado_build,X300,$(HA_DEFS) X300=1)
$(call post_build,X300,HA)
##X310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
X310_XA: X310_IP
X310_XA: check-variables X310_IP
$(call vivado_build,X310,$(XA_DEFS) X310=1)
$(call post_build,X310,XA)
##X300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
X300_XA: X300_IP
X300_XA: check-variables X300_IP
$(call vivado_build,X300,$(XA_DEFS) X300=1)
$(call post_build,X300,XA)
##
##Other Make Targets (these should be called directly)
##----------------------------------------------------
##X300_IP: Build IP for X300 only. Use the -j option to build multiple IP blocks simultaneously.
X300_IP:
+$(call vivado_ip,X300,$(HG_DEFS) X300=1)
##X310_IP: Build IP for X310 only. Use the -j option to build multiple IP blocks simultaneously.
X310_IP:
+$(call vivado_ip,X310,$(HG_DEFS) X310=1)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3*
@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3*
@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
help: ##Show this help message.
top/x300/Makefile.x300.inc
+6 -3
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@@ -45,8 +45,8 @@ include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
ifdef ARTIFACT_DIR
include $(ARTIFACT_DIR)/Makefile.inc
ifdef BUILD_DIR
include $(BUILD_DIR)/Makefile.inc
endif
##################################################
@@ -109,7 +109,7 @@ $(RFNOC_IMAGE_CORE_SRCS)
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(ARTIFACT_DIR)/rfnoc_image_core.vh"
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
@@ -120,6 +120,9 @@ VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_H
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x300.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
top/x400/Makefile
+52 -56
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@@ -9,6 +9,14 @@
##USRP X4xx FPGA Help
##-------------------
##Usage:
## rfnoc_image_builder -y <image core file>
##
## NOTE: For building X4x0 bitfiles, do not run make directly! Instead, use
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
## environment, and run Vivado to build a bitfile.
##
## There exist some special make targets which can be called directly like this:
##
## make <Targets> <Options>
##
##Output:
@@ -16,7 +24,6 @@
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Base output directory for all builds.
BUILD_BASE_DIR ?= .
# Base directory for the build outputs.
@@ -30,7 +37,6 @@ X440_IP: DEFS += QSFP0_0=2 RF_BW=400
# exclude it. Note that some targets exclude it regardless of this setting.
DRAM ?= 1
IMAGE_CORE_NAME ?= usrp_fpga
DEFS += $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
@@ -57,10 +63,6 @@ ifndef TARGET
endif
TOP ?= x4xx
ifdef ARTIFACT_DIR
BUILD_DIR = $(ARTIFACT_DIR)
endif
# vivado_build($1=Device (X410 or X440), $2=Definitions)
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2 INCR_BUILD=$(INCR_BUILD)
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2
@@ -70,99 +72,93 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream file..."; \
cp $(ARTIFACT_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
cp $(BUILD_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Exporting build report..."; \
cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(IMAGE_CORE_NAME)";
else
post_build = @echo "Skipping bitfile export."
endif
##
##Available Targets
##Available Targets:
##
##Reminder: Targets are built by calling
##
## $ rfnoc_image_builder -y <image core file.yml>
##
##The following default image core files are provided:
##
##-----------------------------------|-----------|----|-----------------|-----------------|------------
##Image core name | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
##-----------------------------------|-----------|----|-----------------|-----------------|------------
##x410_CG_400_rfnoc_image_core.yml | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
##x410_UC_200_rfnoc_image_core.yml | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
##x410_X4_200_rfnoc_image_core.yml | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
##x410_XG_200_rfnoc_image_core.yml | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##x440_CG_400_rfnoc_image_core.yml | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
##x440_CG_1600_rfnoc_image_core.yml | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
##x440_X4_200_rfnoc_image_core.yml | 200 MHz | 8 | 4 x 10 GbE | Unused | Unused
##x440_X4_400_rfnoc_image_core.yml | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
##x440_X4_1600_rfnoc_image_core.yml | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
##
##Of course, a custom YAML file may be used.
##
check-variables:
ifndef IMAGE_CORE_NAME
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
endif
ifndef BUILD_DIR
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
endif
##-------------|-----------|----|-----------------|-----------------|------------
##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
##-------------|-----------|----|-----------------|-----------------|------------
##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch
##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
##X440_X1_400 | 400 MHz | 8 | 10 GbE (Lane 0) | Unused | 128b x 8 Ch
##X440_X4_400 | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
##X440_C1_400 | 400 MHz | 8 | 100 GbE | Unused | Unused
##X440_CG_400 | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
##X440_X1_1600 | 1.6 GHz | 2 | 10 GbE (Lane 0) | Unused | 512b x 2 Ch
##X440_X4_1600 | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
##X440_C1_1600 | 1.6 GHz | 2 | 100 GbE | Unused | Unused
##X440_CG_1600 | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
##* Note: Not all targets are shipped with UHD
##* Note: Some YAML configurations might not use all available DRAM channels.
X410: X410_IP build/$(IMAGE_CORE_NAME).dts
X410: check-variables X410_IP $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).dts
$(call vivado_build,X410,$(DEFS) X410=1)
$(call post_build,X410)
X440: X440_IP build/$(IMAGE_CORE_NAME).dts
X440: check-variables X440_IP $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).dts
$(call vivado_build,X440,$(DEFS) X440=1)
$(call post_build,X440)
##
##Other Make Targets
##------------------
##Other Make Targets (these should be called directly)
##----------------------------------------------------
.DEFAULT_GOAL := all
all: X410_IP
X410_IP: ##Build X410 IP only.
X410_IP: ##Build X410 IP only. Use the -j option to build multiple IP blocks simultaneously.
+$(call vivado_ip,X410,$(DEFS) X410=1)
X440_IP: ##Build X440 IP only.
X440_IP: ##Build X440 IP only. Use the -j option to build multiple IP blocks simultaneously.
+$(call vivado_ip,X440,$(DEFS) X440=1)
$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi $(BUILD_DIR)/device_tree.dts
-mkdir -p $(BUILD_OUTPUT_DIR)
tools/parse_versions_for_dts.py \
--input regmap/x410/versioning_regs_regmap_utils.vh \
--output dts/x410-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$(ARTIFACT_DIR)/device_tree.dts
$(BUILD_DIR)/device_tree.dts
$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi $(BUILD_DIR)/device_tree.dts
-mkdir -p $(BUILD_OUTPUT_DIR)
tools/parse_versions_for_dts.py \
--input regmap/x440/versioning_regs_regmap_utils.vh \
--output dts/x440-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$(ARTIFACT_DIR)/device_tree.dts
$(BUILD_DIR)/device_tree.dts
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x*
@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and IP build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-*
@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
help: ##Show this help message.
top/x400/Makefile.x4xx.inc
+5 -5
View File
@@ -46,9 +46,9 @@ include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
ifdef ARTIFACT_DIR
include $(ARTIFACT_DIR)/Makefile.inc
# Now include everything that falls out of the image builder
ifdef BUILD_DIR
include $(BUILD_DIR)/Makefile.inc
endif
##################################################
@@ -162,7 +162,7 @@ $(RFNOC_IMAGE_CORE_SRCS) \
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(ARTIFACT_DIR)/rfnoc_image_core.vh"
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
@@ -175,7 +175,7 @@ VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_H
bin: .prereqs
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS) $(RFNOC_IMAGE_CORE_DEFS)"
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
top/x400/x410_X4_400_rfnoc_image_core.yml
+141
View File
@@ -0,0 +1,141 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 128 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'usrp_x410_fpga_X4_400'# Name to use for the RFNoC Image Core files
default_target: 'X410' # Default make target
inherit:
- 'yaml_include/x410_radio_base.yml'
- 'yaml_include/x4xx_x4_base.yml'
parameters:
RF_BW: 400
ENABLE_DRAM: True
NUM_DRAM_BANKS: 1
NUM_DRAM_CHANS: 4
DRAM_WIDTH: 128
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 32768 # Stream endpoint buffer size
ep1:
ctrl: False
data: True
buff_size_bytes: 32768
ep2:
ctrl: False
data: True
buff_size_bytes: 32768
ep3:
ctrl: False
data: True
buff_size_bytes: 32768
ep4:
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
ctrl: False
data: True
buff_size_bytes: 32768
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 128
MEM_ADDR_W: 32
replay1:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 128
MEM_ADDR_W: 32
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- { srcblk: ep6, srcport: out0, dstblk: replay1, dstport: in_0 }
- { srcblk: replay1, srcport: out_0, dstblk: ep6, dstport: in0 }
- { srcblk: ep7, srcport: out0, dstblk: replay1, dstport: in_1 }
- { srcblk: replay1, srcport: out_1, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device_")
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }