fpga: Align build process for all targets
- All RFNoC capable targets now require rfnoc_image_builder to be built - `make help` is updated for all targets to provide more useful and up-to-date information - The FPGA manual is also updated - All checked-in build artifacts are now removed from git - axi_ram_fifo.yml is updated to provide include path information (required for building N3xx BIST images, which use this) Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
parent
ba5e431c5c
commit
6ef3795e42
+52
-56
@@ -9,6 +9,14 @@
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##USRP X4xx FPGA Help
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##-------------------
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##Usage:
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## rfnoc_image_builder -y <image core file>
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##
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## NOTE: For building X4x0 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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@@ -16,7 +24,6 @@
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Base output directory for all builds.
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BUILD_BASE_DIR ?= .
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# Base directory for the build outputs.
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@@ -30,7 +37,6 @@ X440_IP: DEFS += QSFP0_0=2 RF_BW=400
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# exclude it. Note that some targets exclude it regardless of this setting.
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DRAM ?= 1
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IMAGE_CORE_NAME ?= usrp_fpga
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DEFS += $(OPTIONS)
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# Initialize a build seed. This can be changed to randomly affect build results.
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@@ -57,10 +63,6 @@ ifndef TARGET
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endif
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TOP ?= x4xx
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ifdef ARTIFACT_DIR
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BUILD_DIR = $(ARTIFACT_DIR)
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endif
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# vivado_build($1=Device (X410 or X440), $2=Definitions)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2 INCR_BUILD=$(INCR_BUILD)
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2
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@@ -70,99 +72,93 @@ ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(ARTIFACT_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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cp $(BUILD_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(IMAGE_CORE_NAME)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Available Targets
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##Available Targets:
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##
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml>
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##
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##The following default image core files are provided:
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##
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##-----------------------------------|-----------|----|-----------------|-----------------|------------
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##Image core name | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-----------------------------------|-----------|----|-----------------|-----------------|------------
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##x410_CG_400_rfnoc_image_core.yml | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
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##x410_UC_200_rfnoc_image_core.yml | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##x410_X4_200_rfnoc_image_core.yml | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##x410_XG_200_rfnoc_image_core.yml | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##x440_CG_400_rfnoc_image_core.yml | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
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##x440_CG_1600_rfnoc_image_core.yml | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
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##x440_X4_200_rfnoc_image_core.yml | 200 MHz | 8 | 4 x 10 GbE | Unused | Unused
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##x440_X4_400_rfnoc_image_core.yml | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
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##x440_X4_1600_rfnoc_image_core.yml | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
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##
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##Of course, a custom YAML file may be used.
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##
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
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##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
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##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch
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##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
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##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
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##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
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##X440_X1_400 | 400 MHz | 8 | 10 GbE (Lane 0) | Unused | 128b x 8 Ch
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##X440_X4_400 | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
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##X440_C1_400 | 400 MHz | 8 | 100 GbE | Unused | Unused
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##X440_CG_400 | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
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##X440_X1_1600 | 1.6 GHz | 2 | 10 GbE (Lane 0) | Unused | 512b x 2 Ch
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##X440_X4_1600 | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
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##X440_C1_1600 | 1.6 GHz | 2 | 100 GbE | Unused | Unused
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##X440_CG_1600 | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
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##* Note: Not all targets are shipped with UHD
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##* Note: Some YAML configurations might not use all available DRAM channels.
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X410: X410_IP build/$(IMAGE_CORE_NAME).dts
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X410: check-variables X410_IP $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).dts
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$(call vivado_build,X410,$(DEFS) X410=1)
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$(call post_build,X410)
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X440: X440_IP build/$(IMAGE_CORE_NAME).dts
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X440: check-variables X440_IP $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).dts
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$(call vivado_build,X440,$(DEFS) X440=1)
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$(call post_build,X440)
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##
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##Other Make Targets
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##------------------
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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.DEFAULT_GOAL := all
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all: X410_IP
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X410_IP: ##Build X410 IP only.
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X410_IP: ##Build X410 IP only. Use the -j option to build multiple IP blocks simultaneously.
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+$(call vivado_ip,X410,$(DEFS) X410=1)
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X440_IP: ##Build X440 IP only.
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X440_IP: ##Build X440 IP only. Use the -j option to build multiple IP blocks simultaneously.
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+$(call vivado_ip,X440,$(DEFS) X440=1)
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$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
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$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi $(BUILD_DIR)/device_tree.dts
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-mkdir -p $(BUILD_OUTPUT_DIR)
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tools/parse_versions_for_dts.py \
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--input regmap/x410/versioning_regs_regmap_utils.vh \
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--output dts/x410-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$(ARTIFACT_DIR)/device_tree.dts
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$(BUILD_DIR)/device_tree.dts
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$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
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$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi $(BUILD_DIR)/device_tree.dts
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-mkdir -p $(BUILD_OUTPUT_DIR)
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tools/parse_versions_for_dts.py \
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--input regmap/x440/versioning_regs_regmap_utils.vh \
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--output dts/x440-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$(ARTIFACT_DIR)/device_tree.dts
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$(BUILD_DIR)/device_tree.dts
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x*
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@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and IP build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-*
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@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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@@ -46,9 +46,9 @@ include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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ifdef ARTIFACT_DIR
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include $(ARTIFACT_DIR)/Makefile.inc
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# Now include everything that falls out of the image builder
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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@@ -162,7 +162,7 @@ $(RFNOC_IMAGE_CORE_SRCS) \
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(ARTIFACT_DIR)/rfnoc_image_core.vh"
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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@@ -175,7 +175,7 @@ VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_H
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS) $(RFNOC_IMAGE_CORE_DEFS)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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@@ -0,0 +1,141 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 128 # Bit width of the CHDR bus for this image
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device: 'x410' # USRP type
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image_core_name: 'usrp_x410_fpga_X4_400'# Name to use for the RFNoC Image Core files
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default_target: 'X410' # Default make target
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inherit:
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- 'yaml_include/x410_radio_base.yml'
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- 'yaml_include/x4xx_x4_base.yml'
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parameters:
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RF_BW: 400
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ENABLE_DRAM: True
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NUM_DRAM_BANKS: 1
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NUM_DRAM_CHANS: 4
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DRAM_WIDTH: 128
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 32768 # Stream endpoint buffer size
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep4:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep5:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep6:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep7:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 2
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MEM_DATA_W: 128
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MEM_ADDR_W: 32
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replay1:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 2
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MEM_DATA_W: 128
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MEM_ADDR_W: 32
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A:0 TX
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- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
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# RF A:0 RX
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- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF A:1 TX
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- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
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# RF A:1 RX
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- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# RF B:0 TX
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- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
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# RF B:0 RX
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- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
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# RF B:1 TX
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- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
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# RF B:1 RX
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- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
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#
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# Replay Connections
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- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
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- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
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- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
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- { srcblk: ep6, srcport: out0, dstblk: replay1, dstport: in_0 }
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- { srcblk: replay1, srcport: out_0, dstblk: ep6, dstport: in0 }
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- { srcblk: ep7, srcport: out0, dstblk: replay1, dstport: in_1 }
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- { srcblk: replay1, srcport: out_1, dstblk: ep7, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
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- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
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- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device_")
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
|
||||
Reference in New Issue
Block a user