fpga: Align build process for all targets

- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74

top/n3xx/n300_rfnoc_image_core.yml

@@ -9,6 +9,9 @@ version: '1.0'                          # File version
 chdr_width: 64                          # Bit width of the CHDR bus for this image
 device: 'n300'
 default_target: 'N300_HG'
+image_core_name: 'usrp_n300_fpga_HG'    # Name to use for the generated output files.
+                                        # Change image_core_name and default_target in tandem,
+                                        # because we won't generate the correct DTS files otherwise.
 
 # A list of all stream endpoints in design
 # ----------------------------------------