fpga: Align build process for all targets
- All RFNoC capable targets now require rfnoc_image_builder to be built - `make help` is updated for all targets to provide more useful and up-to-date information - The FPGA manual is also updated - All checked-in build artifacts are now removed from git - axi_ram_fifo.yml is updated to provide include path information (required for building N3xx BIST images, which use this) Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
parent
ba5e431c5c
commit
6ef3795e42
+69
-34
@@ -8,7 +8,15 @@
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##USRP N3XX FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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## rfnoc_image_builder -y <image core file> -t <target>
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##
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## NOTE: For building N3x0 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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@@ -75,9 +83,9 @@ ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/n3xx.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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cp $(BUILD_DIR)/n3xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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else
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post_build = @echo "Skipping bitfile export."
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@@ -86,106 +94,120 @@ endif
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##
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##Supported Targets
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##-----------------
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##
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml> -t <target>
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##
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##The default image core file is called e320_rfnoc_image_core.yml.
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##Of course, a custom YAML file may be used.
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##
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##Example:
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## $ rfnoc_image_builder -y n310_rfnoc_image_core.yml -t N310_XG
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##will build the N310_XG target (10-Gigabit Ethernet on both SFP+ ports).
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##
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##UHD provides a default image core YAML file for every device type called
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##n300_rfnoc_image_core.yml, n310_rfnoc_image_core.yml, and n320_rfnoc_image_core.yml,
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##respectively.
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##For the '-t' argument, combine of the following targets with an appropriate
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##image core file:
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##
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all: N300_HG N300_XG N310_HG N310_XG N320_HG N320_XG ##(Default target)
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##N300_IP: Build IP for N300 only.
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N300_IP:
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+$(call vivado_ip,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
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##N310_IP: Build IP for N310/N320.
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##N320_IP: Build IP for N310/N320.
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N310_IP N320_IP: N3X0_IP
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N3X0_IP:
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+$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##N310_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
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N310_WX: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_WX.dts
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N310_WX: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_WX.dts
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$(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS))
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$(call post_build,N310,WX)
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##N310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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N310_HG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HG.dts
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N310_HG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HG.dts
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$(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
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$(call post_build,N310,HG)
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##N310_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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N310_XG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XG.dts
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N310_XG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XG.dts
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$(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS))
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$(call post_build,N310,XG)
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##N310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
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N310_HA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HA.dts
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N310_HA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HA.dts
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$(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS))
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$(call post_build,N310,HA)
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##N310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
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N310_XA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XA.dts
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N310_XA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XA.dts
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$(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS))
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$(call post_build,N310,XA)
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##N310_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
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N310_AA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_AA.dts
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N310_AA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_AA.dts
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$(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS))
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$(call post_build,N310,AA)
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##N300_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
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N300_WX: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_WX.dts
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N300_WX: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_WX.dts
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$(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS))
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$(call post_build,N300,WX)
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##N300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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N300_HG: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HG.dts
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N300_HG: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HG.dts
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$(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
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$(call post_build,N300,HG)
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##N300_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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N300_XG: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XG.dts
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N300_XG: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XG.dts
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$(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS))
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$(call post_build,N300,XG)
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##N300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
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N300_HA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HA.dts
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N300_HA: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HA.dts
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$(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS))
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$(call post_build,N300,HA)
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##N300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
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N300_XA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XA.dts
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N300_XA: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XA.dts
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$(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS))
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$(call post_build,N300,XA)
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##N300_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
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N300_AA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_AA.dts
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N300_AA: check-variables N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_AA.dts
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$(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS))
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$(call post_build,N300,AA)
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##N320_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
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N320_WX: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_WX.dts
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N320_WX: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_WX.dts
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$(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS))
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$(call post_build,N320,WX)
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##N320_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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N320_HG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_HG.dts
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N320_HG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_HG.dts
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$(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS))
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$(call post_build,N320,HG)
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##N320_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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N320_XG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XG.dts
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N320_XG: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XG.dts
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$(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS))
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$(call post_build,N320,XG)
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##N320_XQ: WR on SFP+ Port0, 10Gig on QSFP+ Port0,1.
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N320_XQ: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XQ.dts
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N320_XQ: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XQ.dts
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$(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS))
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$(call post_build,N320,XQ)
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##N320_AQ: 10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3.
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N320_AQ: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AQ.dts
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N320_AQ: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AQ.dts
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$(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS))
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$(call post_build,N320,AQ)
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##N320_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
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N320_AA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AA.dts
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N320_AA: check-variables N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AA.dts
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$(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS))
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$(call post_build,N320,AA)
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@@ -193,15 +215,28 @@ $(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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##
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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##N310_IP: Build IP for N310/N320. Use the -j option to build multiple IP blocks simultaneously.
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##N320_IP: Build IP for N310/N320. Use the -j option to build multiple IP blocks simultaneously.
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N310_IP N320_IP: N3X0_IP
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N3X0_IP:
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+$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
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##N300_IP: Build IP for N300 only. Use the -j option to build multiple IP blocks simultaneously.
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N300_IP:
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+$(call vivado_ip,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-N3*_*
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@rm -rf $(BUILD_BASE_DIR)/build-N3*_* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-N3*_*
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@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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+11
-16
@@ -40,22 +40,15 @@ include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
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# DUC, Replay, and of course the radio. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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@@ -139,23 +132,25 @@ $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
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$(WHITE_RABBIT_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
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$(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS) \
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$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS) \
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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@@ -1,984 +0,0 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_image_core (for n300)
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//
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// Description:
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//
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// The RFNoC Image Core contains the Verilog description of the RFNoC design
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// to be loaded onto the FPGA.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: n300_bist_rfnoc_image_core.yml
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//
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`default_nettype none
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module rfnoc_image_core #(
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parameter [31:0] CHDR_W = 64,
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parameter [31:0] PORT_W = 64,
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parameter [31:0] ETH0_W = 64,
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parameter [31:0] ETH1_W = 64,
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parameter [31:0] DMA_W = 64,
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parameter MTU = 10,
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter RADIO_NIPC = 1
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) (
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// Clocks
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input wire chdr_aclk,
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input wire ctrl_aclk,
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input wire core_arst,
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input wire radio_clk,
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input wire dram_clk,
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input wire ce_clk,
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// Basic
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input wire [ 15:0] device_id,
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// IO ports /////////////////////////
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// ctrlport_radio0
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output wire m_ctrlport_radio0_req_wr,
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output wire m_ctrlport_radio0_req_rd,
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output wire [ 19:0] m_ctrlport_radio0_req_addr,
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output wire [ 31:0] m_ctrlport_radio0_req_data,
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output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
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output wire m_ctrlport_radio0_req_has_time,
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output wire [ 63:0] m_ctrlport_radio0_req_time,
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input wire m_ctrlport_radio0_resp_ack,
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input wire [ 1:0] m_ctrlport_radio0_resp_status,
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input wire [ 31:0] m_ctrlport_radio0_resp_data,
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// time
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input wire [ 63:0] radio_time,
|
||||
// radio0
|
||||
input wire [ 63:0] radio_rx_data_radio0,
|
||||
input wire [ 1:0] radio_rx_stb_radio0,
|
||||
output wire [ 1:0] radio_rx_running_radio0,
|
||||
output wire [ 63:0] radio_tx_data_radio0,
|
||||
input wire [ 1:0] radio_tx_stb_radio0,
|
||||
output wire [ 1:0] radio_tx_running_radio0,
|
||||
// dram
|
||||
input wire axi_rst,
|
||||
output wire [ 7:0] m_axi_awid,
|
||||
output wire [ 383:0] m_axi_awaddr,
|
||||
output wire [ 63:0] m_axi_awlen,
|
||||
output wire [ 23:0] m_axi_awsize,
|
||||
output wire [ 15:0] m_axi_awburst,
|
||||
output wire [ 7:0] m_axi_awlock,
|
||||
output wire [ 31:0] m_axi_awcache,
|
||||
output wire [ 23:0] m_axi_awprot,
|
||||
output wire [ 31:0] m_axi_awqos,
|
||||
output wire [ 31:0] m_axi_awregion,
|
||||
output wire [ 7:0] m_axi_awuser,
|
||||
output wire [ 7:0] m_axi_awvalid,
|
||||
input wire [ 7:0] m_axi_awready,
|
||||
output wire [4191:0] m_axi_wdata,
|
||||
output wire [ 511:0] m_axi_wstrb,
|
||||
output wire [ 7:0] m_axi_wlast,
|
||||
output wire [ 7:0] m_axi_wuser,
|
||||
output wire [ 7:0] m_axi_wvalid,
|
||||
input wire [ 7:0] m_axi_wready,
|
||||
input wire [ 7:0] m_axi_bid,
|
||||
input wire [ 15:0] m_axi_bresp,
|
||||
input wire [ 7:0] m_axi_buser,
|
||||
input wire [ 7:0] m_axi_bvalid,
|
||||
output wire [ 7:0] m_axi_bready,
|
||||
output wire [ 7:0] m_axi_arid,
|
||||
output wire [ 383:0] m_axi_araddr,
|
||||
output wire [ 63:0] m_axi_arlen,
|
||||
output wire [ 23:0] m_axi_arsize,
|
||||
output wire [ 15:0] m_axi_arburst,
|
||||
output wire [ 7:0] m_axi_arlock,
|
||||
output wire [ 31:0] m_axi_arcache,
|
||||
output wire [ 31:0] m_axi_arprot,
|
||||
output wire [ 31:0] m_axi_arqos,
|
||||
output wire [ 31:0] m_axi_arregion,
|
||||
output wire [ 7:0] m_axi_aruser,
|
||||
output wire [ 7:0] m_axi_arvalid,
|
||||
input wire [ 7:0] m_axi_arready,
|
||||
input wire [ 7:0] m_axi_rid,
|
||||
input wire [4191:0] m_axi_rdata,
|
||||
input wire [ 15:0] m_axi_rresp,
|
||||
input wire [ 7:0] m_axi_rlast,
|
||||
input wire [ 7:0] m_axi_ruser,
|
||||
input wire [ 7:0] m_axi_rvalid,
|
||||
output wire [ 7:0] m_axi_rready,
|
||||
|
||||
// Transport Adapters ///////////////
|
||||
|
||||
// Transport 0 (eth0)
|
||||
input wire [PORT_W-1:0] s_eth0_tdata,
|
||||
input wire s_eth0_tlast,
|
||||
input wire s_eth0_tvalid,
|
||||
output wire s_eth0_tready,
|
||||
output wire [PORT_W-1:0] m_eth0_tdata,
|
||||
output wire m_eth0_tlast,
|
||||
output wire m_eth0_tvalid,
|
||||
input wire m_eth0_tready,
|
||||
// Transport 1 (eth1)
|
||||
input wire [PORT_W-1:0] s_eth1_tdata,
|
||||
input wire s_eth1_tlast,
|
||||
input wire s_eth1_tvalid,
|
||||
output wire s_eth1_tready,
|
||||
output wire [PORT_W-1:0] m_eth1_tdata,
|
||||
output wire m_eth1_tlast,
|
||||
output wire m_eth1_tvalid,
|
||||
input wire m_eth1_tready,
|
||||
// Transport 2 (dma)
|
||||
input wire [PORT_W-1:0] s_dma_tdata,
|
||||
input wire s_dma_tlast,
|
||||
input wire s_dma_tvalid,
|
||||
output wire s_dma_tready,
|
||||
output wire [PORT_W-1:0] m_dma_tdata,
|
||||
output wire m_dma_tlast,
|
||||
output wire m_dma_tvalid,
|
||||
input wire m_dma_tready
|
||||
);
|
||||
|
||||
localparam BLOCK_CHDR_W = 64;
|
||||
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
|
||||
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
|
||||
localparam EP0_W = 64;
|
||||
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
|
||||
localparam EP1_W = 64;
|
||||
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
|
||||
localparam EP4_W = 64;
|
||||
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
|
||||
localparam EP5_W = 64;
|
||||
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
|
||||
|
||||
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
|
||||
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CHDR Crossbar
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [PORT_W-1:0] xb_to_ep0_tdata ;
|
||||
wire xb_to_ep0_tlast ;
|
||||
wire xb_to_ep0_tvalid;
|
||||
wire xb_to_ep0_tready;
|
||||
wire [PORT_W-1:0] ep0_to_xb_tdata ;
|
||||
wire ep0_to_xb_tlast ;
|
||||
wire ep0_to_xb_tvalid;
|
||||
wire ep0_to_xb_tready;
|
||||
wire [PORT_W-1:0] xb_to_ep1_tdata ;
|
||||
wire xb_to_ep1_tlast ;
|
||||
wire xb_to_ep1_tvalid;
|
||||
wire xb_to_ep1_tready;
|
||||
wire [PORT_W-1:0] ep1_to_xb_tdata ;
|
||||
wire ep1_to_xb_tlast ;
|
||||
wire ep1_to_xb_tvalid;
|
||||
wire ep1_to_xb_tready;
|
||||
wire [PORT_W-1:0] xb_to_ep4_tdata ;
|
||||
wire xb_to_ep4_tlast ;
|
||||
wire xb_to_ep4_tvalid;
|
||||
wire xb_to_ep4_tready;
|
||||
wire [PORT_W-1:0] ep4_to_xb_tdata ;
|
||||
wire ep4_to_xb_tlast ;
|
||||
wire ep4_to_xb_tvalid;
|
||||
wire ep4_to_xb_tready;
|
||||
wire [PORT_W-1:0] xb_to_ep5_tdata ;
|
||||
wire xb_to_ep5_tlast ;
|
||||
wire xb_to_ep5_tvalid;
|
||||
wire xb_to_ep5_tready;
|
||||
wire [PORT_W-1:0] ep5_to_xb_tdata ;
|
||||
wire ep5_to_xb_tlast ;
|
||||
wire ep5_to_xb_tvalid;
|
||||
wire ep5_to_xb_tready;
|
||||
|
||||
chdr_crossbar_nxn #(
|
||||
.PORT_W (PORT_W),
|
||||
.NPORTS (7),
|
||||
.CHDR_WIDTHS ({EP5_W, EP4_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
|
||||
.DEFAULT_PORT (0),
|
||||
.ROUTES ({ 7'b1111111,
|
||||
7'b1111111,
|
||||
7'b1111111,
|
||||
7'b1111111,
|
||||
7'b1111100,
|
||||
7'b1111010,
|
||||
7'b1111001 }),
|
||||
.BYTE_MTU (BYTE_MTU),
|
||||
.ROUTE_TBL_SIZE (6),
|
||||
.MUX_ALLOC ("ROUND-ROBIN"),
|
||||
.OPTIMIZE ("AREA"),
|
||||
.NPORTS_MGMT (3),
|
||||
.EXT_RTCFG_PORT (0),
|
||||
.PROTOVER (PROTOVER)
|
||||
) chdr_crossbar_nxn_i (
|
||||
.clk (rfnoc_chdr_clk),
|
||||
.reset (rfnoc_chdr_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_tdata ({ep5_to_xb_tdata , ep4_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }),
|
||||
.s_axis_tlast ({ep5_to_xb_tlast , ep4_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }),
|
||||
.s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
|
||||
.s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
|
||||
.m_axis_tdata ({xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }),
|
||||
.m_axis_tlast ({xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }),
|
||||
.m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
|
||||
.m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
|
||||
.ext_rtcfg_stb (1'h0),
|
||||
.ext_rtcfg_addr (16'h0),
|
||||
.ext_rtcfg_data (32'h0),
|
||||
.ext_rtcfg_ack ()
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Stream Endpoints
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
||||
// Otherwise, make sure it's at least two MTU-sized packets.
|
||||
localparam REQ_BUFF_SIZE_EP0 = 16384;
|
||||
localparam INGRESS_BUFF_SIZE_EP0 =
|
||||
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
|
||||
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
|
||||
$clog2(REQ_BUFF_SIZE_EP0);
|
||||
|
||||
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
|
||||
wire m_ep0_out0_tlast;
|
||||
wire m_ep0_out0_tvalid;
|
||||
wire m_ep0_out0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
|
||||
wire s_ep0_in0_tlast;
|
||||
wire s_ep0_in0_tvalid;
|
||||
wire s_ep0_in0_tready;
|
||||
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
|
||||
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
|
||||
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
|
||||
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
|
||||
|
||||
chdr_stream_endpoint #(
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.PROTOVER (PROTOVER),
|
||||
.CHDR_W (EP0_W),
|
||||
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
||||
.AXIS_CTRL_EN (1),
|
||||
.AXIS_DATA_EN (1),
|
||||
.NUM_DATA_I (1),
|
||||
.NUM_DATA_O (1),
|
||||
.INST_NUM (0),
|
||||
.CTRL_XBAR_PORT (1),
|
||||
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
|
||||
.MTU (EP0_MTU),
|
||||
.REPORT_STRM_ERRS (1)
|
||||
) ep0_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_chdr_tdata (xb_to_ep0_tdata),
|
||||
.s_axis_chdr_tlast (xb_to_ep0_tlast),
|
||||
.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
|
||||
.s_axis_chdr_tready (xb_to_ep0_tready),
|
||||
.m_axis_chdr_tdata (ep0_to_xb_tdata),
|
||||
.m_axis_chdr_tlast (ep0_to_xb_tlast),
|
||||
.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
|
||||
.m_axis_chdr_tready (ep0_to_xb_tready),
|
||||
.s_axis_data_tdata ({s_ep0_in0_tdata}),
|
||||
.s_axis_data_tlast ({s_ep0_in0_tlast}),
|
||||
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
|
||||
.s_axis_data_tready ({s_ep0_in0_tready}),
|
||||
.m_axis_data_tdata ({m_ep0_out0_tdata}),
|
||||
.m_axis_data_tlast ({m_ep0_out0_tlast}),
|
||||
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
|
||||
.m_axis_data_tready ({m_ep0_out0_tready}),
|
||||
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
|
||||
.strm_seq_err_stb (),
|
||||
.strm_data_err_stb (),
|
||||
.strm_route_err_stb (),
|
||||
.signal_data_err (1'b0)
|
||||
);
|
||||
|
||||
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
||||
// Otherwise, make sure it's at least two MTU-sized packets.
|
||||
localparam REQ_BUFF_SIZE_EP1 = 16384;
|
||||
localparam INGRESS_BUFF_SIZE_EP1 =
|
||||
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
|
||||
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
|
||||
$clog2(REQ_BUFF_SIZE_EP1);
|
||||
|
||||
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
|
||||
wire m_ep1_out0_tlast;
|
||||
wire m_ep1_out0_tvalid;
|
||||
wire m_ep1_out0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
|
||||
wire s_ep1_in0_tlast;
|
||||
wire s_ep1_in0_tvalid;
|
||||
wire s_ep1_in0_tready;
|
||||
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
|
||||
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
|
||||
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
|
||||
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
|
||||
|
||||
chdr_stream_endpoint #(
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.PROTOVER (PROTOVER),
|
||||
.CHDR_W (EP1_W),
|
||||
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
||||
.AXIS_CTRL_EN (0),
|
||||
.AXIS_DATA_EN (1),
|
||||
.NUM_DATA_I (1),
|
||||
.NUM_DATA_O (1),
|
||||
.INST_NUM (1),
|
||||
.CTRL_XBAR_PORT (2),
|
||||
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
|
||||
.MTU (EP1_MTU),
|
||||
.REPORT_STRM_ERRS (1)
|
||||
) ep1_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_chdr_tdata (xb_to_ep1_tdata),
|
||||
.s_axis_chdr_tlast (xb_to_ep1_tlast),
|
||||
.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
|
||||
.s_axis_chdr_tready (xb_to_ep1_tready),
|
||||
.m_axis_chdr_tdata (ep1_to_xb_tdata),
|
||||
.m_axis_chdr_tlast (ep1_to_xb_tlast),
|
||||
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
|
||||
.m_axis_chdr_tready (ep1_to_xb_tready),
|
||||
.s_axis_data_tdata ({s_ep1_in0_tdata}),
|
||||
.s_axis_data_tlast ({s_ep1_in0_tlast}),
|
||||
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
|
||||
.s_axis_data_tready ({s_ep1_in0_tready}),
|
||||
.m_axis_data_tdata ({m_ep1_out0_tdata}),
|
||||
.m_axis_data_tlast ({m_ep1_out0_tlast}),
|
||||
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
|
||||
.m_axis_data_tready ({m_ep1_out0_tready}),
|
||||
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
|
||||
.strm_seq_err_stb (),
|
||||
.strm_data_err_stb (),
|
||||
.strm_route_err_stb (),
|
||||
.signal_data_err (1'b0)
|
||||
);
|
||||
|
||||
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
||||
// Otherwise, make sure it's at least two MTU-sized packets.
|
||||
localparam REQ_BUFF_SIZE_EP4 = 16384;
|
||||
localparam INGRESS_BUFF_SIZE_EP4 =
|
||||
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
|
||||
REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
|
||||
$clog2(REQ_BUFF_SIZE_EP4);
|
||||
|
||||
wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
|
||||
wire m_ep4_out0_tlast;
|
||||
wire m_ep4_out0_tvalid;
|
||||
wire m_ep4_out0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
|
||||
wire s_ep4_in0_tlast;
|
||||
wire s_ep4_in0_tvalid;
|
||||
wire s_ep4_in0_tready;
|
||||
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
|
||||
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
|
||||
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
|
||||
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
|
||||
|
||||
chdr_stream_endpoint #(
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.PROTOVER (PROTOVER),
|
||||
.CHDR_W (EP4_W),
|
||||
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
||||
.AXIS_CTRL_EN (0),
|
||||
.AXIS_DATA_EN (1),
|
||||
.NUM_DATA_I (1),
|
||||
.NUM_DATA_O (1),
|
||||
.INST_NUM (2),
|
||||
.CTRL_XBAR_PORT (3),
|
||||
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
|
||||
.MTU (EP4_MTU),
|
||||
.REPORT_STRM_ERRS (1)
|
||||
) ep4_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_chdr_tdata (xb_to_ep4_tdata),
|
||||
.s_axis_chdr_tlast (xb_to_ep4_tlast),
|
||||
.s_axis_chdr_tvalid (xb_to_ep4_tvalid),
|
||||
.s_axis_chdr_tready (xb_to_ep4_tready),
|
||||
.m_axis_chdr_tdata (ep4_to_xb_tdata),
|
||||
.m_axis_chdr_tlast (ep4_to_xb_tlast),
|
||||
.m_axis_chdr_tvalid (ep4_to_xb_tvalid),
|
||||
.m_axis_chdr_tready (ep4_to_xb_tready),
|
||||
.s_axis_data_tdata ({s_ep4_in0_tdata}),
|
||||
.s_axis_data_tlast ({s_ep4_in0_tlast}),
|
||||
.s_axis_data_tvalid ({s_ep4_in0_tvalid}),
|
||||
.s_axis_data_tready ({s_ep4_in0_tready}),
|
||||
.m_axis_data_tdata ({m_ep4_out0_tdata}),
|
||||
.m_axis_data_tlast ({m_ep4_out0_tlast}),
|
||||
.m_axis_data_tvalid ({m_ep4_out0_tvalid}),
|
||||
.m_axis_data_tready ({m_ep4_out0_tready}),
|
||||
.s_axis_ctrl_tdata (s_ep4_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_ep4_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_ep4_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_ep4_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_ep4_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_ep4_ctrl_tready),
|
||||
.strm_seq_err_stb (),
|
||||
.strm_data_err_stb (),
|
||||
.strm_route_err_stb (),
|
||||
.signal_data_err (1'b0)
|
||||
);
|
||||
|
||||
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
||||
// Otherwise, make sure it's at least two MTU-sized packets.
|
||||
localparam REQ_BUFF_SIZE_EP5 = 16384;
|
||||
localparam INGRESS_BUFF_SIZE_EP5 =
|
||||
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
|
||||
REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
|
||||
$clog2(REQ_BUFF_SIZE_EP5);
|
||||
|
||||
wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
|
||||
wire m_ep5_out0_tlast;
|
||||
wire m_ep5_out0_tvalid;
|
||||
wire m_ep5_out0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
|
||||
wire s_ep5_in0_tlast;
|
||||
wire s_ep5_in0_tvalid;
|
||||
wire s_ep5_in0_tready;
|
||||
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
|
||||
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
|
||||
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
|
||||
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
|
||||
|
||||
chdr_stream_endpoint #(
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.PROTOVER (PROTOVER),
|
||||
.CHDR_W (EP5_W),
|
||||
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
||||
.AXIS_CTRL_EN (0),
|
||||
.AXIS_DATA_EN (1),
|
||||
.NUM_DATA_I (1),
|
||||
.NUM_DATA_O (1),
|
||||
.INST_NUM (3),
|
||||
.CTRL_XBAR_PORT (4),
|
||||
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
|
||||
.MTU (EP5_MTU),
|
||||
.REPORT_STRM_ERRS (1)
|
||||
) ep5_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_chdr_tdata (xb_to_ep5_tdata),
|
||||
.s_axis_chdr_tlast (xb_to_ep5_tlast),
|
||||
.s_axis_chdr_tvalid (xb_to_ep5_tvalid),
|
||||
.s_axis_chdr_tready (xb_to_ep5_tready),
|
||||
.m_axis_chdr_tdata (ep5_to_xb_tdata),
|
||||
.m_axis_chdr_tlast (ep5_to_xb_tlast),
|
||||
.m_axis_chdr_tvalid (ep5_to_xb_tvalid),
|
||||
.m_axis_chdr_tready (ep5_to_xb_tready),
|
||||
.s_axis_data_tdata ({s_ep5_in0_tdata}),
|
||||
.s_axis_data_tlast ({s_ep5_in0_tlast}),
|
||||
.s_axis_data_tvalid ({s_ep5_in0_tvalid}),
|
||||
.s_axis_data_tready ({s_ep5_in0_tready}),
|
||||
.m_axis_data_tdata ({m_ep5_out0_tdata}),
|
||||
.m_axis_data_tlast ({m_ep5_out0_tlast}),
|
||||
.m_axis_data_tvalid ({m_ep5_out0_tvalid}),
|
||||
.m_axis_data_tready ({m_ep5_out0_tready}),
|
||||
.s_axis_ctrl_tdata (s_ep5_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_ep5_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_ep5_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_ep5_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_ep5_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_ep5_ctrl_tready),
|
||||
.strm_seq_err_stb (),
|
||||
.strm_data_err_stb (),
|
||||
.strm_route_err_stb (),
|
||||
.signal_data_err (1'b0)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Control Crossbar
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
|
||||
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
|
||||
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
|
||||
wire m_core_ctrl_tready, s_core_ctrl_tready;
|
||||
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
|
||||
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
|
||||
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
|
||||
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
|
||||
wire [31:0] m_fifo0_ctrl_tdata, s_fifo0_ctrl_tdata;
|
||||
wire m_fifo0_ctrl_tlast, s_fifo0_ctrl_tlast;
|
||||
wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid;
|
||||
wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready;
|
||||
|
||||
axis_ctrl_crossbar_nxn #(
|
||||
.WIDTH (32),
|
||||
.NPORTS (4),
|
||||
.TOPOLOGY ("TORUS"),
|
||||
.INGRESS_BUFF_SIZE(5),
|
||||
.ROUTER_BUFF_SIZE (5),
|
||||
.ROUTING_ALLOC ("WORMHOLE"),
|
||||
.SWITCH_ALLOC ("PRIO")
|
||||
) ctrl_xb_i (
|
||||
.clk (rfnoc_ctrl_clk),
|
||||
.reset (rfnoc_ctrl_rst),
|
||||
.s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
||||
.s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
||||
.s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
||||
.s_axis_tready ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
||||
.m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
||||
.m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
||||
.m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
||||
.m_axis_tready ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
||||
.deadlock_detected()
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// RFNoC Core Kernel
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status;
|
||||
|
||||
rfnoc_core_kernel #(
|
||||
.PROTOVER (PROTOVER),
|
||||
.DEVICE_TYPE (16'h1300),
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.SAFE_START_CLKS (0),
|
||||
.NUM_BLOCKS (2),
|
||||
.NUM_STREAM_ENDPOINTS(4),
|
||||
.NUM_ENDPOINTS_CTRL (1),
|
||||
.NUM_TRANSPORTS (3),
|
||||
.NUM_EDGES (8),
|
||||
.CHDR_XBAR_PRESENT (1),
|
||||
.EDGE_TBL ({
|
||||
{10'd06, 6'd01, 10'd04, 6'd00},
|
||||
{10'd04, 6'd00, 10'd06, 6'd01},
|
||||
{10'd06, 6'd00, 10'd03, 6'd00},
|
||||
{10'd03, 6'd00, 10'd06, 6'd00},
|
||||
{10'd05, 6'd01, 10'd02, 6'd00},
|
||||
{10'd02, 6'd00, 10'd05, 6'd01},
|
||||
{10'd05, 6'd00, 10'd01, 6'd00},
|
||||
{10'd01, 6'd00, 10'd05, 6'd00}
|
||||
})
|
||||
) core_kernel_i (
|
||||
.chdr_aclk (chdr_aclk),
|
||||
.chdr_aclk_locked (1'b1),
|
||||
.ctrl_aclk (ctrl_aclk),
|
||||
.ctrl_aclk_locked (1'b1),
|
||||
.core_arst (core_arst),
|
||||
.core_chdr_clk (rfnoc_chdr_clk),
|
||||
.core_chdr_rst (rfnoc_chdr_rst),
|
||||
.core_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.core_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_core_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_core_ctrl_tready),
|
||||
.device_id (device_id),
|
||||
.rfnoc_core_config (rfnoc_core_config),
|
||||
.rfnoc_core_status (rfnoc_core_status)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Blocks
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
//-----------------------------------
|
||||
// radio0
|
||||
//-----------------------------------
|
||||
|
||||
wire radio0_radio_clk;
|
||||
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
|
||||
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
|
||||
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
|
||||
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
|
||||
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
|
||||
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
|
||||
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
|
||||
|
||||
// ctrlport
|
||||
wire radio0_m_ctrlport_req_wr;
|
||||
wire radio0_m_ctrlport_req_rd;
|
||||
wire [ 19:0] radio0_m_ctrlport_req_addr;
|
||||
wire [ 31:0] radio0_m_ctrlport_req_data;
|
||||
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
|
||||
wire radio0_m_ctrlport_req_has_time;
|
||||
wire [ 63:0] radio0_m_ctrlport_req_time;
|
||||
wire radio0_m_ctrlport_resp_ack;
|
||||
wire [ 1:0] radio0_m_ctrlport_resp_status;
|
||||
wire [ 31:0] radio0_m_ctrlport_resp_data;
|
||||
// time
|
||||
wire [ 63:0] radio0_radio_time;
|
||||
// radio
|
||||
wire [32*1*2-1:0] radio0_radio_rx_data;
|
||||
wire [ 1:0] radio0_radio_rx_stb;
|
||||
wire [ 1:0] radio0_radio_rx_running;
|
||||
wire [32*1*2-1:0] radio0_radio_tx_data;
|
||||
wire [ 1:0] radio0_radio_tx_stb;
|
||||
wire [ 1:0] radio0_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (2),
|
||||
.CHDR_W (BLOCK_CHDR_W),
|
||||
.NUM_PORTS (2),
|
||||
.NIPC (1),
|
||||
.ITEM_W (32),
|
||||
.MTU (BLOCK_MTU)
|
||||
) b_radio0_0 (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.radio_clk (radio0_radio_clk),
|
||||
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
|
||||
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
|
||||
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
|
||||
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
|
||||
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
|
||||
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
|
||||
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
|
||||
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
|
||||
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
|
||||
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
|
||||
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
|
||||
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
|
||||
.radio_time (radio0_radio_time),
|
||||
.radio_rx_data (radio0_radio_rx_data),
|
||||
.radio_rx_stb (radio0_radio_rx_stb),
|
||||
.radio_rx_running (radio0_radio_rx_running),
|
||||
.radio_tx_data (radio0_radio_tx_data),
|
||||
.radio_tx_stb (radio0_radio_tx_stb),
|
||||
.radio_tx_running (radio0_radio_tx_running),
|
||||
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
|
||||
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
|
||||
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
|
||||
.s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
|
||||
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
|
||||
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
|
||||
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
|
||||
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
|
||||
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
|
||||
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
|
||||
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
|
||||
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
|
||||
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
|
||||
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
|
||||
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
|
||||
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
|
||||
);
|
||||
|
||||
//-----------------------------------
|
||||
// fifo0
|
||||
//-----------------------------------
|
||||
|
||||
wire fifo0_mem_clk;
|
||||
wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
|
||||
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
|
||||
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
|
||||
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
|
||||
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
|
||||
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
|
||||
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
|
||||
|
||||
// axi_ram
|
||||
wire fifo0_axi_rst;
|
||||
wire [ 7:0] fifo0_m_axi_awid;
|
||||
wire [ 383:0] fifo0_m_axi_awaddr;
|
||||
wire [ 63:0] fifo0_m_axi_awlen;
|
||||
wire [ 23:0] fifo0_m_axi_awsize;
|
||||
wire [ 15:0] fifo0_m_axi_awburst;
|
||||
wire [ 7:0] fifo0_m_axi_awlock;
|
||||
wire [ 31:0] fifo0_m_axi_awcache;
|
||||
wire [ 23:0] fifo0_m_axi_awprot;
|
||||
wire [ 31:0] fifo0_m_axi_awqos;
|
||||
wire [ 31:0] fifo0_m_axi_awregion;
|
||||
wire [ 7:0] fifo0_m_axi_awuser;
|
||||
wire [ 7:0] fifo0_m_axi_awvalid;
|
||||
wire [ 7:0] fifo0_m_axi_awready;
|
||||
wire [4191:0] fifo0_m_axi_wdata;
|
||||
wire [ 511:0] fifo0_m_axi_wstrb;
|
||||
wire [ 7:0] fifo0_m_axi_wlast;
|
||||
wire [ 7:0] fifo0_m_axi_wuser;
|
||||
wire [ 7:0] fifo0_m_axi_wvalid;
|
||||
wire [ 7:0] fifo0_m_axi_wready;
|
||||
wire [ 7:0] fifo0_m_axi_bid;
|
||||
wire [ 15:0] fifo0_m_axi_bresp;
|
||||
wire [ 7:0] fifo0_m_axi_buser;
|
||||
wire [ 7:0] fifo0_m_axi_bvalid;
|
||||
wire [ 7:0] fifo0_m_axi_bready;
|
||||
wire [ 7:0] fifo0_m_axi_arid;
|
||||
wire [ 383:0] fifo0_m_axi_araddr;
|
||||
wire [ 63:0] fifo0_m_axi_arlen;
|
||||
wire [ 23:0] fifo0_m_axi_arsize;
|
||||
wire [ 15:0] fifo0_m_axi_arburst;
|
||||
wire [ 7:0] fifo0_m_axi_arlock;
|
||||
wire [ 31:0] fifo0_m_axi_arcache;
|
||||
wire [ 31:0] fifo0_m_axi_arprot;
|
||||
wire [ 31:0] fifo0_m_axi_arqos;
|
||||
wire [ 31:0] fifo0_m_axi_arregion;
|
||||
wire [ 7:0] fifo0_m_axi_aruser;
|
||||
wire [ 7:0] fifo0_m_axi_arvalid;
|
||||
wire [ 7:0] fifo0_m_axi_arready;
|
||||
wire [ 7:0] fifo0_m_axi_rid;
|
||||
wire [4191:0] fifo0_m_axi_rdata;
|
||||
wire [ 15:0] fifo0_m_axi_rresp;
|
||||
wire [ 7:0] fifo0_m_axi_rlast;
|
||||
wire [ 7:0] fifo0_m_axi_ruser;
|
||||
wire [ 7:0] fifo0_m_axi_rvalid;
|
||||
wire [ 7:0] fifo0_m_axi_rready;
|
||||
|
||||
rfnoc_block_axi_ram_fifo #(
|
||||
.THIS_PORTID (3),
|
||||
.CHDR_W (BLOCK_CHDR_W),
|
||||
.NUM_PORTS (4),
|
||||
.MEM_DATA_W (64),
|
||||
.MEM_ADDR_W (31),
|
||||
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
|
||||
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
|
||||
.MEM_CLK_RATE (303819444),
|
||||
.IN_FIFO_SIZE (),
|
||||
.OUT_FIFO_SIZE (),
|
||||
.MTU (BLOCK_MTU)
|
||||
) b_fifo0_1 (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.mem_clk (fifo0_mem_clk),
|
||||
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
|
||||
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
|
||||
.axi_rst (fifo0_axi_rst),
|
||||
.m_axi_awid (fifo0_m_axi_awid),
|
||||
.m_axi_awaddr (fifo0_m_axi_awaddr),
|
||||
.m_axi_awlen (fifo0_m_axi_awlen),
|
||||
.m_axi_awsize (fifo0_m_axi_awsize),
|
||||
.m_axi_awburst (fifo0_m_axi_awburst),
|
||||
.m_axi_awlock (fifo0_m_axi_awlock),
|
||||
.m_axi_awcache (fifo0_m_axi_awcache),
|
||||
.m_axi_awprot (fifo0_m_axi_awprot),
|
||||
.m_axi_awqos (fifo0_m_axi_awqos),
|
||||
.m_axi_awregion (fifo0_m_axi_awregion),
|
||||
.m_axi_awuser (fifo0_m_axi_awuser),
|
||||
.m_axi_awvalid (fifo0_m_axi_awvalid),
|
||||
.m_axi_awready (fifo0_m_axi_awready),
|
||||
.m_axi_wdata (fifo0_m_axi_wdata),
|
||||
.m_axi_wstrb (fifo0_m_axi_wstrb),
|
||||
.m_axi_wlast (fifo0_m_axi_wlast),
|
||||
.m_axi_wuser (fifo0_m_axi_wuser),
|
||||
.m_axi_wvalid (fifo0_m_axi_wvalid),
|
||||
.m_axi_wready (fifo0_m_axi_wready),
|
||||
.m_axi_bid (fifo0_m_axi_bid),
|
||||
.m_axi_bresp (fifo0_m_axi_bresp),
|
||||
.m_axi_buser (fifo0_m_axi_buser),
|
||||
.m_axi_bvalid (fifo0_m_axi_bvalid),
|
||||
.m_axi_bready (fifo0_m_axi_bready),
|
||||
.m_axi_arid (fifo0_m_axi_arid),
|
||||
.m_axi_araddr (fifo0_m_axi_araddr),
|
||||
.m_axi_arlen (fifo0_m_axi_arlen),
|
||||
.m_axi_arsize (fifo0_m_axi_arsize),
|
||||
.m_axi_arburst (fifo0_m_axi_arburst),
|
||||
.m_axi_arlock (fifo0_m_axi_arlock),
|
||||
.m_axi_arcache (fifo0_m_axi_arcache),
|
||||
.m_axi_arprot (fifo0_m_axi_arprot),
|
||||
.m_axi_arqos (fifo0_m_axi_arqos),
|
||||
.m_axi_arregion (fifo0_m_axi_arregion),
|
||||
.m_axi_aruser (fifo0_m_axi_aruser),
|
||||
.m_axi_arvalid (fifo0_m_axi_arvalid),
|
||||
.m_axi_arready (fifo0_m_axi_arready),
|
||||
.m_axi_rid (fifo0_m_axi_rid),
|
||||
.m_axi_rdata (fifo0_m_axi_rdata),
|
||||
.m_axi_rresp (fifo0_m_axi_rresp),
|
||||
.m_axi_rlast (fifo0_m_axi_rlast),
|
||||
.m_axi_ruser (fifo0_m_axi_ruser),
|
||||
.m_axi_rvalid (fifo0_m_axi_rvalid),
|
||||
.m_axi_rready (fifo0_m_axi_rready),
|
||||
.s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
|
||||
.s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
|
||||
.s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
|
||||
.s_rfnoc_chdr_tready ({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}),
|
||||
.m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }),
|
||||
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
|
||||
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
|
||||
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
|
||||
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
|
||||
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
|
||||
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
|
||||
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
|
||||
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
|
||||
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
|
||||
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
|
||||
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Static Router
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
|
||||
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
|
||||
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
|
||||
assign m_ep0_out0_tready = s_radio0_in_0_tready;
|
||||
|
||||
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
|
||||
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
|
||||
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
|
||||
assign m_radio0_out_0_tready = s_ep0_in0_tready;
|
||||
|
||||
assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
|
||||
assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
|
||||
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
|
||||
assign m_ep1_out0_tready = s_radio0_in_1_tready;
|
||||
|
||||
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
|
||||
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
|
||||
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
|
||||
assign m_radio0_out_1_tready = s_ep1_in0_tready;
|
||||
|
||||
assign s_fifo0_in_0_tdata = m_ep4_out0_tdata;
|
||||
assign s_fifo0_in_0_tlast = m_ep4_out0_tlast;
|
||||
assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid;
|
||||
assign m_ep4_out0_tready = s_fifo0_in_0_tready;
|
||||
|
||||
assign s_ep4_in0_tdata = m_fifo0_out_0_tdata;
|
||||
assign s_ep4_in0_tlast = m_fifo0_out_0_tlast;
|
||||
assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid;
|
||||
assign m_fifo0_out_0_tready = s_ep4_in0_tready;
|
||||
|
||||
assign s_fifo0_in_1_tdata = m_ep5_out0_tdata;
|
||||
assign s_fifo0_in_1_tlast = m_ep5_out0_tlast;
|
||||
assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid;
|
||||
assign m_ep5_out0_tready = s_fifo0_in_1_tready;
|
||||
|
||||
assign s_ep5_in0_tdata = m_fifo0_out_1_tdata;
|
||||
assign s_ep5_in0_tlast = m_fifo0_out_1_tlast;
|
||||
assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid;
|
||||
assign m_fifo0_out_1_tready = s_ep5_in0_tready;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Unused Ports
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}};
|
||||
assign s_fifo0_in_2_tlast = 1'b0;
|
||||
assign s_fifo0_in_2_tvalid = 1'b0;
|
||||
assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}};
|
||||
assign s_fifo0_in_3_tlast = 1'b0;
|
||||
assign s_fifo0_in_3_tvalid = 1'b0;
|
||||
assign m_fifo0_out_2_tready = 1'b1;
|
||||
assign m_fifo0_out_3_tready = 1'b1;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Clock Domains and Resets
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign radio0_radio_clk = radio_clk;
|
||||
assign fifo0_mem_clk = dram_clk;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// IO Port Connection
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Master/Slave Connections:
|
||||
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
|
||||
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
|
||||
assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr;
|
||||
assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data;
|
||||
assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en;
|
||||
assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time;
|
||||
assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time;
|
||||
assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack;
|
||||
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
|
||||
assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
|
||||
|
||||
assign fifo0_axi_rst = axi_rst;
|
||||
assign m_axi_awid = fifo0_m_axi_awid;
|
||||
assign m_axi_awaddr = fifo0_m_axi_awaddr;
|
||||
assign m_axi_awlen = fifo0_m_axi_awlen;
|
||||
assign m_axi_awsize = fifo0_m_axi_awsize;
|
||||
assign m_axi_awburst = fifo0_m_axi_awburst;
|
||||
assign m_axi_awlock = fifo0_m_axi_awlock;
|
||||
assign m_axi_awcache = fifo0_m_axi_awcache;
|
||||
assign m_axi_awprot = fifo0_m_axi_awprot;
|
||||
assign m_axi_awqos = fifo0_m_axi_awqos;
|
||||
assign m_axi_awregion = fifo0_m_axi_awregion;
|
||||
assign m_axi_awuser = fifo0_m_axi_awuser;
|
||||
assign m_axi_awvalid = fifo0_m_axi_awvalid;
|
||||
assign fifo0_m_axi_awready = m_axi_awready;
|
||||
assign m_axi_wdata = fifo0_m_axi_wdata;
|
||||
assign m_axi_wstrb = fifo0_m_axi_wstrb;
|
||||
assign m_axi_wlast = fifo0_m_axi_wlast;
|
||||
assign m_axi_wuser = fifo0_m_axi_wuser;
|
||||
assign m_axi_wvalid = fifo0_m_axi_wvalid;
|
||||
assign fifo0_m_axi_wready = m_axi_wready;
|
||||
assign fifo0_m_axi_bid = m_axi_bid;
|
||||
assign fifo0_m_axi_bresp = m_axi_bresp;
|
||||
assign fifo0_m_axi_buser = m_axi_buser;
|
||||
assign fifo0_m_axi_bvalid = m_axi_bvalid;
|
||||
assign m_axi_bready = fifo0_m_axi_bready;
|
||||
assign m_axi_arid = fifo0_m_axi_arid;
|
||||
assign m_axi_araddr = fifo0_m_axi_araddr;
|
||||
assign m_axi_arlen = fifo0_m_axi_arlen;
|
||||
assign m_axi_arsize = fifo0_m_axi_arsize;
|
||||
assign m_axi_arburst = fifo0_m_axi_arburst;
|
||||
assign m_axi_arlock = fifo0_m_axi_arlock;
|
||||
assign m_axi_arcache = fifo0_m_axi_arcache;
|
||||
assign m_axi_arprot = fifo0_m_axi_arprot;
|
||||
assign m_axi_arqos = fifo0_m_axi_arqos;
|
||||
assign m_axi_arregion = fifo0_m_axi_arregion;
|
||||
assign m_axi_aruser = fifo0_m_axi_aruser;
|
||||
assign m_axi_arvalid = fifo0_m_axi_arvalid;
|
||||
assign fifo0_m_axi_arready = m_axi_arready;
|
||||
assign fifo0_m_axi_rid = m_axi_rid;
|
||||
assign fifo0_m_axi_rdata = m_axi_rdata;
|
||||
assign fifo0_m_axi_rresp = m_axi_rresp;
|
||||
assign fifo0_m_axi_rlast = m_axi_rlast;
|
||||
assign fifo0_m_axi_ruser = m_axi_ruser;
|
||||
assign fifo0_m_axi_rvalid = m_axi_rvalid;
|
||||
assign m_axi_rready = fifo0_m_axi_rready;
|
||||
|
||||
assign radio0_radio_rx_data = radio_rx_data_radio0;
|
||||
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
|
||||
assign radio_rx_running_radio0 = radio0_radio_rx_running;
|
||||
assign radio_tx_data_radio0 = radio0_radio_tx_data;
|
||||
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
|
||||
assign radio_tx_running_radio0 = radio0_radio_tx_running;
|
||||
|
||||
// Broadcaster/Listener Connections:
|
||||
assign radio0_radio_time = radio_time;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n300)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: n300_bist_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -8,8 +8,10 @@ license: >- # License information used in file heade
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'n300'
|
||||
image_core_name: 'n300_bist' # Name to use for the RFNoC Image Core files
|
||||
default_target: 'N300_AA'
|
||||
image_core_name: 'usrp_n300_fpga_AA' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n300)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: n300_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -9,6 +9,9 @@ version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'n300'
|
||||
default_target: 'N300_HG'
|
||||
image_core_name: 'usrp_n300_fpga_HG' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n310)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: n310_bist_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -8,8 +8,10 @@ license: >- # License information used in file heade
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this block
|
||||
device: 'n310'
|
||||
image_core_name: 'n310_bist' # Name to use for the RFNoC Image Core files
|
||||
default_target: 'N310_AA'
|
||||
image_core_name: 'usrp_n310_fpga_AA' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n310)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: n310_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -9,6 +9,9 @@ version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'n310'
|
||||
default_target: 'N310_HG'
|
||||
image_core_name: 'usrp_n310_fpga_HG' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n320)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: n320_bist_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -8,8 +8,10 @@ license: >- # License information used in file heade
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this block
|
||||
device: 'n320'
|
||||
image_core_name: 'n320_bist' # Name to use for the RFNoC Image Core files
|
||||
default_target: 'N320_AA'
|
||||
image_core_name: 'usrp_n320_fpga_AA' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n320)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: n320_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -9,6 +9,9 @@ version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'n320'
|
||||
default_target: 'N320_HG'
|
||||
image_core_name: 'usrp_n320_fpga_HG' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user