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fpga: Align build process for all targets

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- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
2024-06-11 10:20:08 +02:00
committed by Joerg Hofrichter
parent ba5e431c5c
commit 6ef3795e42
37 changed files with 527 additions and 9597 deletions
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top/e320/e320_rfnoc_image_core.yml
+4 -1
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@@ -8,7 +8,10 @@ license: >- # License information used in file heade
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'e320'
default_target: 'E320_1G'
default_target: 'E320_1G' # Target. This controls which transports are instantiated.
image_core_name: 'usrp_e320_fpga_1G' # Name to use for the generated output files.
# Change image_core_name and default_target in tandem,
# because we won't generate the correct DTS files otherwise.
# A list of all stream endpoints in design
# ----------------------------------------