miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: Align build process for all targets

Browse Source 
- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
2024-06-11 10:20:08 +02:00
committed by Joerg Hofrichter
parent ba5e431c5c
commit 6ef3795e42
37 changed files with 527 additions and 9597 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e320/Makefile
+52 -24
View File
@@ -4,10 +4,18 @@
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP E3XX FPGA Help
##USRP E32X FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
## rfnoc_image_builder -y <image core file> -t <target>
##
## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
## environment, and run Vivado to build a bitfile.
##
## There exist some special make targets which can be called directly like this:
##
## make <Targets> <Options>
##
##Output:
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
@@ -40,21 +48,19 @@ ifndef TARGET
endif
TOP ?= e320
DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
# post_build($1=Device, $2=Option)
# post_build($1=Target)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream file..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/e320.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_DIR)/e320.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Exporting build report..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(1)";
else
post_build = @echo "Skipping bitfile export."
endif
@@ -62,42 +68,64 @@ endif
##
##Supported Targets
##-----------------
##
##Reminder: Targets are built by calling
##
## $ rfnoc_image_builder -y <image core file.yml> -t <target>
##
##The default image core file is called e320_rfnoc_image_core.yml.
##Of course, a custom YAML file may be used.
##
##Example:
## $ rfnoc_image_builder -y e320_rfnoc_image_core.yml --target E320_XG
##will build the E320_XG target (10-Gigabit Ethernet on the SFP+ port).
##
##The following targets are supported:
all: E320_1G E320_XG ##(Default target)
##E320_IP: Build IP for E320 only.
E320_IP:
+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
check-variables:
ifndef IMAGE_CORE_NAME
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
endif
ifndef BUILD_DIR
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
endif
##E320_1G: 1GigE on SFP+ Port.
E320_1G: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
E320_1G: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
$(call vivado_build,E320,$(1G_DEFS) E320=1)
$(call post_build,E320,1G)
$(call post_build,E320_1G)
##E320_XG: 10GigE on SFP+ Port.
E320_XG: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
E320_XG: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
$(call vivado_build,E320,$(XG_DEFS) E320=1)
$(call post_build,E320,XG)
$(call post_build,E320_XG)
##E320_AA: Aurora on SFP+ Port.
E320_AA: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
E320_AA: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
$(call vivado_build,E320,$(AA_DEFS) E320=1)
$(call post_build,E320,AA)
$(call post_build,E320_AA)
$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
-mkdir -p $(BUILD_OUTPUT_DIR)
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
##
##Other Make Targets (these should be called directly)
##----------------------------------------------------
##E320_IP: Build IP for E320 only. Use the -j option to build multiple IP blocks simultaneously.
E320_IP:
+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
@rm -rf $(BUILD_BASE_DIR)/build-E3*_* $(BUILD_BASE_DIR)/build-e3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
@rm -rf $(BUILD_OUTPUT_DIR)
@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
@rm -rf $(BUILD_OUTPUT_DIR) $(BUILD_DIR)
help: ##Show this help message.
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'