fpga: Align build process for all targets
- All RFNoC capable targets now require rfnoc_image_builder to be built - `make help` is updated for all targets to provide more useful and up-to-date information - The FPGA manual is also updated - All checked-in build artifacts are now removed from git - axi_ram_fifo.yml is updated to provide include path information (required for building N3xx BIST images, which use this) Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
parent
ba5e431c5c
commit
6ef3795e42
+52
-24
@@ -4,10 +4,18 @@
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP E3XX FPGA Help
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##USRP E32X FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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## rfnoc_image_builder -y <image core file> -t <target>
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##
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## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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@@ -40,21 +48,19 @@ ifndef TARGET
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endif
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TOP ?= e320
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DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
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vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
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vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Device, $2=Option)
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# post_build($1=Target)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/e320.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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cp $(BUILD_DIR)/e320.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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@@ -62,42 +68,64 @@ endif
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##
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##Supported Targets
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##-----------------
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##
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml> -t <target>
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##
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##The default image core file is called e320_rfnoc_image_core.yml.
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##Of course, a custom YAML file may be used.
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##
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##Example:
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## $ rfnoc_image_builder -y e320_rfnoc_image_core.yml --target E320_XG
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##will build the E320_XG target (10-Gigabit Ethernet on the SFP+ port).
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##
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##The following targets are supported:
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all: E320_1G E320_XG ##(Default target)
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##E320_IP: Build IP for E320 only.
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E320_IP:
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+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##E320_1G: 1GigE on SFP+ Port.
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E320_1G: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
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E320_1G: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
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$(call vivado_build,E320,$(1G_DEFS) E320=1)
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$(call post_build,E320,1G)
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$(call post_build,E320_1G)
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##E320_XG: 10GigE on SFP+ Port.
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E320_XG: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
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E320_XG: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
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$(call vivado_build,E320,$(XG_DEFS) E320=1)
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$(call post_build,E320,XG)
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$(call post_build,E320_XG)
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##E320_AA: Aurora on SFP+ Port.
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E320_AA: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
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E320_AA: check-variables E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
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$(call vivado_build,E320,$(AA_DEFS) E320=1)
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$(call post_build,E320,AA)
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$(call post_build,E320_AA)
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$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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##
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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##E320_IP: Build IP for E320 only. Use the -j option to build multiple IP blocks simultaneously.
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E320_IP:
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+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
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@rm -rf $(BUILD_BASE_DIR)/build-E3*_* $(BUILD_BASE_DIR)/build-e3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
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@rm -rf $(BUILD_OUTPUT_DIR)
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@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR) $(BUILD_DIR)
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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+11
-16
@@ -5,7 +5,7 @@
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE = <Input arg>
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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@@ -36,21 +36,15 @@ include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
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# DUC, and of course the radio. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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@@ -117,23 +111,24 @@ $(CAP_GEN_GENERIC_SRCS) \
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$(RFNOC_SRCS) \
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$(RFNOC_OOT_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
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$(RFNOC_BLOCK_RADIO_SRCS) \
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$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
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$(abspath $(MB_XDC))
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$(abspath $(MB_XDC)) \
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$(RFNOC_IMAGE_CORE_SRCS)
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e320.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for e320)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: e320_rfnoc_image_core.yml
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -8,7 +8,10 @@ license: >- # License information used in file heade
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'e320'
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default_target: 'E320_1G'
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default_target: 'E320_1G' # Target. This controls which transports are instantiated.
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image_core_name: 'usrp_e320_fpga_1G' # Name to use for the generated output files.
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# Change image_core_name and default_target in tandem,
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# because we won't generate the correct DTS files otherwise.
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# A list of all stream endpoints in design
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# ----------------------------------------
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