fpga: Align build process for all targets

- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74

top/e31x/Makefile.e31x.inc

@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = <Input arg>
+# TOP_MODULE = <Input arg>
 # NAME = <Input arg>
 # PART_ID = <Input arg>
 # ARCH = <Input arg>
@@ -32,22 +32,15 @@ include $(LIB_DIR)/dsp/Makefile.srcs
 include $(LIB_DIR)/io_cap_gen/Makefile.srcs
 include $(LIB_DIR)/rfnoc/Makefile.srcs
 
-# For the sake of convenience, we include the Makefile.srcs for the DDC, DUC,
-# radio, replay and FIFO blocks. Any other block needs to use the
-# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
-include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
-include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
-include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
-include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
-include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
-
 # If out-of-tree modules want to be compiled into this image, then they need to
 # pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
 # Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
 # source files.
 -include $(RFNOC_OOT_MAKEFILE_SRCS)
 
-IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
+ifdef BUILD_DIR
+include $(BUILD_DIR)/Makefile.inc
+endif
 
 ##################################################
 # Sources
@@ -88,7 +81,6 @@ $(FIFO_SRCS) \
 $(AURORA_PHY_SRCS) \
 $(BD_SRCS) \
 $(RADIO_SRCS) \
-$(RFNOC_SRCS) \
 $(TIMING_SRCS) \
 $(VITA_SRCS) \
 $(CAT_CAP_GEN_SRCS) \
@@ -99,25 +91,29 @@ $(LIB_IP_XCI_SRCS) \
 $(LIB_HLS_IP_SRCS) \
 $(EXTRAM_SRCS) \
 $(CAP_GEN_GENERIC_SRCS) \
+$(RFNOC_SRCS) \
 $(RFNOC_OOT_SRCS)\
-$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
-$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
-$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
-$(RFNOC_BLOCK_REPLAY_SRCS) \
+$(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_EXAMPLE_SRCS) \
+$(RFNOC_IMAGE_CORE_SRCS) \
 $(abspath $(MB_XDC))
 
-IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
+# Pass the image core header files required by RFNoC
+# to Vivado as Verilog definitions.
+IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
 
 ##################################################
 # Dependency Targets
 ##################################################
 .SECONDEXPANSION:
 
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs
+	@echo "Build directory:: $(BUILD_DIR)"
+	@echo "Printing MB_XDC:: $(MB_XDC)"
+	@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
 	$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
 
 synth: .prereqs