fpga: Align build process for all targets
- All RFNoC capable targets now require rfnoc_image_builder to be built - `make help` is updated for all targets to provide more useful and up-to-date information - The FPGA manual is also updated - All checked-in build artifacts are now removed from git - axi_ram_fifo.yml is updated to provide include path information (required for building N3xx BIST images, which use this) Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
parent
ba5e431c5c
commit
6ef3795e42
+60
-28
@@ -4,10 +4,18 @@
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP E3XX FPGA Help
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##USRP E31X FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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## rfnoc_image_builder -y <image core file> -t <target> -n <image core name>
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##
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## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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@@ -37,20 +45,18 @@ ifndef TARGET
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endif
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TOP ?= e31x
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DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Device, $2=Option)
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# post_build($1=Device)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
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cp $(BUILD_DIR)/e31x.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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@@ -59,50 +65,76 @@ endif
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##
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##Supported Targets
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##-----------------
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml> -t <target name> -n <image core name>
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##
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##The following table lists all valid combinations:
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##
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##--------------------------|---------------|-------------------------|------------------
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## Default Image core file | Target | Image core name | Description
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##--------------------------|---------------|-------------------------|------------------
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##e310_rfnoc_image_core.yml | E310_SG1 | usrp_e310_sg1_fpga | E310 speedgrade 1
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##e310_rfnoc_image_core.yml | E310_SG1_IDLE | usrp_e310_sg1_idle_fpga | E310 speedgrade 1, idle image
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##e310_rfnoc_image_core.yml | E310_SG3 | usrp_e310_sg3_fpga | E310 speedgrade 3
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##e310_rfnoc_image_core.yml | E310_SG3_IDLE | usrp_e310_sg3_idle_fpga | E310 speedgrade 3, idle image
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##
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##Of course, a custom YAML file may be used.
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##
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all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 ##(Default target)
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##E310_SG1_IP: Build IP for E310_SG1 only.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
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E310_SG1_IDLE E3XX_idle: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
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E310_SG1_IDLE E3XX_idle: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
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$(call post_build,$@,E310_SG1_IDLE)
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$(call post_build,$@)
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##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
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E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
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E310_SG3_IDLE E3XX_idle_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
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$(call post_build,$@,E310_SG3_IDLE)
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$(call post_build,$@)
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##E310_SG1: Build USRP E3XX (Speed Grade 1).
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E310_SG1 E310: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
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E310_SG1 E310: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG1)
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$(call post_build,$@)
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##E310_SG3: Build USRP E3XX (Speed Grade 3).
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E310_SG3 E310_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
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E310_SG3 E310_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG3)
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$(call post_build,$@)
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$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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##
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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##E310_SG1_IP: Build IP for E310_SG1 only. Use the -j option to build multiple IP blocks simultaneously.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only. Use the -j option to build multiple IP blocks simultaneously.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-E3*
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@rm -rf $(BUILD_BASE_DIR)/build-E3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-E3*
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@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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