fpga: Align build process for all targets
- All RFNoC capable targets now require rfnoc_image_builder to be built - `make help` is updated for all targets to provide more useful and up-to-date information - The FPGA manual is also updated - All checked-in build artifacts are now removed from git - axi_ram_fifo.yml is updated to provide include path information (required for building N3xx BIST images, which use this) Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
parent
ba5e431c5c
commit
6ef3795e42
+60
-28
@@ -4,10 +4,18 @@
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP E3XX FPGA Help
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##USRP E31X FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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## rfnoc_image_builder -y <image core file> -t <target> -n <image core name>
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##
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## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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@@ -37,20 +45,18 @@ ifndef TARGET
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endif
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TOP ?= e31x
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DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Device, $2=Option)
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# post_build($1=Device)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
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cp $(BUILD_DIR)/e31x.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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@@ -59,50 +65,76 @@ endif
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##
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##Supported Targets
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##-----------------
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml> -t <target name> -n <image core name>
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##
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##The following table lists all valid combinations:
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##
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##--------------------------|---------------|-------------------------|------------------
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## Default Image core file | Target | Image core name | Description
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##--------------------------|---------------|-------------------------|------------------
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##e310_rfnoc_image_core.yml | E310_SG1 | usrp_e310_sg1_fpga | E310 speedgrade 1
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##e310_rfnoc_image_core.yml | E310_SG1_IDLE | usrp_e310_sg1_idle_fpga | E310 speedgrade 1, idle image
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##e310_rfnoc_image_core.yml | E310_SG3 | usrp_e310_sg3_fpga | E310 speedgrade 3
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##e310_rfnoc_image_core.yml | E310_SG3_IDLE | usrp_e310_sg3_idle_fpga | E310 speedgrade 3, idle image
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##
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##Of course, a custom YAML file may be used.
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##
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all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 ##(Default target)
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##E310_SG1_IP: Build IP for E310_SG1 only.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
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E310_SG1_IDLE E3XX_idle: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
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E310_SG1_IDLE E3XX_idle: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
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$(call post_build,$@,E310_SG1_IDLE)
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$(call post_build,$@)
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##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
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E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
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E310_SG3_IDLE E3XX_idle_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
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$(call post_build,$@,E310_SG3_IDLE)
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$(call post_build,$@)
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##E310_SG1: Build USRP E3XX (Speed Grade 1).
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E310_SG1 E310: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
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E310_SG1 E310: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG1)
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$(call post_build,$@)
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##E310_SG3: Build USRP E3XX (Speed Grade 3).
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E310_SG3 E310_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
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E310_SG3 E310_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG3)
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$(call post_build,$@)
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$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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##
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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##E310_SG1_IP: Build IP for E310_SG1 only. Use the -j option to build multiple IP blocks simultaneously.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only. Use the -j option to build multiple IP blocks simultaneously.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-E3*
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@rm -rf $(BUILD_BASE_DIR)/build-E3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-E3*
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@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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+14
-18
@@ -5,7 +5,7 @@
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE = <Input arg>
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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@@ -32,22 +32,15 @@ include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/io_cap_gen/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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# For the sake of convenience, we include the Makefile.srcs for the DDC, DUC,
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# radio, replay and FIFO blocks. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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@@ -88,7 +81,6 @@ $(FIFO_SRCS) \
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$(AURORA_PHY_SRCS) \
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$(BD_SRCS) \
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$(RADIO_SRCS) \
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$(RFNOC_SRCS) \
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$(TIMING_SRCS) \
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$(VITA_SRCS) \
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$(CAT_CAP_GEN_SRCS) \
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@@ -99,25 +91,29 @@ $(LIB_IP_XCI_SRCS) \
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$(LIB_HLS_IP_SRCS) \
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$(EXTRAM_SRCS) \
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$(CAP_GEN_GENERIC_SRCS) \
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$(RFNOC_SRCS) \
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$(RFNOC_OOT_SRCS)\
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$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_EXAMPLE_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS) \
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$(abspath $(MB_XDC))
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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@@ -1,572 +0,0 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_image_core (for e31x)
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//
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// Description:
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//
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// The RFNoC Image Core contains the Verilog description of the RFNoC design
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// to be loaded onto the FPGA.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: e310_rfnoc_image_core.yml
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//
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`default_nettype none
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module rfnoc_image_core #(
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parameter [31:0] CHDR_W = 64,
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parameter [31:0] PORT_W = 64,
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parameter [31:0] DMA_W = 64,
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parameter MTU = 10,
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter RADIO_NIPC = 1
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) (
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// Clocks
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input wire chdr_aclk,
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input wire ctrl_aclk,
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input wire core_arst,
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input wire radio_clk,
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input wire dram_clk,
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// Basic
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input wire [ 15:0] device_id,
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// IO ports /////////////////////////
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// ctrlport
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [ 19:0] m_ctrlport_req_addr,
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output wire [ 31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [ 63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [ 31:0] m_ctrlport_resp_data,
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// time
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input wire [ 63:0] radio_time,
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// radio
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input wire [ 63:0] radio_rx_data,
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input wire [ 1:0] radio_rx_stb,
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output wire [ 1:0] radio_rx_running,
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output wire [ 63:0] radio_tx_data,
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input wire [ 1:0] radio_tx_stb,
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output wire [ 1:0] radio_tx_running,
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// dram
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input wire axi_rst,
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output wire [ 7:0] m_axi_awid,
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output wire [ 383:0] m_axi_awaddr,
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output wire [ 63:0] m_axi_awlen,
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output wire [ 23:0] m_axi_awsize,
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output wire [ 15:0] m_axi_awburst,
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output wire [ 7:0] m_axi_awlock,
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output wire [ 31:0] m_axi_awcache,
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output wire [ 23:0] m_axi_awprot,
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output wire [ 31:0] m_axi_awqos,
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output wire [ 31:0] m_axi_awregion,
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output wire [ 7:0] m_axi_awuser,
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output wire [ 7:0] m_axi_awvalid,
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input wire [ 7:0] m_axi_awready,
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output wire [4191:0] m_axi_wdata,
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output wire [ 511:0] m_axi_wstrb,
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output wire [ 7:0] m_axi_wlast,
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output wire [ 7:0] m_axi_wuser,
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output wire [ 7:0] m_axi_wvalid,
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input wire [ 7:0] m_axi_wready,
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input wire [ 7:0] m_axi_bid,
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input wire [ 15:0] m_axi_bresp,
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input wire [ 7:0] m_axi_buser,
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input wire [ 7:0] m_axi_bvalid,
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output wire [ 7:0] m_axi_bready,
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output wire [ 7:0] m_axi_arid,
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output wire [ 383:0] m_axi_araddr,
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output wire [ 63:0] m_axi_arlen,
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output wire [ 23:0] m_axi_arsize,
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output wire [ 15:0] m_axi_arburst,
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output wire [ 7:0] m_axi_arlock,
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output wire [ 31:0] m_axi_arcache,
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output wire [ 31:0] m_axi_arprot,
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output wire [ 31:0] m_axi_arqos,
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output wire [ 31:0] m_axi_arregion,
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output wire [ 7:0] m_axi_aruser,
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output wire [ 7:0] m_axi_arvalid,
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input wire [ 7:0] m_axi_arready,
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input wire [ 7:0] m_axi_rid,
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input wire [4191:0] m_axi_rdata,
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input wire [ 15:0] m_axi_rresp,
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input wire [ 7:0] m_axi_rlast,
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input wire [ 7:0] m_axi_ruser,
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input wire [ 7:0] m_axi_rvalid,
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output wire [ 7:0] m_axi_rready,
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// Transport Adapters ///////////////
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// Transport 0 (dma)
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input wire [PORT_W-1:0] s_dma_tdata,
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input wire s_dma_tlast,
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input wire s_dma_tvalid,
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output wire s_dma_tready,
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output wire [PORT_W-1:0] m_dma_tdata,
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output wire m_dma_tlast,
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output wire m_dma_tvalid,
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input wire m_dma_tready
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);
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localparam BLOCK_CHDR_W = 64;
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localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
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localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
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localparam EP0_W = 64;
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localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
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localparam EP1_W = 64;
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localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
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wire rfnoc_chdr_clk, rfnoc_chdr_rst;
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wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CHDR Crossbar
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [PORT_W-1:0] xb_to_ep0_tdata ;
|
||||
wire xb_to_ep0_tlast ;
|
||||
wire xb_to_ep0_tvalid;
|
||||
wire xb_to_ep0_tready;
|
||||
wire [PORT_W-1:0] ep0_to_xb_tdata ;
|
||||
wire ep0_to_xb_tlast ;
|
||||
wire ep0_to_xb_tvalid;
|
||||
wire ep0_to_xb_tready;
|
||||
wire [PORT_W-1:0] xb_to_ep1_tdata ;
|
||||
wire xb_to_ep1_tlast ;
|
||||
wire xb_to_ep1_tvalid;
|
||||
wire xb_to_ep1_tready;
|
||||
wire [PORT_W-1:0] ep1_to_xb_tdata ;
|
||||
wire ep1_to_xb_tlast ;
|
||||
wire ep1_to_xb_tvalid;
|
||||
wire ep1_to_xb_tready;
|
||||
|
||||
chdr_crossbar_nxn #(
|
||||
.PORT_W (PORT_W),
|
||||
.NPORTS (3),
|
||||
.CHDR_WIDTHS ({EP1_W, EP0_W, DMA_W}),
|
||||
.DEFAULT_PORT (0),
|
||||
.ROUTES ({ 3'b111,
|
||||
3'b111,
|
||||
3'b111 }),
|
||||
.BYTE_MTU (BYTE_MTU),
|
||||
.ROUTE_TBL_SIZE (6),
|
||||
.MUX_ALLOC ("ROUND-ROBIN"),
|
||||
.OPTIMIZE ("AREA"),
|
||||
.NPORTS_MGMT (1),
|
||||
.EXT_RTCFG_PORT (0),
|
||||
.PROTOVER (PROTOVER)
|
||||
) chdr_crossbar_nxn_i (
|
||||
.clk (rfnoc_chdr_clk),
|
||||
.reset (rfnoc_chdr_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_tdata ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata }),
|
||||
.s_axis_tlast ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast }),
|
||||
.s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}),
|
||||
.s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}),
|
||||
.m_axis_tdata ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata }),
|
||||
.m_axis_tlast ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast }),
|
||||
.m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}),
|
||||
.m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}),
|
||||
.ext_rtcfg_stb (1'h0),
|
||||
.ext_rtcfg_addr (16'h0),
|
||||
.ext_rtcfg_data (32'h0),
|
||||
.ext_rtcfg_ack ()
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Stream Endpoints
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
||||
// Otherwise, make sure it's at least two MTU-sized packets.
|
||||
localparam REQ_BUFF_SIZE_EP0 = 16384;
|
||||
localparam INGRESS_BUFF_SIZE_EP0 =
|
||||
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
|
||||
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
|
||||
$clog2(REQ_BUFF_SIZE_EP0);
|
||||
|
||||
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
|
||||
wire m_ep0_out0_tlast;
|
||||
wire m_ep0_out0_tvalid;
|
||||
wire m_ep0_out0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
|
||||
wire s_ep0_in0_tlast;
|
||||
wire s_ep0_in0_tvalid;
|
||||
wire s_ep0_in0_tready;
|
||||
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
|
||||
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
|
||||
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
|
||||
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
|
||||
|
||||
chdr_stream_endpoint #(
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.PROTOVER (PROTOVER),
|
||||
.CHDR_W (EP0_W),
|
||||
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
||||
.AXIS_CTRL_EN (1),
|
||||
.AXIS_DATA_EN (1),
|
||||
.NUM_DATA_I (1),
|
||||
.NUM_DATA_O (1),
|
||||
.INST_NUM (0),
|
||||
.CTRL_XBAR_PORT (1),
|
||||
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
|
||||
.MTU (EP0_MTU),
|
||||
.REPORT_STRM_ERRS (1)
|
||||
) ep0_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_chdr_tdata (xb_to_ep0_tdata),
|
||||
.s_axis_chdr_tlast (xb_to_ep0_tlast),
|
||||
.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
|
||||
.s_axis_chdr_tready (xb_to_ep0_tready),
|
||||
.m_axis_chdr_tdata (ep0_to_xb_tdata),
|
||||
.m_axis_chdr_tlast (ep0_to_xb_tlast),
|
||||
.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
|
||||
.m_axis_chdr_tready (ep0_to_xb_tready),
|
||||
.s_axis_data_tdata ({s_ep0_in0_tdata}),
|
||||
.s_axis_data_tlast ({s_ep0_in0_tlast}),
|
||||
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
|
||||
.s_axis_data_tready ({s_ep0_in0_tready}),
|
||||
.m_axis_data_tdata ({m_ep0_out0_tdata}),
|
||||
.m_axis_data_tlast ({m_ep0_out0_tlast}),
|
||||
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
|
||||
.m_axis_data_tready ({m_ep0_out0_tready}),
|
||||
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
|
||||
.strm_seq_err_stb (),
|
||||
.strm_data_err_stb (),
|
||||
.strm_route_err_stb (),
|
||||
.signal_data_err (1'b0)
|
||||
);
|
||||
|
||||
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
||||
// Otherwise, make sure it's at least two MTU-sized packets.
|
||||
localparam REQ_BUFF_SIZE_EP1 = 16384;
|
||||
localparam INGRESS_BUFF_SIZE_EP1 =
|
||||
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
|
||||
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
|
||||
$clog2(REQ_BUFF_SIZE_EP1);
|
||||
|
||||
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
|
||||
wire m_ep1_out0_tlast;
|
||||
wire m_ep1_out0_tvalid;
|
||||
wire m_ep1_out0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
|
||||
wire s_ep1_in0_tlast;
|
||||
wire s_ep1_in0_tvalid;
|
||||
wire s_ep1_in0_tready;
|
||||
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
|
||||
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
|
||||
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
|
||||
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
|
||||
|
||||
chdr_stream_endpoint #(
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.PROTOVER (PROTOVER),
|
||||
.CHDR_W (EP1_W),
|
||||
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
||||
.AXIS_CTRL_EN (0),
|
||||
.AXIS_DATA_EN (1),
|
||||
.NUM_DATA_I (1),
|
||||
.NUM_DATA_O (1),
|
||||
.INST_NUM (1),
|
||||
.CTRL_XBAR_PORT (2),
|
||||
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
|
||||
.MTU (EP1_MTU),
|
||||
.REPORT_STRM_ERRS (1)
|
||||
) ep1_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.device_id (device_id),
|
||||
.s_axis_chdr_tdata (xb_to_ep1_tdata),
|
||||
.s_axis_chdr_tlast (xb_to_ep1_tlast),
|
||||
.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
|
||||
.s_axis_chdr_tready (xb_to_ep1_tready),
|
||||
.m_axis_chdr_tdata (ep1_to_xb_tdata),
|
||||
.m_axis_chdr_tlast (ep1_to_xb_tlast),
|
||||
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
|
||||
.m_axis_chdr_tready (ep1_to_xb_tready),
|
||||
.s_axis_data_tdata ({s_ep1_in0_tdata}),
|
||||
.s_axis_data_tlast ({s_ep1_in0_tlast}),
|
||||
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
|
||||
.s_axis_data_tready ({s_ep1_in0_tready}),
|
||||
.m_axis_data_tdata ({m_ep1_out0_tdata}),
|
||||
.m_axis_data_tlast ({m_ep1_out0_tlast}),
|
||||
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
|
||||
.m_axis_data_tready ({m_ep1_out0_tready}),
|
||||
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
|
||||
.strm_seq_err_stb (),
|
||||
.strm_data_err_stb (),
|
||||
.strm_route_err_stb (),
|
||||
.signal_data_err (1'b0)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Control Crossbar
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
|
||||
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
|
||||
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
|
||||
wire m_core_ctrl_tready, s_core_ctrl_tready;
|
||||
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
|
||||
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
|
||||
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
|
||||
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
|
||||
|
||||
axis_ctrl_crossbar_nxn #(
|
||||
.WIDTH (32),
|
||||
.NPORTS (3),
|
||||
.TOPOLOGY ("TORUS"),
|
||||
.INGRESS_BUFF_SIZE(5),
|
||||
.ROUTER_BUFF_SIZE (5),
|
||||
.ROUTING_ALLOC ("WORMHOLE"),
|
||||
.SWITCH_ALLOC ("PRIO")
|
||||
) ctrl_xb_i (
|
||||
.clk (rfnoc_ctrl_clk),
|
||||
.reset (rfnoc_ctrl_rst),
|
||||
.s_axis_tdata ({m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
||||
.s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
||||
.s_axis_tlast ({m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
||||
.s_axis_tready ({m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
||||
.m_axis_tdata ({s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
||||
.m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
||||
.m_axis_tlast ({s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
||||
.m_axis_tready ({s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
||||
.deadlock_detected()
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// RFNoC Core Kernel
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
|
||||
|
||||
rfnoc_core_kernel #(
|
||||
.PROTOVER (PROTOVER),
|
||||
.DEVICE_TYPE (16'hE310),
|
||||
.DEVICE_FAMILY ("7SERIES"),
|
||||
.SAFE_START_CLKS (0),
|
||||
.NUM_BLOCKS (1),
|
||||
.NUM_STREAM_ENDPOINTS(2),
|
||||
.NUM_ENDPOINTS_CTRL (1),
|
||||
.NUM_TRANSPORTS (1),
|
||||
.NUM_EDGES (4),
|
||||
.CHDR_XBAR_PRESENT (1),
|
||||
.EDGE_TBL ({
|
||||
{10'd03, 6'd01, 10'd02, 6'd00},
|
||||
{10'd02, 6'd00, 10'd03, 6'd01},
|
||||
{10'd03, 6'd00, 10'd01, 6'd00},
|
||||
{10'd01, 6'd00, 10'd03, 6'd00}
|
||||
})
|
||||
) core_kernel_i (
|
||||
.chdr_aclk (chdr_aclk),
|
||||
.chdr_aclk_locked (1'b1),
|
||||
.ctrl_aclk (ctrl_aclk),
|
||||
.ctrl_aclk_locked (1'b1),
|
||||
.core_arst (core_arst),
|
||||
.core_chdr_clk (rfnoc_chdr_clk),
|
||||
.core_chdr_rst (rfnoc_chdr_rst),
|
||||
.core_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.core_ctrl_rst (rfnoc_ctrl_rst),
|
||||
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
|
||||
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
|
||||
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
|
||||
.s_axis_ctrl_tready (s_core_ctrl_tready),
|
||||
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
|
||||
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
|
||||
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
|
||||
.m_axis_ctrl_tready (m_core_ctrl_tready),
|
||||
.device_id (device_id),
|
||||
.rfnoc_core_config (rfnoc_core_config),
|
||||
.rfnoc_core_status (rfnoc_core_status)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Blocks
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
//-----------------------------------
|
||||
// radio0
|
||||
//-----------------------------------
|
||||
|
||||
wire radio0_radio_clk;
|
||||
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
|
||||
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
|
||||
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
|
||||
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
|
||||
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
|
||||
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
|
||||
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
|
||||
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
|
||||
|
||||
// ctrlport
|
||||
wire radio0_m_ctrlport_req_wr;
|
||||
wire radio0_m_ctrlport_req_rd;
|
||||
wire [ 19:0] radio0_m_ctrlport_req_addr;
|
||||
wire [ 31:0] radio0_m_ctrlport_req_data;
|
||||
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
|
||||
wire radio0_m_ctrlport_req_has_time;
|
||||
wire [ 63:0] radio0_m_ctrlport_req_time;
|
||||
wire radio0_m_ctrlport_resp_ack;
|
||||
wire [ 1:0] radio0_m_ctrlport_resp_status;
|
||||
wire [ 31:0] radio0_m_ctrlport_resp_data;
|
||||
// time
|
||||
wire [ 63:0] radio0_radio_time;
|
||||
// radio
|
||||
wire [32*RADIO_NIPC*2-1:0] radio0_radio_rx_data;
|
||||
wire [ 1:0] radio0_radio_rx_stb;
|
||||
wire [ 1:0] radio0_radio_rx_running;
|
||||
wire [32*RADIO_NIPC*2-1:0] radio0_radio_tx_data;
|
||||
wire [ 1:0] radio0_radio_tx_stb;
|
||||
wire [ 1:0] radio0_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (2),
|
||||
.CHDR_W (BLOCK_CHDR_W),
|
||||
.NUM_PORTS (2),
|
||||
.NIPC (RADIO_NIPC),
|
||||
.ITEM_W (32),
|
||||
.MTU (BLOCK_MTU)
|
||||
) b_radio0_0 (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.radio_clk (radio0_radio_clk),
|
||||
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
|
||||
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
|
||||
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
|
||||
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
|
||||
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
|
||||
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
|
||||
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
|
||||
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
|
||||
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
|
||||
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
|
||||
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
|
||||
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
|
||||
.radio_time (radio0_radio_time),
|
||||
.radio_rx_data (radio0_radio_rx_data),
|
||||
.radio_rx_stb (radio0_radio_rx_stb),
|
||||
.radio_rx_running (radio0_radio_rx_running),
|
||||
.radio_tx_data (radio0_radio_tx_data),
|
||||
.radio_tx_stb (radio0_radio_tx_stb),
|
||||
.radio_tx_running (radio0_radio_tx_running),
|
||||
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
|
||||
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
|
||||
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
|
||||
.s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
|
||||
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
|
||||
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
|
||||
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
|
||||
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
|
||||
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
|
||||
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
|
||||
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
|
||||
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
|
||||
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
|
||||
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
|
||||
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
|
||||
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Static Router
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
|
||||
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
|
||||
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
|
||||
assign m_ep0_out0_tready = s_radio0_in_0_tready;
|
||||
|
||||
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
|
||||
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
|
||||
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
|
||||
assign m_radio0_out_0_tready = s_ep0_in0_tready;
|
||||
|
||||
assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
|
||||
assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
|
||||
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
|
||||
assign m_ep1_out0_tready = s_radio0_in_1_tready;
|
||||
|
||||
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
|
||||
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
|
||||
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
|
||||
assign m_radio0_out_1_tready = s_ep1_in0_tready;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Unused Ports
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Clock Domains and Resets
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign radio0_radio_clk = radio_clk;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// IO Port Connection
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Master/Slave Connections:
|
||||
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
|
||||
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
|
||||
assign m_ctrlport_req_addr = radio0_m_ctrlport_req_addr;
|
||||
assign m_ctrlport_req_data = radio0_m_ctrlport_req_data;
|
||||
assign m_ctrlport_req_byte_en = radio0_m_ctrlport_req_byte_en;
|
||||
assign m_ctrlport_req_has_time = radio0_m_ctrlport_req_has_time;
|
||||
assign m_ctrlport_req_time = radio0_m_ctrlport_req_time;
|
||||
assign radio0_m_ctrlport_resp_ack = m_ctrlport_resp_ack;
|
||||
assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
|
||||
assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
|
||||
|
||||
assign radio0_radio_rx_data = radio_rx_data;
|
||||
assign radio0_radio_rx_stb = radio_rx_stb;
|
||||
assign radio_rx_running = radio0_radio_rx_running;
|
||||
assign radio_tx_data = radio0_radio_tx_data;
|
||||
assign radio0_radio_tx_stb = radio_tx_stb;
|
||||
assign radio_tx_running = radio0_radio_tx_running;
|
||||
|
||||
// Broadcaster/Listener Connections:
|
||||
assign radio0_radio_time = radio_time;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for e31x)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: e310_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -8,8 +8,10 @@ license: >- # License information used in file heade
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'e310' # USRP type
|
||||
image_core_name: 'e310' # Name to use for the RFNoC Image Core files
|
||||
default_target: 'E310_SG3'
|
||||
image_core_name: 'usrp_e310_sg3_fpga' # Name to use for the generated output files.
|
||||
# Change image_core_name and default_target in tandem,
|
||||
# because we won't generate the correct DTS files otherwise.
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user