miegl/b210-k7-fpga
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fpga: Align build process for all targets

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- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
This commit is contained in:
Martin Braun
2024-06-11 10:20:08 +02:00
committed by Joerg Hofrichter
parent ba5e431c5c
commit 6ef3795e42
37 changed files with 527 additions and 9597 deletions
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tools/make/viv_design_builder.mak
+2
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@@ -20,6 +20,8 @@ SIMULATION = 0
# -------------------------------------------------------------------
BUILD_VIVADO_DESIGN = \
@ \
$(if $(BUILD_DIR),,$(error "BUILD_DIR" is not defined! Use rfnoc_image_builder to create valid commands)) \
$(if $(IMAGE_CORE_NAME),,$(error "IMAGE_CORE_NAME" is not defined! Use rfnoc_image_builder to create valid commands)) \
export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \
export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \
export VIV_TOP_MODULE=$(2); \