fpga: x400: Add netlist make flow

Original-commit: 789fa8f65727afabdeb4eea30a941015c6cd2ad5
2024-06-11 10:20:07 +02:00
parent 69e728dba0
commit 6d89320721
5 changed files with 138 additions and 9 deletions
@@ -187,4 +187,7 @@ rtl: .prereqs
 viv_ip: .prereqs $$(DESIGN_SRCS) ip
 	@echo "IP build for $(NAME) DONE . . ."

-.PHONY: bin synth rtl viv_ip
+secure_core: .prereqs
+	$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_secure_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
+
+.PHONY: bin synth rtl viv_ip secure_synth_netlist