fpga: x400: Add netlist make flow
Original-commit: 789fa8f65727afabdeb4eea30a941015c6cd2ad5
This commit is contained in:
Javier Valenzuela
committed by
Joerg Hofrichter
Joerg Hofrichter
parent
69e728dba0
commit
6d89320721
@@ -0,0 +1,19 @@
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#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
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source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
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# STEP#1: Create project, add sources, refresh IP
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vivado_utils::initialize_project
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# STEP#2: Run synthesis
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vivado_utils::synthesize_design -mode out_of_context
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vivado_utils::generate_post_synth_reports
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# STEP#3: Generate encrypted netlist
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vivado_utils::export_encrypted_netlist
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# Cleanup
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vivado_utils::close_batch_project
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+110
-8
@@ -10,6 +10,9 @@ namespace eval ::vivado_utils {
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namespace export \
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initialize_project \
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synthesize_design \
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export_synth_netlist \
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separate_encrypted \
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export_encrypted_netlist \
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check_design \
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generate_post_synth_reports \
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generate_post_place_reports \
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@@ -27,6 +30,7 @@ namespace eval ::vivado_utils {
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variable g_source_files $::env(VIV_DESIGN_SRCS)
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variable g_vivado_mode $::env(VIV_MODE)
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variable g_project_save $::env(VIV_PROJECT)
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variable g_secure_key $::env(VIV_SECURE_KEY)
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# Optional environment variables
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variable g_verilog_defs ""
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@@ -73,23 +77,29 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
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foreach src_file $g_source_files {
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set src_ext [file extension $src_file ]
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if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
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puts "BUILDER: Adding VHDL : $src_file"
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puts "BUILDER: Adding VHDL: $src_file"
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read_vhdl -library work $src_file
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} elseif [expr [lsearch {.v .vh .sv .svh} $src_ext] >= 0] {
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puts "BUILDER: Adding Verilog : $src_file"
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} elseif [expr [lsearch {.v .vh} $src_ext] >= 0] {
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puts "BUILDER: Adding Verilog: $src_file"
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read_verilog $src_file
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} elseif [expr [lsearch {.vp} $src_ext] >= 0] {
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puts "BUILDER: Adding encrypted Verilog: $src_file"
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read_verilog $src_file
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} elseif [expr [lsearch {.sv .svh} $src_ext] >= 0] {
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puts "BUILDER: Adding SystemVerilog: $src_file"
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read_verilog -sv $src_file
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} elseif [expr [lsearch {.xdc} $src_ext] >= 0] {
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puts "BUILDER: Adding XDC : $src_file"
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puts "BUILDER: Adding XDC: $src_file"
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read_xdc $src_file
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} elseif [expr [lsearch {.sdc} $src_ext] >= 0] {
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puts "BUILDER: Adding SDC : $src_file"
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puts "BUILDER: Adding SDC: $src_file"
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read_xdc $src_file
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} elseif [expr [lsearch {.xci} $src_ext] >= 0] {
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puts "BUILDER: Adding IP : $src_file"
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puts "BUILDER: Adding IP: $src_file"
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read_ip $src_file
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set_property generate_synth_checkpoint true [get_files $src_file]
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} elseif [expr [lsearch {.ngc .edif .edf} $src_ext] >= 0] {
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puts "BUILDER: Adding Netlist : $src_file"
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puts "BUILDER: Adding Netlist: $src_file"
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read_edif $src_file
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} elseif [expr [lsearch {.bd} $src_ext] >= 0] {
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puts "BUILDER: Adding Block Design to list (added after IP regeneration): $src_file"
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@@ -98,7 +108,7 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
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puts "BUILDER: Adding Block Design XML to list (added after IP regeneration): $src_file"
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append bd_files "$src_file "
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} elseif [expr [lsearch {.dat} $src_ext] >= 0] {
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puts "BUILDER: Adding Data File : $src_file"
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puts "BUILDER: Adding Data File: $src_file"
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add_files $src_file
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} else {
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puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
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@@ -148,6 +158,98 @@ proc ::vivado_utils::synthesize_design {args} {
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eval $synth_cmd
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}
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# ---------------------------------------------------
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# Generate netlist from Synthesis
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# ---------------------------------------------------
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proc ::vivado_utils::export_synth_netlist { {suffix ""} } {
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variable g_output_dir
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variable g_top_module
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puts "BUILDER: Writing EDIF netlist for $g_top_module"
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set filename ${g_output_dir}/${g_top_module}
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if { [expr [string length $suffix] > 0] } {
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set filename ${filename}_${suffix}
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}
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write_edif -security_mode all -force ${filename}.edf
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write_verilog -mode synth_stub -force -file ${filename}_stub.v
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}
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# ---------------------------------------------------
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# Extract encrypted sections from a file
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# ---------------------------------------------------
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proc ::vivado_utils::separate_encrypted {input_filename unencrypted_filename encrypted_filename} {
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set protected_sections ""
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set unprotected_sections ""
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set inside_protected_section 0
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# Read each line from the input file and separate it into protected and
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# unprotected sections.
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set input_file [open $input_filename r]
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while {[gets $input_file line] >= 0} {
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# Check if we are inside a protected section
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if {[string match "*`pragma protect begin_protected*" $line]} {
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set inside_protected_section 1
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}
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# Append the line to the appropriate section
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if {$inside_protected_section} {
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append protected_sections "$line\n"
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} else {
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append unprotected_sections "$line\n"
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}
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if {[string match "*`pragma protect end_protected*" $line]} {
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set inside_protected_section 0
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}
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}
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close $input_file
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# Write the extracted portions to files
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set encrypted_file [open $encrypted_filename w]
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puts $encrypted_file $protected_sections
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close $encrypted_file
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set unencrypted_file [open $unencrypted_filename w]
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puts $unencrypted_file $unprotected_sections
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close $unencrypted_file
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}
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# ---------------------------------------------------------
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# Generate an IEEE-1735 encrypted netlist in a single file
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# ---------------------------------------------------------
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proc ::vivado_utils::export_encrypted_netlist { {suffix ""} } {
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variable g_output_dir
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variable g_top_module
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variable g_secure_key
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puts "BUILDER: Writing encrypted netlist for $g_top_module"
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set filename ${g_output_dir}/${g_top_module}
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if { [expr [string length $suffix] > 0] } {
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set filename ${filename}_${suffix}
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}
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# Uniquify the module names to prevent collisions when the netlist is used
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rename_ref -prefix_all $g_top_module
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# Write the design to a Verilog netlist
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write_verilog -force ${filename}_netlist.v
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puts "BUILDER: Unencrypted netlist written to ${filename}_netlist.v"
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write_xdc -force ${filename}.xdc
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puts "BUILDER: Constraints written to ${filename}.xdc"
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if {$g_secure_key ne ""} {
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# The netlist may have parts that are already encrypted and Vivado doesn't
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# let us encrypt stuff that's already encrypted, so we need to split it up.
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vivado_utils::separate_encrypted ${filename}_netlist.v ${filename}_netlist_user.v ${filename}_netlist_other.vp
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# Encrypt the parts that aren't already encrypted
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encrypt -key ${g_secure_key} -lang verilog -ext .vp ${filename}_netlist_user.v
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# Merge the two encrypted files
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set combined_netlists [read [open ${filename}_netlist_user.vp r]][read [open ${filename}_netlist_other.vp r]]
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set combined_netlists_file [open ${filename}.vp w]
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puts $combined_netlists_file $combined_netlists
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close $combined_netlists_file
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puts "BUILDER: Encrypted netlist written to ${filename}.vp"
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}
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}
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# ---------------------------------------------------
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# Check design (Shortcut for Vivado's synth_design -rtl)
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# ---------------------------------------------------
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