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fpga: x400: Add netlist make flow

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Original-commit: 789fa8f65727afabdeb4eea30a941015c6cd2ad5
This commit is contained in:
Javier Valenzuela
2024-06-11 10:20:07 +02:00
committed by Joerg Hofrichter
parent 69e728dba0
commit 6d89320721
5 changed files with 138 additions and 9 deletions
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tools/make/viv_design_builder.mak
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@@ -29,6 +29,7 @@ BUILD_VIVADO_DESIGN = \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
export VIV_INCR_BUILD=$(INCR_BUILD); \
export VIV_SECURE_KEY=$(call RESOLVE_PATH,$(abspath $(SECURE_KEY))); \
cd $(BUILD_DIR); \
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(MAKEFILE_DIR)/dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou