Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,66 @@
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#
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# Copyright 2015 Ettus Research LLC
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../..)
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = kintex7
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PART_ID = xc7k410t/ffg900/-2
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/io_port2/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(IOPORT2_SRCS) \
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../../x300_pcie_int.v \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = ../../ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(IP_FIFO_4K_2CLK_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = x300_pcie_int_tb
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SIM_SRCS = \
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$(abspath x300_pcie_int_tb.sv)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,596 @@
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//
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// Copyright 2013 Ettus Research LLC
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//
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`timescale 1ns/1ps
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`define NS_PER_TICK 1
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`define NUM_TEST_CASES 23
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`define SIM_TIMEOUT_US 1000 // 1ms
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`include "sim_clks_rsts.vh"
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`include "sim_exec_report.vh"
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module x300_pcie_int_tb();
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`DEFINE_CLK(clk, 8.000, 50)
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`DEFINE_RESET(reset, 0, 10)
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`TEST_BENCH_INIT("x300_pcie_int_tb",`NUM_TEST_CASES,`NS_PER_TICK)
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reg temp_pass = 0;
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reg pkt_swap = 0;
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reg [15:0] it = 0;
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reg [15:0] tx_ch, rx_ch = 0;
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reg [31:0] dma_sample_cnt = 0;
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reg [31:0] dma_packet_cnt = 0;
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reg [31:0] dma_out_sample_cnt[0:5];
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reg [63:0] dma_out_last_sample[0:5];
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reg pcie_usr_reg_wr, pcie_usr_reg_rd;
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reg [1:0] pcie_usr_reg_len;
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reg [19:0] pcie_usr_reg_addr;
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reg [31:0] pcie_usr_reg_data_in, pcie_usr_data;
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wire pcie_usr_reg_rc, pcie_usr_reg_rdy;
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wire [31:0] pcie_usr_reg_data_out;
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wire chinch_reg_wr, chinch_reg_rd;
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wire [1:0] chinch_reg_len;
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wire [19:0] chinch_reg_addr;
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wire [31:0] chinch_reg_data_out;
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reg chinch_reg_rc, chinch_reg_rdy;
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reg [31:0] chinch_reg_data_in;
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reg [2:0] i_chan, o_chan;
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reg [383:0] i_tdata_par;
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reg [5:0] i_tvalid_par = 6'b000000, o_tready_par = 6'b111111;
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wire [383:0] o_tdata_par;
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wire [5:0] o_tvalid_par, i_tready_par;
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reg i_tvalid, i_tready, o_tvalid, o_tready;
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reg [63:0] i_tdata, o_tdata;
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localparam READ = 2'b01;
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localparam WRITE = 2'b10;
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task usr_regport_request;
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input [1:0] operation;
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input [19:0] address;
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input [31:0] data;
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begin
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pcie_usr_reg_data_in <= data;
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pcie_usr_reg_addr <= address;
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pcie_usr_reg_wr <= operation[1];
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pcie_usr_reg_rd <= operation[0];
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pcie_usr_reg_len <= 2'b10;
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@(posedge clk);
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while (~pcie_usr_reg_rdy) @(posedge clk);
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pcie_usr_reg_wr <= 1'b0;
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pcie_usr_reg_rd <= 1'b0;
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@(posedge clk);
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end
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endtask // usr_regport_request
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task usr_regport_response;
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begin
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@(posedge clk);
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while (~pcie_usr_reg_rc) @(posedge clk);
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pcie_usr_data <= pcie_usr_reg_data_out;
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@(posedge clk);
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end
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endtask // usr_regport_response
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task chinch_regport_request;
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input [1:0] operation;
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input [19:0] address;
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input [31:0] data;
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begin
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@(posedge clk);
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while (~(chinch_reg_rdy &&
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chinch_reg_addr == address &&
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{chinch_reg_wr,chinch_reg_rd} == operation &&
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chinch_reg_len == 2'b10 &&
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(operation == WRITE || chinch_reg_data_out == data)
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)) @(posedge clk);
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@(posedge clk);
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end
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endtask // chinch_regport_request
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task chinch_regport_response;
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input [31:0] data;
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begin
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@(posedge clk);
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chinch_reg_data_in <= data;
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chinch_reg_rc <= 1'b1;
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@(posedge clk);
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chinch_reg_rc <= 1'b0;
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end
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endtask // chinch_regport_response
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task send_packet;
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input [63:0] sid;
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input [31:0] len;
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input [31:0] quant;
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begin
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if(quant < 2) begin
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i_tdata <= { sid[63:32],len[15:0], sid[15:0] };
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i_tvalid <= 1;
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@(posedge clk);
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i_tvalid <= 0;
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@(posedge clk);
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end else begin
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i_tdata <= { sid[63:32],len[15:0], sid[15:0] };
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i_tvalid <= 1;
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@(posedge clk);
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i_tdata <= 64'h0000_0001_0000_0000;
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repeat(quant - 2) begin
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i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
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@(posedge clk);
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end
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i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
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@(posedge clk);
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i_tvalid <= 1'b0;
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@(posedge clk);
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end // else: !if(len < 3)
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end
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endtask // send_packet
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task reset_dma_counts;
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begin
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dma_sample_cnt <= 32'd0;
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dma_packet_cnt <= 32'd0;
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dma_out_sample_cnt[0] <= 32'd0;
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dma_out_sample_cnt[1] <= 32'd0;
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dma_out_sample_cnt[2] <= 32'd0;
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dma_out_sample_cnt[3] <= 32'd0;
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dma_out_sample_cnt[4] <= 32'd0;
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dma_out_sample_cnt[5] <= 32'd0;
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dma_out_last_sample[0] <= 64'd0;
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dma_out_last_sample[1] <= 64'd0;
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dma_out_last_sample[2] <= 64'd0;
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dma_out_last_sample[3] <= 64'd0;
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dma_out_last_sample[4] <= 64'd0;
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dma_out_last_sample[5] <= 64'd0;
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@(posedge clk);
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end
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endtask // reset_dma_counts
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task select_channels;
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input [2:0] tx_ch;
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input [2:0] rx_ch;
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begin
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i_chan <= tx_ch;
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o_chan <= rx_ch;
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@(posedge clk);
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end
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endtask // select_channels
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task wait_for_pkt_loopback;
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begin
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while (i_tvalid & i_tready) @(posedge clk); //Wait for outbound pkt to pad and send
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while (~o_tvalid) @(posedge clk); //Wait for inbound pkt to arrive
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while (o_tvalid & o_tready) @(posedge clk); //Wait for inbound pkt to finish
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end
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endtask // wait_for_pkt_loopback
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wire [63:0] dma_loop_tdata ;
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wire [ 2:0] dma_loop_tuser ;
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wire dma_loop_tvalid, dma_loop_tlast, dma_loop_tready;
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wire [63:0] iop2_msg_tdata ;
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wire iop2_msg_tvalid, iop2_msg_tlast, iop2_msg_tready;
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initial begin : tb_main
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while (reset) @(posedge clk);
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chinch_reg_rdy <= 1'b1;
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chinch_reg_rc <= 1'b0;
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`TEST_CASE_START("Verify signature register");
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usr_regport_request(READ, 20'h40000, 32'h0);
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usr_regport_response();
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`TEST_CASE_DONE((pcie_usr_data == "X300"))
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`TEST_CASE_START("Verify counter frequency register");
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usr_regport_request(READ, 20'h4000C, 32'h0);
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usr_regport_response();
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`TEST_CASE_DONE((pcie_usr_data == 166666667));
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`TEST_CASE_START("Verify scratch registers");
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usr_regport_request(WRITE, 20'h40010, 32'hDEAD);
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usr_regport_request(WRITE, 20'h40014, 32'hBEEF);
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usr_regport_request(READ, 20'h40014, 32'h0);
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usr_regport_response();
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temp_pass <= (pcie_usr_data == 32'hBEEF);
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usr_regport_request(READ, 20'h40010, 32'h0);
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usr_regport_response();
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`TEST_CASE_DONE((pcie_usr_data == 32'hDEAD) & temp_pass);
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`TEST_CASE_START("Client register port write 1");
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usr_regport_request(WRITE, 20'h60000, 32'h12345678);
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chinch_regport_request(WRITE, 20'h60000, 32'h12345678);
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usr_regport_request(WRITE, 20'h7FFFC, 32'h1357);
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chinch_regport_request(WRITE, 20'h7FFFC, 32'h1357);
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usr_regport_request(WRITE, 20'h70000, 32'h2468);
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chinch_regport_request(WRITE, 20'h70000, 32'h2468);
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Client register port read 1");
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usr_regport_request(READ, 20'h60000, 32'h0);
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chinch_regport_request(READ, 20'h60000, 32'h0);
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chinch_regport_response(32'hACE0BA51);
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usr_regport_response();
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`ASSERT_ERROR((pcie_usr_data == 32'hACE0BA51),"");
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usr_regport_request(READ, 20'h7FFFC, 32'h0);
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chinch_regport_request(READ, 20'h7FFFC, 32'h0);
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chinch_regport_response(32'hACE0BA52);
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usr_regport_response();
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`ASSERT_ERROR((pcie_usr_data == 32'hACE0BA52),"");
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usr_regport_request(READ, 20'h70000, 32'h0);
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chinch_regport_request(READ, 20'h70000, 32'h0);
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chinch_regport_response(32'hACE0BA53);
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usr_regport_response();
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`TEST_CASE_DONE((pcie_usr_data == 32'hACE0BA53));
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`TEST_CASE_START("Configure RX DMA routing table");
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usr_regport_request(WRITE, 20'h40500, 32'h0000_0000);
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usr_regport_request(WRITE, 20'h40500, 32'h0001_0001);
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usr_regport_request(WRITE, 20'h40500, 32'h0002_0002);
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usr_regport_request(WRITE, 20'h40500, 32'h0003_0003);
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usr_regport_request(WRITE, 20'h40500, 32'h00D3_0000);
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usr_regport_request(WRITE, 20'h40500, 32'h00D2_0001);
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usr_regport_request(WRITE, 20'h40500, 32'h00D1_0002);
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usr_regport_request(WRITE, 20'h40500, 32'h00D0_0003);
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Frame size register read");
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usr_regport_request(READ, 20'h40204, 32'h0);
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usr_regport_response();
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`ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [TX0].");
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usr_regport_request(READ, 20'h40214, 32'h0);
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usr_regport_response();
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`ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [TX1].");
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usr_regport_request(READ, 20'h40404, 32'h0);
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usr_regport_response();
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`ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [RX0].");
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usr_regport_request(READ, 20'h40414, 32'h0);
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usr_regport_response();
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`ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [RX1].");
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`TEST_CASE_DONE(1);
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o_tready <= 1'b1;
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`TEST_CASE_START("Loopback packet");
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reset_dma_counts();
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usr_regport_request(WRITE, 20'h40200, 32'h0000_0012);
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usr_regport_request(WRITE, 20'h40400, 32'h0000_0012);
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select_channels(0,0);
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send_packet(16'h00D2, 80, 32);
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wait_for_pkt_loopback();
|
||||
`TEST_CASE_DONE((dma_sample_cnt==10 && dma_packet_cnt==1 && dma_out_sample_cnt[0]==32));
|
||||
|
||||
reset_dma_counts();
|
||||
select_channels(1,0);
|
||||
send_packet(16'h00D3, 80, 32);
|
||||
wait_for_pkt_loopback();
|
||||
`TEST_CASE_DONE(dma_sample_cnt==10 && dma_packet_cnt==1 && dma_out_sample_cnt[0]==32);
|
||||
|
||||
`TEST_CASE_START("Frame size register write.");
|
||||
usr_regport_request(WRITE, 20'h40224, 32'd16);
|
||||
usr_regport_request(WRITE, 20'h40234, 32'd16);
|
||||
usr_regport_request(WRITE, 20'h40424, 32'd16);
|
||||
usr_regport_request(WRITE, 20'h40434, 32'd16);
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Frame size register read");
|
||||
usr_regport_request(READ, 20'h40224, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [TX2].");
|
||||
usr_regport_request(READ, 20'h40234, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [TX3].");
|
||||
usr_regport_request(READ, 20'h40424, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [RX2].");
|
||||
usr_regport_request(READ, 20'h40434, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [RX3].");
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Loopback packet");
|
||||
reset_dma_counts();
|
||||
select_channels(2,2);
|
||||
send_packet(16'h0002, 32, 16);
|
||||
wait_for_pkt_loopback();
|
||||
`TEST_CASE_DONE(dma_sample_cnt==4 && dma_packet_cnt==1 && dma_out_sample_cnt[2]==16);
|
||||
|
||||
reset_dma_counts();
|
||||
select_channels(3,3);
|
||||
send_packet(16'h0003, 32, 16);
|
||||
wait_for_pkt_loopback();
|
||||
`TEST_CASE_DONE((dma_sample_cnt==4 && dma_packet_cnt==1 && dma_out_sample_cnt[3]==16));
|
||||
|
||||
`TEST_CASE_START("Loopback multiple packets");
|
||||
reset_dma_counts();
|
||||
select_channels(3,2);
|
||||
send_packet(16'h0002, 128, 16);
|
||||
send_packet(16'h0002, 128, 16);
|
||||
send_packet(16'h0002, 128, 16);
|
||||
send_packet(16'h0002, 128, 16);
|
||||
wait_for_pkt_loopback();
|
||||
repeat(64) @(posedge clk);
|
||||
`TEST_CASE_DONE(dma_sample_cnt==64 && dma_packet_cnt==4 && dma_out_sample_cnt[2]==64 && o_tdata==64'h0000009e00000020);
|
||||
|
||||
`TEST_CASE_START("Loopback multiple packets (RX Swapped)");
|
||||
reset_dma_counts();
|
||||
select_channels(3,2);
|
||||
|
||||
usr_regport_request(WRITE, 20'h40230, 32'h10);
|
||||
usr_regport_request(WRITE, 20'h40420, 32'h00);
|
||||
repeat(16) @(posedge clk);
|
||||
|
||||
send_packet(16'h0002, 128, 16);
|
||||
send_packet(16'h0002, 128, 16);
|
||||
wait_for_pkt_loopback();
|
||||
repeat(64) @(posedge clk);
|
||||
`TEST_CASE_DONE(dma_sample_cnt==32 && dma_packet_cnt==2 && dma_out_sample_cnt[2]==32 && o_tdata==64'h000000200000009e);
|
||||
|
||||
/* @TODO: Need to implement data swapping in TB
|
||||
`TEST_CASE_START();
|
||||
reset_dma_counts();
|
||||
select_channels(3,2);
|
||||
|
||||
usr_regport_request(WRITE, 20'h40230, 32'h00);
|
||||
usr_regport_request(WRITE, 20'h40420, 32'h10);
|
||||
repeat(16) @(posedge clk);
|
||||
|
||||
send_packet(16'h0002, 128, 16);
|
||||
send_packet(16'h0002, 128, 16);
|
||||
wait_for_pkt_loopback();
|
||||
repeat(64) @(posedge clk);
|
||||
`TEST_CASE_DONE(dma_sample_cnt==32 && dma_packet_cnt==2 && dma_out_sample_cnt[2]==32 && o_tdata[7:0]==32,
|
||||
"Loopback multiple packets (TX Swapped).");
|
||||
*/
|
||||
|
||||
`TEST_CASE_START("Good DMA status.");
|
||||
reset_dma_counts();
|
||||
select_channels(3,2);
|
||||
usr_regport_request(READ, 20'h40230, 32'h0);
|
||||
usr_regport_response();
|
||||
temp_pass <= (pcie_usr_data == 32'h0);
|
||||
usr_regport_request(READ, 20'h40420, 32'h0);
|
||||
usr_regport_response();
|
||||
`TEST_CASE_DONE(temp_pass && (pcie_usr_data == 32'h0));
|
||||
|
||||
`TEST_CASE_START("Bad DMA status.");
|
||||
send_packet(16'h0002, 160, 20);
|
||||
repeat(64) @(posedge clk);
|
||||
usr_regport_request(READ, 20'h40230, 32'h0);
|
||||
usr_regport_response();
|
||||
temp_pass <= (pcie_usr_data == 32'h1);
|
||||
usr_regport_request(READ, 20'h40420, 32'h0);
|
||||
usr_regport_response();
|
||||
`TEST_CASE_DONE(temp_pass || (pcie_usr_data == 32'h1));
|
||||
|
||||
`TEST_CASE_START("DMA Status reset.");
|
||||
usr_regport_request(WRITE, 20'h40230, 32'h1);
|
||||
usr_regport_request(READ, 20'h40230, 32'h0);
|
||||
usr_regport_response();
|
||||
temp_pass <= (pcie_usr_data == 32'h0);
|
||||
usr_regport_request(WRITE, 20'h40420, 32'h1);
|
||||
usr_regport_request(READ, 20'h40420, 32'h0);
|
||||
usr_regport_response();
|
||||
`TEST_CASE_DONE(temp_pass && (pcie_usr_data == 32'h0));
|
||||
|
||||
`TEST_CASE_START("Packet count register reset");
|
||||
select_channels(2,1);
|
||||
reset_dma_counts();
|
||||
usr_regport_request(WRITE, 20'h4022C, 32'h0);
|
||||
usr_regport_request(READ, 20'h4022C, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 0), "TX Packet count register reset.");
|
||||
usr_regport_request(WRITE, 20'h4041C, 32'h0);
|
||||
usr_regport_request(READ, 20'h4041C, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 0), "RX Packet count register reset.");
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("TX Packet count register read");
|
||||
send_packet(16'h0001, 80, 16);
|
||||
send_packet(16'h0001, 24, 16);
|
||||
send_packet(16'h0001, 48, 16);
|
||||
repeat(64) @(posedge clk);
|
||||
usr_regport_request(READ, 20'h4022C, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 3), "TX Packet count register read.");
|
||||
usr_regport_request(READ, 20'h4041C, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 3), "RX Packet count register read.");
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("TX Sample count register reset");
|
||||
select_channels(1,2);
|
||||
reset_dma_counts();
|
||||
usr_regport_request(WRITE, 20'h40218, 32'h0);
|
||||
usr_regport_request(READ, 20'h40218, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 0), "TX Sample count register reset.");
|
||||
usr_regport_request(WRITE, 20'h40428, 32'h0);
|
||||
usr_regport_request(READ, 20'h40428, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 0), "RX Sample count register reset.");
|
||||
`TEST_CASE_DONE(1'b1);
|
||||
|
||||
`TEST_CASE_START("TX Sample count register read");
|
||||
send_packet(16'h0002, 28, 16);
|
||||
wait_for_pkt_loopback();
|
||||
usr_regport_request(READ, 20'h40218, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 4), "TX Sample count register read.");
|
||||
usr_regport_request(READ, 20'h40428, 32'h0);
|
||||
usr_regport_response();
|
||||
`ASSERT_ERROR((pcie_usr_data == 4), "RX Sample count register read.");
|
||||
`TEST_CASE_DONE(1'b1);
|
||||
|
||||
`TEST_CASE_START("Setup for NxN DMA test");
|
||||
for (it = 0; it < 16'd6; it = it + 16'd1) begin
|
||||
usr_regport_request(WRITE, 20'h40204 + (it * 16), 32'h4);
|
||||
usr_regport_request(WRITE, 20'h40404 + (it * 16), 32'h4);
|
||||
usr_regport_request(WRITE, 20'h40500, {it, it});
|
||||
end
|
||||
`TEST_CASE_DONE(1'b1);
|
||||
|
||||
`TEST_CASE_START("Setup for NxN DMA test");
|
||||
for (tx_ch = 0; tx_ch < 6; tx_ch = tx_ch + 16'd2) begin
|
||||
for (rx_ch = 1; rx_ch < 6; rx_ch = rx_ch + 16'd1) begin
|
||||
select_channels(tx_ch,rx_ch);
|
||||
reset_dma_counts();
|
||||
@(posedge clk);
|
||||
send_packet(rx_ch, 16, 4);
|
||||
wait_for_pkt_loopback();
|
||||
if (dma_sample_cnt==2 && dma_packet_cnt==1 && dma_out_sample_cnt[rx_ch]==4) begin
|
||||
$display("[TEST%d]: NxN DMA Test [TX=%d, RX=%d]...Passed",tc_run_count,tx_ch[3:0],rx_ch[3:0]);
|
||||
end else begin
|
||||
$display("[TEST%d]: NxN DMA Test [TX=%d, RX=%d]...FAILED!!!",tc_run_count,tx_ch[3:0],rx_ch[3:0]);
|
||||
end
|
||||
@(posedge clk);
|
||||
end
|
||||
end
|
||||
`TEST_CASE_DONE(1'b1);
|
||||
end // initial begin
|
||||
|
||||
|
||||
x300_pcie_int #(
|
||||
.DMA_STREAM_WIDTH (64),
|
||||
.NUM_TX_STREAMS (6 ),
|
||||
.NUM_RX_STREAMS (6 ),
|
||||
.REGPORT_ADDR_WIDTH(20),
|
||||
.REGPORT_DATA_WIDTH(32),
|
||||
.IOP2_MSG_WIDTH (64)
|
||||
) x300_pcie_int (
|
||||
.ioport2_clk (clk ),
|
||||
.bus_clk (clk ),
|
||||
.bus_rst (reset ),
|
||||
|
||||
//DMA TX FIFOs (IoPort2 Clock Domain)
|
||||
.dmatx_tdata_iop2 (i_tdata_par ),
|
||||
.dmatx_tvalid_iop2 (i_tvalid_par ),
|
||||
.dmatx_tready_iop2 (i_tready_par ),
|
||||
|
||||
//DMA TX FIFOs (IoPort2 Clock Domain)
|
||||
.dmarx_tdata_iop2 (o_tdata_par ),
|
||||
.dmarx_tvalid_iop2 (o_tvalid_par ),
|
||||
.dmarx_tready_iop2 (o_tready_par ),
|
||||
|
||||
//PCIe User Regport
|
||||
.pcie_usr_reg_wr (pcie_usr_reg_wr ),
|
||||
.pcie_usr_reg_rd (pcie_usr_reg_rd ),
|
||||
.pcie_usr_reg_addr (pcie_usr_reg_addr ),
|
||||
.pcie_usr_reg_data_in (pcie_usr_reg_data_in ),
|
||||
.pcie_usr_reg_len (pcie_usr_reg_len ),
|
||||
.pcie_usr_reg_data_out(pcie_usr_reg_data_out),
|
||||
.pcie_usr_reg_rc (pcie_usr_reg_rc ),
|
||||
.pcie_usr_reg_rdy (pcie_usr_reg_rdy ),
|
||||
|
||||
//Chinch Regport
|
||||
.chinch_reg_wr (chinch_reg_wr ),
|
||||
.chinch_reg_rd (chinch_reg_rd ),
|
||||
.chinch_reg_addr (chinch_reg_addr ),
|
||||
.chinch_reg_data_out (chinch_reg_data_out ),
|
||||
.chinch_reg_len (chinch_reg_len ),
|
||||
.chinch_reg_data_in (chinch_reg_data_in ),
|
||||
.chinch_reg_rc (chinch_reg_rc ),
|
||||
.chinch_reg_rdy (chinch_reg_rdy ),
|
||||
|
||||
//DMA TX FIFO (Bus Clock Domain)
|
||||
.dmatx_tdata (dma_loop_tdata ),
|
||||
.dmatx_tuser (dma_loop_tuser ),
|
||||
.dmatx_tlast (dma_loop_tlast ),
|
||||
.dmatx_tvalid (dma_loop_tvalid ),
|
||||
.dmatx_tready (dma_loop_tready ),
|
||||
|
||||
//DMA RX FIFO (Bus Clock Domain)
|
||||
.dmarx_tdata (dma_loop_tdata ),
|
||||
.dmarx_tuser (dma_loop_tuser ),
|
||||
.dmarx_tlast (dma_loop_tlast ),
|
||||
.dmarx_tvalid (dma_loop_tvalid ),
|
||||
.dmarx_tready (dma_loop_tready ),
|
||||
|
||||
//Message FIFO Out (Bus Clock Domain)
|
||||
.rego_tdata (iop2_msg_tdata ),
|
||||
.rego_tvalid (iop2_msg_tvalid ),
|
||||
.rego_tlast (iop2_msg_tlast ),
|
||||
.rego_tready (iop2_msg_tready ),
|
||||
|
||||
//Message FIFO In (Bus Clock Domain)
|
||||
.regi_tdata (iop2_msg_tdata ),
|
||||
.regi_tvalid (iop2_msg_tvalid ),
|
||||
.regi_tlast (iop2_msg_tlast ),
|
||||
.regi_tready (iop2_msg_tready ),
|
||||
|
||||
.debug ( )
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (dma_loop_tvalid & dma_loop_tready) begin
|
||||
dma_sample_cnt <= dma_sample_cnt + 32'd1;
|
||||
if (dma_loop_tlast) dma_packet_cnt <= dma_packet_cnt + 32'd1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
case (i_chan)
|
||||
3'd5:
|
||||
{i_tdata_par[383:320], i_tvalid_par[5], i_tready} <= {i_tdata, i_tvalid, i_tready_par[5]};
|
||||
3'd4:
|
||||
{i_tdata_par[319:256], i_tvalid_par[4], i_tready} <= {i_tdata, i_tvalid, i_tready_par[4]};
|
||||
3'd3:
|
||||
{i_tdata_par[255:192], i_tvalid_par[3], i_tready} <= {i_tdata, i_tvalid, i_tready_par[3]};
|
||||
3'd2:
|
||||
{i_tdata_par[191:128], i_tvalid_par[2], i_tready} <= {i_tdata, i_tvalid, i_tready_par[2]};
|
||||
3'd1:
|
||||
{i_tdata_par[127:64], i_tvalid_par[1], i_tready} <= {i_tdata, i_tvalid, i_tready_par[1]};
|
||||
default:
|
||||
{i_tdata_par[63:0], i_tvalid_par[0], i_tready} <= {i_tdata, i_tvalid, i_tready_par[0]};
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
case (o_chan)
|
||||
3'd5:
|
||||
{o_tdata, o_tvalid, o_tready_par[5]} <= {o_tdata_par[383:320], o_tvalid_par[5], o_tready};
|
||||
3'd4:
|
||||
{o_tdata, o_tvalid, o_tready_par[4]} <= {o_tdata_par[319:256], o_tvalid_par[4], o_tready};
|
||||
3'd3:
|
||||
{o_tdata, o_tvalid, o_tready_par[3]} <= {o_tdata_par[255:192], o_tvalid_par[3], o_tready};
|
||||
3'd2:
|
||||
{o_tdata, o_tvalid, o_tready_par[2]} <= {o_tdata_par[191:128], o_tvalid_par[2], o_tready};
|
||||
3'd1:
|
||||
{o_tdata, o_tvalid, o_tready_par[1]} <= {o_tdata_par[127:64], o_tvalid_par[1], o_tready};
|
||||
default:
|
||||
{o_tdata, o_tvalid, o_tready_par[0]} <= {o_tdata_par[63:0], o_tvalid_par[0], o_tready};
|
||||
endcase
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<6; i=i+1) begin: dma_counter_generator
|
||||
always @(posedge clk) begin
|
||||
if (o_tvalid_par[i] & o_tready_par[i]) begin
|
||||
dma_out_sample_cnt[i] <= dma_out_sample_cnt[i] + 32'd1;
|
||||
dma_out_last_sample[i] <= o_tdata_par[(64*i)+63:64*i];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user