Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,77 @@
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#
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# Copyright 2015 Ettus Research LLC
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../..)
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = kintex7
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PART_ID = xc7k410t/ffg900/-2
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(RFNOC_SRCS) \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = ../../ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(IP_AURORA_64B66B_PCS_PMA_SRCS) \
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$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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$(AURORA_PHY_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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include $(BASE_DIR)/../sim/general/Makefile.srcs
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include $(BASE_DIR)/../sim/control/Makefile.srcs
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include $(BASE_DIR)/../sim/axi/Makefile.srcs
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# Define only one toplevel module
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SIM_TOP = aurora_loopback_tb
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# Simulation runtime in microseconds
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SIM_RUNTIME_US = 70
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SIM_SRCS = \
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$(abspath aurora_loopback_tb.sv) \
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$(SIM_GENERAL_SRCS) \
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$(SIM_CONTROL_SRCS) \
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$(SIM_AXI_SRCS)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,310 @@
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//
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// Copyright 2016 Ettus Research LLC
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//
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`timescale 1ns/1ps
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`define NS_PER_TICK 1
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`define NUM_TEST_CASES 13
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`include "sim_clks_rsts.vh"
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`include "sim_exec_report.vh"
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`include "sim_cvita_lib.svh"
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`include "sim_axi4_lib.svh"
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`include "sim_set_rb_lib.svh"
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module aurora_loopback_tb();
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`TEST_BENCH_INIT("aurora_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK)
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// Define all clocks and resets
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`DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock
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`DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert
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wire XG_CLK_N = ~XG_CLK_P;
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wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N;
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localparam PACKET_MODE = 1;
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// Aurora Loopback Topology:
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//
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// TB Simulus ====> |------------| |----------------|
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// | Aurora MAC | <===> | Aurora PCS/PMA | <====>||
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// TB Checker <==== |------------| |----------------| || Loopback through
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// ||
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// ====> |------------| |----------------| || perfect serial channel
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// Loopback | | Aurora MAC | <===> | Aurora PCS/PMA | <====>||
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// <==== |------------| |----------------|
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// Initialize DUT
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wire aurora_refclk, aurora_init_clk;
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wire m_user_clk, s_user_clk;
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wire m_user_rst, s_user_rst;
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wire m_channel_up, s_channel_up;
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wire m_hard_err, s_hard_err;
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wire m_soft_err, s_soft_err;
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aurora_phy_clk_gen aurora_clk_gen_i (
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.areset(GSR),
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.refclk_p(XG_CLK_P),
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.refclk_n(XG_CLK_N),
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.refclk(aurora_refclk),
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.clk156(),
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.init_clk(aurora_init_clk)
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);
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wire [63:0] m_i_tdata, m_o_tdata;
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wire m_i_tvalid, m_i_tready, m_o_tvalid;
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wire [63:0] s_i_tdata, s_o_tdata;
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wire s_i_tvalid, s_i_tready, s_o_tvalid;
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wire [63:0] loop_tdata;
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wire loop_tlast, loop_tvalid, loop_tready;
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wire [31:0] m_overruns, s_overruns;
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wire [31:0] m_soft_errors, s_soft_errors;
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reg m_bist_gen, m_bist_check, s_bist_loopback;
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reg [5:0] m_bist_rate;
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wire m_bist_locked;
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wire [47:0] m_bist_samps, m_bist_errors;
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cvita_master m_tx_chdr (.clk(m_user_clk));
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cvita_slave m_rx_chdr (.clk(s_user_clk));
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aurora_phy_x1 #(.SIMULATION(1)) aurora_phy_master_i (
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// Resets
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.areset(GSR),
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// Clocks
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.refclk(aurora_refclk),
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.user_clk(m_user_clk),
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.init_clk(aurora_init_clk),
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.user_rst(m_user_rst),
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// GTX Serial I/O
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.tx_p(SFP_LN0_P), .tx_n(SFP_LN0_N),
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.rx_p(SFP_LN1_P), .rx_n(SFP_LN1_N),
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// AXI4-Stream TX Interface
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.s_axis_tdata(m_i_tdata), .s_axis_tvalid(m_i_tvalid), .s_axis_tready(m_i_tready),
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// AXI4-Stream RX Interface
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.m_axis_tdata(m_o_tdata), .m_axis_tvalid(m_o_tvalid),
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// AXI4-Lite Config Interface
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.s_axi_awaddr(32'h0), .s_axi_araddr(32'h0), .s_axi_awvalid(1'b0), .s_axi_awready(),
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.s_axi_wdata(32'h0), .s_axi_wvalid(1'b0), .s_axi_wstrb(1'b0), .s_axi_wready(),
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.s_axi_bvalid(), .s_axi_bresp(), .s_axi_bready(1'b1),
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.s_axi_arready(), .s_axi_arvalid(1'b0),
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.s_axi_rdata(), .s_axi_rvalid(), .s_axi_rresp(), .s_axi_rready(1'b1),
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// Status and Error Reporting Interface
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.channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err)
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);
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aurora_axis_mac #(.PACKET_MODE(PACKET_MODE), .BIST_ENABLED(1)) aurora_mac_master_i (
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// Clocks and resets
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.phy_clk(m_user_clk), .phy_rst(m_user_rst),
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.sys_clk(m_user_clk), .sys_rst(m_user_rst),
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.clear(1'b0),
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// PHY Interface
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.phy_s_axis_tdata(m_o_tdata), .phy_s_axis_tvalid(m_o_tvalid),
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.phy_m_axis_tdata(m_i_tdata), .phy_m_axis_tvalid(m_i_tvalid), .phy_m_axis_tready(m_i_tready),
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// User Interface
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.s_axis_tdata(m_tx_chdr.axis.tdata), .s_axis_tlast(m_tx_chdr.axis.tlast),
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.s_axis_tvalid(m_tx_chdr.axis.tvalid), .s_axis_tready(m_tx_chdr.axis.tready),
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.m_axis_tdata(m_rx_chdr.axis.tdata), .m_axis_tlast(m_rx_chdr.axis.tlast),
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.m_axis_tvalid(m_rx_chdr.axis.tvalid), .m_axis_tready(m_rx_chdr.axis.tready),
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// Misc PHY
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.channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err),
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.overruns(m_overruns), .soft_errors(m_soft_errors),
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//BIST
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.bist_gen_en(m_bist_gen), .bist_checker_en(m_bist_check), .bist_loopback_en(1'b0), .bist_gen_rate(m_bist_rate),
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.bist_checker_locked(m_bist_locked), .bist_checker_samps(m_bist_samps), .bist_checker_errors(m_bist_errors)
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);
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aurora_phy_x1 #(.SIMULATION(1)) aurora_phy_slave_i (
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// Resets
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.areset(GSR),
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// Clocks
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.refclk(aurora_refclk),
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.user_clk(s_user_clk),
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.init_clk(aurora_init_clk),
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.user_rst(s_user_rst),
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// GTX Serial I/O
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.tx_p(SFP_LN1_P), .tx_n(SFP_LN1_N),
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.rx_p(SFP_LN0_P), .rx_n(SFP_LN0_N),
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// AXI4-Stream TX Interface
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.s_axis_tdata(s_i_tdata), .s_axis_tvalid(s_i_tvalid), .s_axis_tready(s_i_tready),
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// AXI4-Stream RX Interface
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.m_axis_tdata(s_o_tdata), .m_axis_tvalid(s_o_tvalid),
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// AXI4-Lite Config Interface
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// AXI4-Lite Config Interface
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.s_axi_awaddr(32'h0), .s_axi_araddr(32'h0), .s_axi_awvalid(1'b0), .s_axi_awready(),
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.s_axi_wdata(32'h0), .s_axi_wvalid(1'b0), .s_axi_wstrb(1'b0), .s_axi_wready(),
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.s_axi_bvalid(), .s_axi_bresp(), .s_axi_bready(1'b1),
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.s_axi_arready(), .s_axi_arvalid(1'b0),
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.s_axi_rdata(), .s_axi_rvalid(), .s_axi_rresp(), .s_axi_rready(1'b1),
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// Status and Error Reporting Interface
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.channel_up(s_channel_up), .hard_err(s_hard_err), .soft_err(s_soft_err)
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);
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aurora_axis_mac #(.PACKET_MODE(PACKET_MODE), .BIST_ENABLED(1)) aurora_mac_slave_i (
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// Clocks and resets
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.phy_clk(s_user_clk), .phy_rst(s_user_rst),
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.sys_clk(s_user_clk), .sys_rst(s_user_rst),
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.clear(1'b0),
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// PHY Interface
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.phy_s_axis_tdata(s_o_tdata), .phy_s_axis_tvalid(s_o_tvalid),
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.phy_m_axis_tdata(s_i_tdata), .phy_m_axis_tvalid(s_i_tvalid), .phy_m_axis_tready(s_i_tready),
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// User Interface
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.s_axis_tdata(loop_tdata), .s_axis_tlast(loop_tlast),
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.s_axis_tvalid(~s_bist_loopback & loop_tvalid), .s_axis_tready(loop_tready),
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.m_axis_tdata(loop_tdata), .m_axis_tlast(loop_tlast),
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.m_axis_tvalid(loop_tvalid), .m_axis_tready(~s_bist_loopback & loop_tready),
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// Misc PHY
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.channel_up(s_channel_up), .hard_err(s_hard_err), .soft_err(s_soft_err),
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.overruns(s_overruns), .soft_errors(s_soft_errors),
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//BIST
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.bist_gen_en(1'b0), .bist_checker_en(1'b0), .bist_loopback_en(s_bist_loopback), .bist_gen_rate(6'd0),
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.bist_checker_locked(), .bist_checker_samps(), .bist_checker_errors()
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);
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//Testbench variables
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cvita_hdr_t header, header_out;
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cvita_stats_t stats;
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logic [63:0] crc_cache;
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//------------------------------------------
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//Main thread for testbench execution
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//------------------------------------------
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initial begin : tb_main
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string s;
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`TEST_CASE_START("Wait for reset");
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while (GSR) @(posedge XG_CLK_P);
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`TEST_CASE_DONE((~GSR));
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m_bist_gen <= 1'b0;
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m_bist_rate <= 6'd0;
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m_bist_check <= 1'b0;
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s_bist_loopback <= 1'b0;
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m_tx_chdr.push_bubble();
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`TEST_CASE_START("Wait for master channel to come up");
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while (m_channel_up !== 1'b1) @(posedge m_user_clk);
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`TEST_CASE_DONE(1'b1);
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`TEST_CASE_START("Wait for slave channel to come up");
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while (s_channel_up !== 1'b1) @(posedge s_user_clk);
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`TEST_CASE_DONE(1'b1);
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`TEST_CASE_START("Run PRBS BIST");
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s_bist_loopback <= PACKET_MODE;
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@(posedge m_user_clk);
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m_bist_rate <= 6'd60;
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m_bist_gen <= 1'b1;
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m_bist_check <= 1'b1;
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@(posedge m_user_clk);
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while (m_bist_locked !== 1'b1) @(posedge m_user_clk);
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repeat (512) @(posedge m_user_clk);
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`ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect");
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`ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!");
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@(posedge m_user_clk);
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m_bist_gen <= 1'b0;
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repeat (256) @(posedge m_user_clk);
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m_bist_check <= 1'b0;
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`TEST_CASE_DONE(1'b1);
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header = '{
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pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666,
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length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};
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`TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
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m_rx_chdr.axis.tready = 0;
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m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header);
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||||
m_rx_chdr.axis.tready = 1;
|
||||
m_rx_chdr.wait_for_pkt_get_info(header_out, stats);
|
||||
`ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch");
|
||||
$sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x",
|
||||
{header.src_sid,header.dst_sid},{header_out.src_sid,header_out.dst_sid});
|
||||
`ASSERT_ERROR({header.src_sid,header.dst_sid}=={header_out.src_sid,header_out.dst_sid}, s);
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Fill up empty FIFO then drain (long packet)");
|
||||
m_rx_chdr.axis.tready = 0;
|
||||
m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header);
|
||||
m_rx_chdr.axis.tready = 1;
|
||||
m_rx_chdr.wait_for_pkt_get_info(header_out, stats);
|
||||
`ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch");
|
||||
$sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x",
|
||||
{header.src_sid,header.dst_sid},{header_out.src_sid,header_out.dst_sid});
|
||||
`ASSERT_ERROR({header.src_sid,header.dst_sid}=={header_out.src_sid,header_out.dst_sid}, s);
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
header = '{
|
||||
pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666,
|
||||
length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};
|
||||
|
||||
`TEST_CASE_START("Concurrent read and write (single packet)");
|
||||
repeat (10) @(posedge m_user_clk); //Wait for clear to go low
|
||||
m_rx_chdr.axis.tready = 1;
|
||||
fork
|
||||
begin
|
||||
m_tx_chdr.push_ramp_pkt(200, 64'd0, 64'h100, header);
|
||||
end
|
||||
begin
|
||||
m_rx_chdr.wait_for_pkt_get_info(header_out, stats);
|
||||
end
|
||||
join
|
||||
crc_cache = stats.crc; //Cache CRC for future test cases
|
||||
`ASSERT_ERROR(stats.count==200, "Bad packet: Length mismatch");
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Concurrent read and write (multiple packets)");
|
||||
m_rx_chdr.axis.tready = 1;
|
||||
fork
|
||||
begin
|
||||
repeat (20) begin
|
||||
m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header);
|
||||
m_tx_chdr.push_bubble();
|
||||
end
|
||||
end
|
||||
begin
|
||||
repeat (20) begin
|
||||
m_rx_chdr.wait_for_pkt_get_info(header_out, stats);
|
||||
`ASSERT_ERROR(stats.count==20, "Bad packet: Length mismatch");
|
||||
`ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC");
|
||||
end
|
||||
end
|
||||
join
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Validate no drops (master)");
|
||||
`TEST_CASE_DONE((m_overruns === 32'd0));
|
||||
|
||||
`TEST_CASE_START("Validate no drops (slave)");
|
||||
`TEST_CASE_DONE((s_overruns === 32'd0));
|
||||
|
||||
s_bist_loopback <= 1'b1;
|
||||
|
||||
`TEST_CASE_START("Run PRBS BIST (Loopback Mode)");
|
||||
@(posedge m_user_clk);
|
||||
m_bist_gen <= 1'b1;
|
||||
m_bist_rate <= 6'd60;
|
||||
m_bist_check <= 1'b1;
|
||||
@(posedge m_user_clk);
|
||||
while (m_bist_locked !== 1'b1) @(posedge m_user_clk);
|
||||
repeat (512) @(posedge m_user_clk);
|
||||
`ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect");
|
||||
`ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!");
|
||||
@(posedge m_user_clk);
|
||||
m_bist_gen <= 1'b0;
|
||||
repeat (256) @(posedge m_user_clk);
|
||||
m_bist_check <= 1'b0;
|
||||
`TEST_CASE_DONE(1'b1);
|
||||
|
||||
s_bist_loopback <= 1'b0;
|
||||
|
||||
`TEST_CASE_START("Validate no drops (master)");
|
||||
`TEST_CASE_DONE((m_overruns === 32'd0));
|
||||
|
||||
`TEST_CASE_START("Validate no drops (slave)");
|
||||
`TEST_CASE_DONE((s_overruns === 32'd0));
|
||||
|
||||
`TEST_BENCH_DONE;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user