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Merge FPGA repository back into UHD repository

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The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
2020-01-28 09:35:36 -08:00
co-authored by Alex Williams Andrej Rode Ashish Chaudhari Ben Hilburn Ciro Nishiguchi Daniel Jepson Derek Kozel EJ Kreinar Humberto Jimenez Ian Buckley Jörg Hofrichter Jon Kiser Josh Blum Jonathon Pendlum Matt Ettus Michael West Moritz Fischer Nick Foster Nicolas Cuervo Paul Butler Paul David Ryan Marlow Sugandha Gupta Sylvain Munaut Trung Tran Vidush Vishwanath Wade Fife
parent 74893643ca
commit 6b67702ad7
2157 changed files with 1282567 additions and 0 deletions
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top/x300/.gitignore
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build
build-*
isim*
fuse*
tmp*
*.log
*.jou
*impact*
top/x300/Makefile
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#
# Copyright 2012-2016 Ettus Research LLC
#
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP X3X0 FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
##
##Output:
## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
## build/usrp_<product>_fpga_<image_type>.bin: Configuration bitstream without header
## build/usrp_<product>_fpga_<image_type>.lvbitx: Configuration bitstream for PCIe (NI-RIO)
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Debug Options
# Uncomment the following line to add a debug UART on GPIO 10 & 11
#OPTIONS += DEBUG_UART=1
CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS)
XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS)
HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS)
XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
ifdef CHECK
TARGET = rtl
else ifdef SYNTH
TARGET = synth
else
TARGET = bin
endif
endif
TOP ?= x300
DEFAULT_IMAGE_CORE_FILE_X300=x300_rfnoc_image_core.v
DEFAULT_IMAGE_CORE_FILE_X310=x310_rfnoc_image_core.v
DEFAULT_EDGE_FILE_X300=$(abspath x300_static_router.hex)
DEFAULT_EDGE_FILE_X310=$(abspath x310_static_router.hex)
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
# post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream files..."; \
cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
echo "Generating LVBITX..."; \
$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
echo "Exporting build report..."; \
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
endif
##
##Supported Targets
##-----------------
##all: X300_HG X310_HG X300_XG X310_XG (Default target)
all: X300_HG X310_HG X300_XG X310_XG
##X310_1G: 1GigE on both SFP+ ports.
X310_1G:
$(call vivado_build,X310,$(GIGE_DEFS) X310=1)
$(call post_build,X310,1G)
##X300_1G: 1GigE on both SFP+ ports.
X300_1G:
$(call vivado_build,X300,$(GIGE_DEFS) X300=1)
$(call post_build,X300,1G)
##X310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
X310_HG:
$(call vivado_build,X310,$(HG_DEFS) X310=1)
$(call post_build,X310,HG)
##X300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
X300_HG:
$(call vivado_build,X300,$(HG_DEFS) X300=1)
$(call post_build,X300,HG)
##X310_XG: 10GigE on both SFP+ ports.
X310_XG:
$(call vivado_build,X310,$(XG_DEFS) X310=1)
$(call post_build,X310,XG)
##X300_XG: 10GigE on both SFP+ ports.
X300_XG:
$(call vivado_build,X300,$(XG_DEFS) X300=1)
$(call post_build,X300,XG)
##X310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
X310_HA:
$(call vivado_build,X310,$(HA_DEFS) X310=1)
$(call post_build,X310,HA)
##X300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
X300_HA:
$(call vivado_build,X300,$(HA_DEFS) X300=1)
$(call post_build,X300,HA)
##X310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
X310_XA:
$(call vivado_build,X310,$(XA_DEFS) X310=1)
$(call post_build,X310,XA)
##X300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
X300_XA:
$(call vivado_build,X300,$(XA_DEFS) X300=1)
$(call post_build,X300,XA)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf build-X3*_*
@rm -rf build
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf build-X3*_*
@rm -rf build
help: ##Show this help message.
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
.PHONY: all clean cleanall help
top/x300/Makefile.x300.inc
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#
# Copyright 2008-2012 Ettus Research LLC
#
##################################################
# Project Setup
##################################################
# TOP_MODULE = <Input arg>
# NAME = <Input arg>
# PART_ID = <Input arg>
# ARCH = <Input arg>
##################################################
# Include other makefiles
##################################################
BASE_DIR = $(abspath ..)
IP_DIR = $(abspath ./ip)
include $(BASE_DIR)/../tools/make/viv_design_builder.mak
include $(IP_DIR)/Makefile.inc
include coregen_dsp/Makefile.srcs
include $(LIB_DIR)/ip/Makefile.inc
include $(LIB_DIR)/hls/Makefile.inc
include $(LIB_DIR)/control/Makefile.srcs
include $(LIB_DIR)/fifo/Makefile.srcs
include $(LIB_DIR)/simple_gemac/Makefile.srcs
include $(LIB_DIR)/timing/Makefile.srcs
include $(LIB_DIR)/zpu/Makefile.srcs
include $(LIB_DIR)/wishbone/Makefile.srcs
include $(LIB_DIR)/packet_proc/Makefile.srcs
include $(LIB_DIR)/xge/Makefile.srcs
include $(LIB_DIR)/xge_interface/Makefile.srcs
include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/io_port2/Makefile.srcs
include $(LIB_DIR)/axi/Makefile.srcs
include $(LIB_DIR)/io_cap_gen/Makefile.srcs
include $(LIB_DIR)/rfnoc/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
##################################################
TOP_SRCS = \
x300.v \
x300_pcie_int.v \
x300_core.v \
x300_sfpp_io_core.v \
x300_zpu_config.vhd \
x300_eth_interface.v \
nirio_chdr64_adapter.v \
soft_ctrl.v \
capture_ddrlvds.v \
gen_ddrlvds.v \
bus_int.v \
x300.xdc \
timing.xdc \
$(IMAGE_CORE)
ifdef BUILD_10G
SFP_SERDES_SRCS += $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.xdc) $(TEN_GIGE_PHY_SRCS) $(IP_TEN_GIGE_PHY_XCI_SRCS)
endif
ifdef BUILD_1G
SFP_SERDES_SRCS += $(abspath x300_1ge.xdc) $(ONE_GIGE_PHY_SRCS) $(IP_ONE_GIGE_PHY_XCI_SRCS)
endif
ifdef BUILD_AURORA
SFP_SERDES_SRCS += $(abspath x300_aurora.xdc) $(AURORA_PHY_SRCS) $(IP_AURORA_XCI_SRCS)
endif
ifdef SFP0_10GBE
SFP_SERDES_SRCS += $(abspath x300_10ge_port0.xdc)
endif
ifdef SFP1_10GBE
SFP_SERDES_SRCS += $(abspath x300_10ge_port1.xdc)
endif
ifndef NO_DRAM_FIFOS
DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath x300_dram.xdc)
else
DRAM_SRCS =
endif
DESIGN_SRCS = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
$(UDP_SRCS) $(EXTRAM_SRCS) \
$(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \
$(SFP_SERDES_SRCS) $(IOPORT2_SRCS) \
$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_OOT_SRCS)
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs $$(DESIGN_SRCS) ip
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x300.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs $$(DESIGN_SRCS) ip
$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
rtl: .prereqs $$(DESIGN_SRCS) ip
$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
.PHONY: bin rtl
top/x300/build_x300.tcl
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#
# Copyright 2014-2015 Ettus Research
#
source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
# STEP#1: Create project, add sources, refresh IP
vivado_utils::initialize_project
# STEP#2: Run synthesis
vivado_utils::synthesize_design
vivado_utils::generate_post_synth_reports
# STEP#3: Run implementation strategy
set x3xx_strategy [dict create]
dict set x3xx_strategy "opt_design.is_enabled" 1
dict set x3xx_strategy "opt_design.directive" "NoBramPowerOpt"
dict set x3xx_strategy "post_opt_power_opt_design.is_enabled" 0
dict set x3xx_strategy "place_design.directive" "ExtraNetDelay_high"
dict set x3xx_strategy "post_place_power_opt_design.is_enabled" 0
dict set x3xx_strategy "post_place_phys_opt_design.is_enabled" 1
dict set x3xx_strategy "post_place_phys_opt_design.directive" "AggressiveExplore"
dict set x3xx_strategy "route_design.directive" "Explore"
dict set x3xx_strategy "route_design.more_options" "-tns_cleanup"
dict set x3xx_strategy "post_route_phys_opt_design.is_enabled" 1
dict set x3xx_strategy "post_route_phys_opt_design.directive" "Explore"
vivado_strategies::implement_design $x3xx_strategy
# STEP#4: Generate reports
vivado_utils::generate_post_route_reports
# STEP#5: Generate a bitstream, netlist and debug probes
# STC3 Requirement: Disable waiting for DCI Match
set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [get_designs *]
# STC3 Requirement: No bitstream compression
set_property BITSTREAM.GENERAL.COMPRESS False [get_designs *]
# Use 6MHz clock to configure bitstream
set_property BITSTREAM.CONFIG.CONFIGRATE 6 [get_designs *]
vivado_utils::write_implementation_outputs
# Cleanup
vivado_utils::close_batch_project
top/x300/bus_int.v
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//
// Copyright 2013 Ettus Research LLC
// Copyright 2017 Ettus Research, a National Instruments Company
// Copyright 2019 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
module bus_int #(
parameter NUM_RADIOS = 2,
parameter NUM_CHANNELS_PER_RADIO = 2,
parameter NUM_CHANNELS = 4
)(
input clk, input clk_div2, input reset, input reset_div2,
output sen, output sclk, output mosi, input miso,
inout scl0, inout sda0,
inout scl1, inout sda1,
inout scl2, inout sda2,
output gps_txd, input gps_rxd,
output debug_txd, input debug_rxd,
output [1:0] leds,
output [3:0] sw_rst,
// Timekeeper
input pps,
// Block connections
input ce_clk,
input ce_rst,
// Radio Connections
input radio_clk,
input radio_rst,
input [ NUM_CHANNELS-1:0] radio_rx_stb,
input [32*NUM_CHANNELS-1:0] radio_rx_data,
output [ NUM_CHANNELS-1:0] radio_rx_running,
input [ NUM_CHANNELS-1:0] radio_tx_stb,
output [32*NUM_CHANNELS-1:0] radio_tx_data,
output [ NUM_CHANNELS-1:0] radio_tx_running,
// Daughter Board Settings Buses
output [ NUM_RADIOS-1:0] db_fe_set_stb,
output [ 8*NUM_RADIOS-1:0] db_fe_set_addr,
output [32*NUM_RADIOS-1:0] db_fe_set_data,
input [ NUM_RADIOS-1:0] db_fe_rb_stb,
output [ 8*NUM_RADIOS-1:0] db_fe_rb_addr,
input [64*NUM_RADIOS-1:0] db_fe_rb_data,
// SFP+ 0
input SFPP0_ModAbs, input SFPP0_TxFault, input SFPP0_RxLOS, inout SFPP0_RS0, inout SFPP0_RS1,
// SFP+ 1
input SFPP1_ModAbs, input SFPP1_TxFault, input SFPP1_RxLOS, inout SFPP1_RS0, inout SFPP1_RS1,
// Clock control and status
input [7:0] clock_status, output [7:0] clock_control, output [31:0] ref_freq, output ref_freq_changed,
// SFP+ 0 data stream
output [63:0] sfp0_tx_tdata, output [3:0] sfp0_tx_tuser, output sfp0_tx_tlast, output sfp0_tx_tvalid, input sfp0_tx_tready,
input [63:0] sfp0_rx_tdata, input [3:0] sfp0_rx_tuser, input sfp0_rx_tlast, input sfp0_rx_tvalid, output sfp0_rx_tready,
// SFP+ 1 data stream
output [63:0] sfp1_tx_tdata, output [3:0] sfp1_tx_tuser, output sfp1_tx_tlast, output sfp1_tx_tvalid, input sfp1_tx_tready,
input [63:0] sfp1_rx_tdata, input [3:0] sfp1_rx_tuser, input sfp1_rx_tlast, input sfp1_rx_tvalid, output sfp1_rx_tready,
// PCIe
output [63:0] pcio_tdata, output [2:0] pcio_tuser, output pcio_tlast, output pcio_tvalid, input pcio_tready,
input [63:0] pcii_tdata, input [2:0] pcii_tuser, input pcii_tlast, input pcii_tvalid, output pcii_tready,
//iop2 message fifos
output [63:0] o_iop2_msg_tdata, output o_iop2_msg_tvalid, output o_iop2_msg_tlast, input o_iop2_msg_tready,
input [63:0] i_iop2_msg_tdata, input i_iop2_msg_tvalid, input i_iop2_msg_tlast, output i_iop2_msg_tready,
//------------------------------------------------------------------
// Wishbone Slave Interface(s)
//------------------------------------------------------------------
input [31:0] sfp0_wb_dat_i,
output [31:0] sfp0_wb_dat_o,
output [15:0] sfp0_wb_adr,
output [3:0] sfp0_wb_sel,
input sfp0_wb_ack,
output sfp0_wb_stb,
output sfp0_wb_cyc,
output sfp0_wb_we,
input sfp0_wb_int, // IJB. Nothing to connect this too!! No IRQ controller on x300.
input [31:0] sfp1_wb_dat_i,
output [31:0] sfp1_wb_dat_o,
output [15:0] sfp1_wb_adr,
output [3:0] sfp1_wb_sel,
input sfp1_wb_ack,
output sfp1_wb_stb,
output sfp1_wb_cyc,
output sfp1_wb_we,
input sfp1_wb_int, // IJB. Nothing to connect this too!! No IRQ controller on x300.
input [15:0] sfp0_phy_status,
input [15:0] sfp1_phy_status,
input [31:0] xadc_readback,
//
// AXI4 (128b@250MHz) interface to DDR3 controller
//
input ddr3_axi_clk_x2,
input ddr3_axi_rst,
// Write Address Ports
output [1*2-1:0] ddr3_axi_awid,
output [32*2-1:0] ddr3_axi_awaddr,
output [8*2-1:0] ddr3_axi_awlen,
output [3*2-1:0] ddr3_axi_awsize,
output [2*2-1:0] ddr3_axi_awburst,
output [1*2-1:0] ddr3_axi_awlock,
output [4*2-1:0] ddr3_axi_awcache,
output [3*2-1:0] ddr3_axi_awprot,
output [4*2-1:0] ddr3_axi_awqos,
output [1*2-1:0] ddr3_axi_awvalid,
input [1*2-1:0] ddr3_axi_awready,
// Write Data Ports
output [64*2-1:0] ddr3_axi_wdata,
output [8*2-1:0] ddr3_axi_wstrb,
output [1*2-1:0] ddr3_axi_wlast,
output [1*2-1:0] ddr3_axi_wvalid,
input [1*2-1:0] ddr3_axi_wready,
// Write Response Ports
output [1*2-1:0] ddr3_axi_bready,
input [1*2-1:0] ddr3_axi_bid,
input [2*2-1:0] ddr3_axi_bresp,
input [1*2-1:0] ddr3_axi_bvalid,
// Read Address Ports
output [1*2-1:0] ddr3_axi_arid,
output [32*2-1:0] ddr3_axi_araddr,
output [8*2-1:0] ddr3_axi_arlen,
output [3*2-1:0] ddr3_axi_arsize,
output [2*2-1:0] ddr3_axi_arburst,
output [1*2-1:0] ddr3_axi_arlock,
output [4*2-1:0] ddr3_axi_arcache,
output [3*2-1:0] ddr3_axi_arprot,
output [4*2-1:0] ddr3_axi_arqos,
output [1*2-1:0] ddr3_axi_arvalid,
input [1*2-1:0] ddr3_axi_arready,
// Read Data Ports
input [1*2-1:0] ddr3_axi_rid,
input [64*2-1:0] ddr3_axi_rdata,
input [2*2-1:0] ddr3_axi_rresp,
input [1*2-1:0] ddr3_axi_rlast,
input [1*2-1:0] ddr3_axi_rvalid,
output [1*2-1:0] ddr3_axi_rready,
// Debug
output [31:0] debug0,
output [31:0] debug1,
output [127:0] debug2);
localparam SR_AWIDTH = 8;
localparam RB_AWIDTH = 8;
localparam SR_LEDS = 8'd00;
localparam SR_SW_RST = 8'd01;
localparam SR_CLOCK_CTRL = 8'd02;
localparam SR_DEVICE_ID = 8'd03;
localparam SR_REF_FREQ = 8'd04;
localparam SR_SFPP_CTRL0 = 8'd08;
localparam SR_SFPP_CTRL1 = 8'd09;
localparam SR_SPI = 8'd32;
localparam SR_ETHINT0 = 8'd40;
localparam SR_ETHINT1 = 8'd56;
//localparam SR_NEXT_ADDR = 8'd72;
localparam SR_BASE_TIME = 8'd100;
localparam RB_COUNTER = 8'd00;
localparam RB_SPI_RDY = 8'd01;
localparam RB_SPI_DATA = 8'd02;
localparam RB_CLK_STATUS = 8'd03;
localparam RB_ETH_TYPE0 = 8'd04;
localparam RB_ETH_TYPE1 = 8'd05;
localparam RB_COMPAT_NUM = 8'd06;
localparam RB_RFNOC_INFO = 8'd07;
localparam RB_SFPP_STATUS0 = 8'd08;
localparam RB_SFPP_STATUS1 = 8'd09;
localparam RB_GIT_HASH = 8'd10;
localparam RB_XADC_VALS = 8'd11;
localparam RB_NUM_TIMEKEEPERS = 8'd12;
localparam COMPAT_MAJOR = 16'h0026;
localparam COMPAT_MINOR = 16'h0000;
localparam NUM_TIMEKEEPERS = 1;
localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0};
wire [31:0] set_data;
wire [7:0] set_addr;
reg [31:0] rb_data;
wire [RB_AWIDTH-1:0] rb_addr;
wire rb_rd_stb;
wire set_stb;
wire spi_ready;
wire [31:0] rb_spi_data;
wire [15:0] device_id;
wire m_ctrlport_req_wr_radio0;
wire m_ctrlport_req_rd_radio0;
wire [19:0] m_ctrlport_req_addr_radio0;
wire [31:0] m_ctrlport_req_data_radio0;
wire [3:0] m_ctrlport_req_byte_en_radio0;
wire m_ctrlport_req_has_time_radio0;
wire [63:0] m_ctrlport_req_time_radio0;
wire m_ctrlport_resp_ack_radio0;
wire [1:0] m_ctrlport_resp_status_radio0;
wire [31:0] m_ctrlport_resp_data_radio0;
wire m_ctrlport_req_wr_radio1;
wire m_ctrlport_req_rd_radio1;
wire [19:0] m_ctrlport_req_addr_radio1;
wire [31:0] m_ctrlport_req_data_radio1;
wire [3:0] m_ctrlport_req_byte_en_radio1;
wire m_ctrlport_req_has_time_radio1;
wire [63:0] m_ctrlport_req_time_radio1;
wire m_ctrlport_resp_ack_radio1;
wire [1:0] m_ctrlport_resp_status_radio1;
wire [31:0] m_ctrlport_resp_data_radio1;
// ZPU in and ZPU out axi streams
wire [63:0] zpui_tdata, zpuo_tdata;
wire [3:0] zpui_tuser, zpuo_tuser;
wire zpui_tlast, zpuo_tlast, zpui_tvalid, zpuo_tvalid, zpui_tready, zpuo_tready;
wire [63:0] zpui0_tdata, zpuo0_tdata;
wire [3:0] zpui0_tuser, zpuo0_tuser;
wire zpui0_tlast, zpuo0_tlast, zpui0_tvalid, zpuo0_tvalid, zpui0_tready, zpuo0_tready;
wire [63:0] zpui1_tdata, zpuo1_tdata;
wire [3:0] zpui1_tuser, zpuo1_tuser;
wire zpui1_tlast, zpuo1_tlast, zpui1_tvalid, zpuo1_tvalid, zpui1_tready, zpuo1_tready;
// v2e (vita to ethernet) and e2v (eth to vita)
wire [63:0] v2e0_tdata, v2e1_tdata, e2v0_tdata, e2v1_tdata;
wire v2e0_tlast, v2e1_tlast, v2e0_tvalid, v2e1_tvalid, v2e0_tready, v2e1_tready;
wire e2v0_tlast, e2v1_tlast, e2v0_tvalid, e2v1_tvalid, e2v0_tready, e2v1_tready;
//settings bus for crossbar router
wire [31:0] set_data_xb;
wire [8:0] set_addr_xb;
wire set_stb_xb;
// SFP+ logic
wire SFPP0_ModAbs_sync, SFPP0_TxFault_sync, SFPP0_RxLOS_sync;
reg SFPP0_ModAbs_reg, SFPP0_TxFault_reg, SFPP0_RxLOS_reg;
reg SFPP0_ModAbs_chgd, SFPP0_TxFault_chgd, SFPP0_RxLOS_chgd;
wire SFPP1_ModAbs_sync, SFPP1_TxFault_sync, SFPP1_RxLOS_sync;
reg SFPP1_ModAbs_reg, SFPP1_TxFault_reg, SFPP1_RxLOS_reg;
reg SFPP1_ModAbs_chgd, SFPP1_TxFault_chgd, SFPP1_RxLOS_chgd;
wire [15:0] sfp0_phy_status_sync, sfp1_phy_status_sync;
////////////////////////////////////////////////////////////////////
// Soft CPU - drives network setup, soft reset, ICMP, ...
////////////////////////////////////////////////////////////////////
soft_ctrl #(.SB_ADDRW(SR_AWIDTH), .RB_ADDRW(RB_AWIDTH)) sc
(
.clk(clk), .rst(reset),
.clk_div2(clk_div2), .rst_div2(reset_div2),
//------------------------------------------------------------------
// I2C interfaces
//------------------------------------------------------------------
.scl0(scl0), .sda0(sda0),
.scl1(scl1), .sda1(sda1),
.scl2(scl2), .sda2(sda2),
//------------------------------------------------------------------
// UARTs for CPU comms
//------------------------------------------------------------------
.gps_rxd(gps_rxd), .gps_txd(gps_txd),
.debug_rxd(debug_rxd), .debug_txd(debug_txd),
//------------------------------------------------------------------
// settings bus interface
//------------------------------------------------------------------
.set_stb(set_stb),
.set_addr(set_addr),
.set_data(set_data),
//------------------------------------------------------------------
// settings bus interface for crossbar router
//------------------------------------------------------------------
.set_stb_xb(set_stb_xb),
.set_addr_xb(set_addr_xb),
.set_data_xb(set_data_xb),
//------------------------------------------------------------------
// readback bus interface
//------------------------------------------------------------------
.rb_addr(rb_addr),
.rb_data(rb_data),
.rb_rd_stb(rb_rd_stb),
//------------------------------------------------------------------
// packet interface in
//------------------------------------------------------------------
.rx_tdata(zpui_tdata),
.rx_tuser(zpui_tuser),
.rx_tlast(zpui_tlast),
.rx_tvalid(zpui_tvalid),
.rx_tready(zpui_tready),
//------------------------------------------------------------------
// packet interface out
//------------------------------------------------------------------
.tx_tdata(zpuo_tdata),
.tx_tuser(zpuo_tuser),
.tx_tlast(zpuo_tlast),
.tx_tvalid(zpuo_tvalid),
.tx_tready(zpuo_tready),
//------------------------------------------------------------------
// Wishbone Slave Interface(s)
//------------------------------------------------------------------
.s4_dat_i(sfp0_wb_dat_i),
.s4_dat_o(sfp0_wb_dat_o),
.s4_adr(sfp0_wb_adr),
.s4_sel(sfp0_wb_sel),
.s4_ack(sfp0_wb_ack),
.s4_stb(sfp0_wb_stb),
.s4_cyc(sfp0_wb_cyc),
.s4_we(sfp0_wb_we),
.s4_int(sfp0_wb_int),
//------------------------------------------------------------------
// IoPort2 Msg Interface
//------------------------------------------------------------------
.o_iop2_msg_tdata(o_iop2_msg_tdata),
.o_iop2_msg_tvalid(o_iop2_msg_tvalid),
.o_iop2_msg_tlast(o_iop2_msg_tlast),
.o_iop2_msg_tready(o_iop2_msg_tready),
.i_iop2_msg_tdata(i_iop2_msg_tdata),
.i_iop2_msg_tvalid(i_iop2_msg_tvalid),
.i_iop2_msg_tlast(i_iop2_msg_tlast),
.i_iop2_msg_tready(i_iop2_msg_tready),
.s5_dat_i(sfp1_wb_dat_i),
.s5_dat_o(sfp1_wb_dat_o),
.s5_adr(sfp1_wb_adr),
.s5_sel(sfp1_wb_sel),
.s5_ack(sfp1_wb_ack),
.s5_stb(sfp1_wb_stb),
.s5_cyc(sfp1_wb_cyc),
.s5_we(sfp1_wb_we),
.s5_int(sfp1_wb_int),
//------------------------------------------------------------------
// Debug
//------------------------------------------------------------------
.debug0(debug2),
.debug1()
);
setting_reg #(.my_addr(SR_LEDS), .awidth(SR_AWIDTH), .width(2)) set_leds
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(leds));
//
// SW_RST - Bit allocation:
// [0] - PHY reset
// [1] - Radio clk domain reset
// [2] - Radio Clk PLL reset.
// [3] - ADC IdelayCtrl reset
//
setting_reg #(.my_addr(SR_SW_RST), .awidth(SR_AWIDTH), .width(4)) set_sw_rst
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(sw_rst));
setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(8),
.at_reset(7'b1000000) //bit 6 high means GPSDO on by default
) set_clk_ctrl
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(clock_control));
setting_reg #(.my_addr(SR_DEVICE_ID), .awidth(SR_AWIDTH), .width(16),
.at_reset(32'd0)
) set_dev_id
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(device_id), .changed());
setting_reg #(.my_addr(SR_REF_FREQ), .awidth(SR_AWIDTH), .width(32),
.at_reset(32'd10_000_000) //default to 10 MHz reference clock
) set_ref_freq
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(ref_freq), .changed(ref_freq_changed));
simple_spi_core #(.BASE(SR_SPI), .WIDTH(1), .CLK_IDLE(0), .SEN_IDLE(1'b1)) misc_spi
(.clock(clk), .reset(reset),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.readback(rb_spi_data), .ready(spi_ready),
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
.debug());
reg [31:0] counter;
wire [31:0] rb_data_crossbar = 32'h0;
wire [63:0] radio_time_tb;
wire [63:0] radio_time_last_pps_tb;
wire [63:0] period_ns_q32_tb;
wire [63:0] radio_time;
wire [63:0] radio_time_last_pps;
reg [31:0] radio_time_hi;
reg [31:0] radio_time_last_pps_hi;
reg radio_time_hi_ld;
reg radio_time_last_pps_hi_ld;
always @(posedge clk) counter <= counter + 1;
always @* begin
radio_time_hi_ld = 1'b0;
radio_time_last_pps_hi_ld = 1'b0;
casex (rb_addr)
RB_RFNOC_INFO: rb_data = {device_id, RFNOC_PROTOVER[15:0]};
RB_COMPAT_NUM: rb_data = {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
RB_COUNTER: rb_data = counter;
RB_SPI_RDY: rb_data = {31'b0, spi_ready};
RB_SPI_DATA: rb_data = rb_spi_data;
RB_CLK_STATUS: rb_data = {24'b0, clock_status};
// SFPP Interface pins.
RB_SFPP_STATUS0: rb_data = {
sfp0_phy_status_sync, 10'b0,
SFPP0_ModAbs_chgd, SFPP0_TxFault_chgd, SFPP0_RxLOS_chgd,
SFPP0_ModAbs_sync, SFPP0_TxFault_sync, SFPP0_RxLOS_sync};
RB_SFPP_STATUS1: rb_data = {
sfp1_phy_status_sync, 10'b0,
SFPP1_ModAbs_chgd, SFPP1_TxFault_chgd, SFPP1_RxLOS_chgd,
SFPP1_ModAbs_sync, SFPP1_TxFault_sync, SFPP1_RxLOS_sync};
RB_NUM_TIMEKEEPERS: rb_data = NUM_TIMEKEEPERS;
// Allow readback of configured ethernet interfaces.
`ifdef SFP0_AURORA
RB_ETH_TYPE0: rb_data = {32'h2};
`else
`ifdef SFP0_10GBE
RB_ETH_TYPE0: rb_data = {32'h1};
`else
RB_ETH_TYPE0: rb_data = {32'h0};
`endif
`endif
`ifdef SFP1_AURORA
RB_ETH_TYPE1: rb_data = {32'h2};
`else
`ifdef SFP1_10GBE
RB_ETH_TYPE1: rb_data = {32'h1};
`else
RB_ETH_TYPE1: rb_data = {32'h0};
`endif
`endif
RB_GIT_HASH: rb_data = `GIT_HASH;
RB_XADC_VALS: rb_data = xadc_readback;
SR_BASE_TIME: begin
rb_data = radio_time[31:0];
radio_time_hi_ld = 1'b1;
end
SR_BASE_TIME + 'h04: rb_data = radio_time_hi;
SR_BASE_TIME + 'h14: begin
rb_data = radio_time_last_pps[31:0];
radio_time_last_pps_hi_ld = 1'b1;
end
SR_BASE_TIME + 'h18: rb_data = radio_time_last_pps_hi;
SR_BASE_TIME + 'h1C: rb_data = period_ns_q32_tb[31:0];
SR_BASE_TIME + 'h20: rb_data = period_ns_q32_tb[63:32];
default: begin
rb_data = 32'h0;
end
endcase // case (rb_addr)
end
always @(posedge clk_div2) begin
if (radio_time_hi_ld)
radio_time_hi <= radio_time[63:32];
if (radio_time_last_pps_hi_ld)
radio_time_last_pps_hi <= radio_time_last_pps[63:32];
end
// Timekeeper
axi_fifo_2clk #(
.WIDTH (64),
.SIZE (3)
) radio_time_clk_cross_fifo (
.reset (radio_rst),
.i_aclk (radio_clk),
.i_tdata (radio_time_tb),
.i_tvalid (1'b1),
.i_tready (),
.o_aclk (clk_div2),
.o_tdata (radio_time),
.o_tready (1'b1),
.o_tvalid ()
);
axi_fifo_2clk #(
.WIDTH (64),
.SIZE (3)
) radio_time_last_pps_clk_cross_fifo (
.reset (radio_rst),
.i_aclk (radio_clk),
.i_tdata (radio_time_last_pps_tb),
.i_tvalid (1'b1),
.i_tready (),
.o_aclk (clk_div2),
.o_tdata (radio_time_last_pps),
.o_tready (1'b1),
.o_tvalid ()
);
timekeeper #(
.BASE_ADDR (SR_BASE_TIME),
.TIME_INCREMENT (1'b1)
) timekeeper_i (
.tb_clk (radio_clk),
.tb_rst (radio_rst),
.s_ctrlport_clk (clk_div2),
.s_ctrlport_req_wr (set_stb),
.s_ctrlport_req_rd (),
.s_ctrlport_req_addr (set_addr),
.s_ctrlport_req_data (set_data),
.s_ctrlport_resp_ack (),
.s_ctrlport_resp_data (),
.sample_rx_stb (radio_rx_stb[0]),
.pps (pps),
.tb_timestamp (radio_time_tb),
.tb_timestamp_last_pps (radio_time_last_pps_tb),
.tb_period_ns_q32 (period_ns_q32_tb)
);
// Latch state changes to SFP0+ pins.
synchronizer #(.INITIAL_VAL(1'b0)) sfpp0_modabs_sync (
.clk(clk), .rst(1'b0 /* no reset */), .in(SFPP0_ModAbs), .out(SFPP0_ModAbs_sync));
synchronizer #(.INITIAL_VAL(1'b0)) sfpp0_txfault_sync (
.clk(clk), .rst(1'b0 /* no reset */), .in(SFPP0_TxFault), .out(SFPP0_TxFault_sync));
synchronizer #(.INITIAL_VAL(1'b0)) sfpp0_rxlos_sync (
.clk(clk), .rst(1'b0 /* no reset */), .in(SFPP0_RxLOS), .out(SFPP0_RxLOS_sync));
always @(posedge clk) begin
SFPP0_ModAbs_reg <= SFPP0_ModAbs_sync;
SFPP0_TxFault_reg <= SFPP0_TxFault_sync;
SFPP0_RxLOS_reg <= SFPP0_RxLOS_sync;
end
always @(posedge clk) begin
if (reset || (rb_rd_stb && (rb_addr == RB_SFPP_STATUS0))) begin
SFPP0_ModAbs_chgd <= 1'b0;
SFPP0_TxFault_chgd <= 1'b0;
SFPP0_RxLOS_chgd <= 1'b0;
end else begin
if (SFPP0_ModAbs_sync != SFPP0_ModAbs_reg)
SFPP0_ModAbs_chgd <= 1'b1;
if (SFPP0_TxFault_sync != SFPP0_TxFault_reg)
SFPP0_TxFault_chgd <= 1'b1;
if (SFPP0_RxLOS_sync != SFPP0_RxLOS_reg)
SFPP0_RxLOS_chgd <= 1'b1;
end
end
// Latch state changes to SFP1+ pins.
synchronizer #(.INITIAL_VAL(1'b0)) sfpp1_modabs_sync (
.clk(clk), .rst(1'b0 /* no reset */), .in(SFPP1_ModAbs), .out(SFPP1_ModAbs_sync));
synchronizer #(.INITIAL_VAL(1'b0)) sfpp1_txfault_sync (
.clk(clk), .rst(1'b0 /* no reset */), .in(SFPP1_TxFault), .out(SFPP1_TxFault_sync));
synchronizer #(.INITIAL_VAL(1'b0)) sfpp1_rxlos_sync (
.clk(clk), .rst(1'b0 /* no reset */), .in(SFPP1_RxLOS), .out(SFPP1_RxLOS_sync));
always @(posedge clk) begin
SFPP1_ModAbs_reg <= SFPP1_ModAbs_sync;
SFPP1_TxFault_reg <= SFPP1_TxFault_sync;
SFPP1_RxLOS_reg <= SFPP1_RxLOS_sync;
end
always @(posedge clk) begin
if (reset || (rb_rd_stb && (rb_addr == RB_SFPP_STATUS1))) begin
SFPP1_ModAbs_chgd <= 1'b0;
SFPP1_TxFault_chgd <= 1'b0;
SFPP1_RxLOS_chgd <= 1'b0;
end else begin
if (SFPP1_ModAbs_sync != SFPP1_ModAbs_reg)
SFPP1_ModAbs_chgd <= 1'b1;
if (SFPP1_TxFault_sync != SFPP1_TxFault_reg)
SFPP1_TxFault_chgd <= 1'b1;
if (SFPP1_RxLOS_sync != SFPP1_RxLOS_reg)
SFPP1_RxLOS_chgd <= 1'b1;
end
end
//Synchronize ethernet PHY status bits to bus_clk
//All bits in the bus can be treated as asynchronous
genvar i;
generate
for (i=0; i<16; i=i+1) begin: eth_status_synchronizer_gen
synchronizer #(.INITIAL_VAL(1'b0)) sfp0_status (
.clk(clk), .rst(1'b0 /* no reset */), .in(sfp0_phy_status[i]), .out(sfp0_phy_status_sync[i]));
synchronizer #(.INITIAL_VAL(1'b0)) sfp1_status (
.clk(clk), .rst(1'b0 /* no reset */), .in(sfp1_phy_status[i]), .out(sfp1_phy_status_sync[i]));
end
endgenerate
wire [1:0] sfpp0_ctrl;
// SFPP_RS0/1 pins are open drain.
setting_reg #(.my_addr(SR_SFPP_CTRL0), .awidth(SR_AWIDTH), .width(2), .at_reset(2'b00)) set_sfpp0_ctrl
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(sfpp0_ctrl));
assign SFPP0_RS0 = sfpp0_ctrl[0] ? 1'b0 : 1'bz;
assign SFPP0_RS1 = sfpp0_ctrl[1] ? 1'b0 : 1'bz;
wire [1:0] sfpp1_ctrl;
// SFPP1_RS0/1 pins are open drain.
setting_reg #(.my_addr(SR_SFPP_CTRL1), .awidth(SR_AWIDTH), .width(2), .at_reset(2'b00)) set_sfpp1_ctrl
(.clk(clk), .rst(reset),
.strobe(set_stb), .addr(set_addr), .in(set_data),
.out(sfpp1_ctrl));
assign SFPP1_RS0 = sfpp1_ctrl[0] ? 1'b0 : 1'bz;
assign SFPP1_RS1 = sfpp1_ctrl[1] ? 1'b0 : 1'bz;
// ////////////////////////////////////////////////////////////////
// ETH interfaces
`ifdef SFP0_AURORA
// The packet format over Aurora is CHDR so we don't need any special framing/deframing
assign {e2v0_tdata, e2v0_tlast, e2v0_tvalid, sfp0_rx_tready} = {sfp0_rx_tdata, sfp0_rx_tlast, sfp0_rx_tvalid, e2v0_tready};
assign {sfp0_tx_tdata, sfp0_tx_tlast, sfp0_tx_tvalid, v2e0_tready} = {v2e0_tdata, v2e0_tlast, v2e0_tvalid, sfp0_tx_tready};
assign {zpui0_tdata, zpui0_tlast, zpui0_tvalid, zpuo0_tready} = {64'h0, 1'b0, 1'b0, 1'b1};
`else
x300_eth_interface #(
.PROTOVER(RFNOC_PROTOVER), .MTU(10), .NODE_INST(0), .BASE(SR_ETHINT0)
) eth_interface0 (
.clk(clk), .reset(reset),
.device_id(device_id),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.eth_tx_tdata(sfp0_tx_tdata), .eth_tx_tuser(sfp0_tx_tuser), .eth_tx_tlast(sfp0_tx_tlast),
.eth_tx_tvalid(sfp0_tx_tvalid), .eth_tx_tready(sfp0_tx_tready),
.eth_rx_tdata(sfp0_rx_tdata), .eth_rx_tuser(sfp0_rx_tuser), .eth_rx_tlast(sfp0_rx_tlast),
.eth_rx_tvalid(sfp0_rx_tvalid), .eth_rx_tready(sfp0_rx_tready),
.e2v_tdata(e2v0_tdata), .e2v_tlast(e2v0_tlast), .e2v_tvalid(e2v0_tvalid), .e2v_tready(e2v0_tready),
.v2e_tdata(v2e0_tdata), .v2e_tlast(v2e0_tlast), .v2e_tvalid(v2e0_tvalid), .v2e_tready(v2e0_tready),
.e2z_tdata(zpui0_tdata), .e2z_tuser(zpui0_tuser), .e2z_tlast(zpui0_tlast), .e2z_tvalid(zpui0_tvalid), .e2z_tready(zpui0_tready),
.z2e_tdata(zpuo0_tdata), .z2e_tuser(zpuo0_tuser), .z2e_tlast(zpuo0_tlast), .z2e_tvalid(zpuo0_tvalid), .z2e_tready(zpuo0_tready)
);
`endif
`ifdef SFP1_AURORA
// The packet format over Aurora is CHDR so we don't need any special framing/deframing
assign {e2v1_tdata, e2v1_tlast, e2v1_tvalid, sfp1_rx_tready} = {sfp1_rx_tdata, sfp1_rx_tlast, sfp1_rx_tvalid, e2v1_tready};
assign {sfp1_tx_tdata, sfp1_tx_tlast, sfp1_tx_tvalid, v2e1_tready} = {v2e1_tdata, v2e1_tlast, v2e1_tvalid, sfp1_tx_tready};
assign {zpui1_tdata, zpui1_tlast, zpui1_tvalid, zpuo1_tready} = {64'h0, 1'b0, 1'b0, 1'b1};
`else
x300_eth_interface #(
.PROTOVER(RFNOC_PROTOVER), .MTU(10), .NODE_INST(1), .BASE(SR_ETHINT1)
) eth_interface1 (
.clk(clk), .reset(reset),
.device_id(device_id),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.eth_tx_tdata(sfp1_tx_tdata), .eth_tx_tuser(sfp1_tx_tuser), .eth_tx_tlast(sfp1_tx_tlast),
.eth_tx_tvalid(sfp1_tx_tvalid), .eth_tx_tready(sfp1_tx_tready),
.eth_rx_tdata(sfp1_rx_tdata), .eth_rx_tuser(sfp1_rx_tuser), .eth_rx_tlast(sfp1_rx_tlast),
.eth_rx_tvalid(sfp1_rx_tvalid), .eth_rx_tready(sfp1_rx_tready),
.e2v_tdata(e2v1_tdata), .e2v_tlast(e2v1_tlast), .e2v_tvalid(e2v1_tvalid), .e2v_tready(e2v1_tready),
.v2e_tdata(v2e1_tdata), .v2e_tlast(v2e1_tlast), .v2e_tvalid(v2e1_tvalid), .v2e_tready(v2e1_tready),
.e2z_tdata(zpui1_tdata), .e2z_tuser(zpui1_tuser), .e2z_tlast(zpui1_tlast), .e2z_tvalid(zpui1_tvalid), .e2z_tready(zpui1_tready),
.z2e_tdata(zpuo1_tdata), .z2e_tuser(zpuo1_tuser), .z2e_tlast(zpuo1_tlast), .z2e_tvalid(zpuo1_tvalid), .z2e_tready(zpuo1_tready)
);
`endif
axi_mux4 #(.PRIO(0), .WIDTH(68)) zpui_mux
(.clk(clk), .reset(reset), .clear(1'b0),
.i0_tdata({zpui0_tuser,zpui0_tdata}), .i0_tlast(zpui0_tlast), .i0_tvalid(zpui0_tvalid), .i0_tready(zpui0_tready),
.i1_tdata({zpui1_tuser,zpui1_tdata}), .i1_tlast(zpui1_tlast), .i1_tvalid(zpui1_tvalid), .i1_tready(zpui1_tready),
.i2_tdata(68'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
.i3_tdata(68'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
.o_tdata({zpui_tuser,zpui_tdata}), .o_tlast(zpui_tlast), .o_tvalid(zpui_tvalid), .o_tready(zpui_tready));
// Demux ZPU to Eth output by the port number in top 8 bits of data on first line
wire [67:0] zpuo_eth_header;
wire [1:0] zpuo_eth_dest = (zpuo_eth_header[63:56] == 8'd0) ? 2'b00 : 2'b01;
axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(68)) zpuo_demux
(.clk(clk), .reset(reset), .clear(1'b0),
.header(zpuo_eth_header), .dest(zpuo_eth_dest),
.i_tdata({zpuo_tuser,zpuo_tdata}), .i_tlast(zpuo_tlast), .i_tvalid(zpuo_tvalid), .i_tready(zpuo_tready),
.o0_tdata({zpuo0_tuser,zpuo0_tdata}), .o0_tlast(zpuo0_tlast), .o0_tvalid(zpuo0_tvalid), .o0_tready(zpuo0_tready),
.o1_tdata({zpuo1_tuser,zpuo1_tdata}), .o1_tlast(zpuo1_tlast), .o1_tvalid(zpuo1_tvalid), .o1_tready(zpuo1_tready),
.o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
//
// End ETH interfaces
////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// PCIe Interface
//
localparam DMA_RX_DEST_WIDTH = 3;
// PCIe to CHDR (p2c) and CHDR to PCIe (c2p)
wire [63:0] p2c_tdata;
wire p2c_tlast, p2c_tvalid, p2c_tready;
wire [63:0] c2p_tdata;
wire c2p_tlast, c2p_tvalid, c2p_tready;
// Transport adapter with the management interface
nirio_chdr64_adapter #(
.PROTOVER(RFNOC_PROTOVER),
.DMA_ID_WIDTH(DMA_RX_DEST_WIDTH)
) nirio_xport_adapter
(
.clk(clk), .rst(reset),
.device_id(device_id),
// From x300_pcie_int
.s_dma_tdata(pcii_tdata),
.s_dma_tuser(pcii_tuser),
.s_dma_tlast(pcii_tlast),
.s_dma_tvalid(pcii_tvalid),
.s_dma_tready(pcii_tready),
// To x300_pcie_int
.m_dma_tdata(pcio_tdata),
.m_dma_tuser(pcio_tuser),
.m_dma_tlast(pcio_tlast),
.m_dma_tvalid(pcio_tvalid),
.m_dma_tready(pcio_tready),
// From xport adapter into the image core
.m_chdr_tdata(p2c_tdata),
.m_chdr_tlast(p2c_tlast),
.m_chdr_tvalid(p2c_tvalid),
.m_chdr_tready(p2c_tready),
// From image core into the xport adapter
.s_chdr_tdata(c2p_tdata),
.s_chdr_tlast(c2p_tlast),
.s_chdr_tvalid(c2p_tvalid),
.s_chdr_tready(c2p_tready)
);
//
// End PCIe Interface
///////////////////////////////////////////////////////////////////////////
rfnoc_image_core #(
.PROTOVER(RFNOC_PROTOVER)
) rfnoc_sandbox_i (
.chdr_aclk (clk ),
.ctrl_aclk (clk_div2 ),
.core_arst (reset ),
.device_id (device_id ),
.radio_clk (radio_clk ),
.ce_clk (ce_clk ),
.dram_clk (ddr3_axi_clk_x2),
.m_ctrlport_radio1_req_wr (m_ctrlport_req_wr_radio1 ),
.m_ctrlport_radio1_req_rd (m_ctrlport_req_rd_radio1 ),
.m_ctrlport_radio1_req_addr (m_ctrlport_req_addr_radio1 ),
.m_ctrlport_radio1_req_data (m_ctrlport_req_data_radio1 ),
.m_ctrlport_radio1_req_byte_en (m_ctrlport_req_byte_en_radio1 ),
.m_ctrlport_radio1_req_has_time (m_ctrlport_req_has_time_radio1),
.m_ctrlport_radio1_req_time (m_ctrlport_req_time_radio1 ),
.m_ctrlport_radio1_resp_ack (m_ctrlport_resp_ack_radio1 ),
.m_ctrlport_radio1_resp_status (m_ctrlport_resp_status_radio1 ),
.m_ctrlport_radio1_resp_data (m_ctrlport_resp_data_radio1 ),
.m_ctrlport_radio0_req_wr (m_ctrlport_req_wr_radio0 ),
.m_ctrlport_radio0_req_rd (m_ctrlport_req_rd_radio0 ),
.m_ctrlport_radio0_req_addr (m_ctrlport_req_addr_radio0 ),
.m_ctrlport_radio0_req_data (m_ctrlport_req_data_radio0 ),
.m_ctrlport_radio0_req_byte_en (m_ctrlport_req_byte_en_radio0 ),
.m_ctrlport_radio0_req_has_time (m_ctrlport_req_has_time_radio0),
.m_ctrlport_radio0_req_time (m_ctrlport_req_time_radio0 ),
.m_ctrlport_radio0_resp_ack (m_ctrlport_resp_ack_radio0 ),
.m_ctrlport_radio0_resp_status (m_ctrlport_resp_status_radio0 ),
.m_ctrlport_radio0_resp_data (m_ctrlport_resp_data_radio0 ),
.radio_time (radio_time_tb ),
.radio_rx_stb_radio0 (radio_rx_stb[1:0] ),
.radio_rx_data_radio0 (radio_rx_data[63:0] ),
.radio_rx_running_radio0 (radio_rx_running[1:0] ),
.radio_tx_stb_radio0 (radio_tx_stb[1:0] ),
.radio_tx_data_radio0 (radio_tx_data[63:0] ),
.radio_tx_running_radio0 (radio_tx_running[1:0] ),
.radio_rx_stb_radio1 (radio_rx_stb[3:2] ),
.radio_rx_data_radio1 (radio_rx_data[127:64] ),
.radio_rx_running_radio1 (radio_rx_running[3:2] ),
.radio_tx_stb_radio1 (radio_tx_stb[3:2] ),
.radio_tx_data_radio1 (radio_tx_data[127:64] ),
.radio_tx_running_radio1 (radio_tx_running[3:2] ),
// DRAM interface
.axi_rst (ddr3_axi_rst),
// Slave Interface Write Address Ports
.m_axi_awid (ddr3_axi_awid ),
.m_axi_awaddr (ddr3_axi_awaddr ),
.m_axi_awlen (ddr3_axi_awlen ),
.m_axi_awsize (ddr3_axi_awsize ),
.m_axi_awburst (ddr3_axi_awburst),
.m_axi_awlock (ddr3_axi_awlock ),
.m_axi_awcache (ddr3_axi_awcache),
.m_axi_awprot (ddr3_axi_awprot ),
.m_axi_awqos (ddr3_axi_awqos ),
.m_axi_awregion (),
.m_axi_awuser (),
.m_axi_awvalid (ddr3_axi_awvalid),
.m_axi_awready (ddr3_axi_awready),
// Slave Interface Write Data Ports
.m_axi_wdata (ddr3_axi_wdata ),
.m_axi_wstrb (ddr3_axi_wstrb ),
.m_axi_wlast (ddr3_axi_wlast ),
.m_axi_wuser (),
.m_axi_wvalid (ddr3_axi_wvalid),
.m_axi_wready (ddr3_axi_wready),
// Slave Interface Write Response Ports
.m_axi_bid (ddr3_axi_bid ),
.m_axi_bresp (ddr3_axi_bresp ),
.m_axi_buser (),
.m_axi_bvalid (ddr3_axi_bvalid),
.m_axi_bready (ddr3_axi_bready),
// Slave Interface Read Address Ports
.m_axi_arid (ddr3_axi_arid ),
.m_axi_araddr (ddr3_axi_araddr ),
.m_axi_arlen (ddr3_axi_arlen ),
.m_axi_arsize (ddr3_axi_arsize ),
.m_axi_arburst (ddr3_axi_arburst),
.m_axi_arlock (ddr3_axi_arlock ),
.m_axi_arcache (ddr3_axi_arcache),
.m_axi_arprot (ddr3_axi_arprot ),
.m_axi_arqos (ddr3_axi_arqos ),
.m_axi_arregion (),
.m_axi_aruser (),
.m_axi_arvalid (ddr3_axi_arvalid),
.m_axi_arready (ddr3_axi_arready),
// Slave Interface Read Data Ports
.m_axi_rid (ddr3_axi_rid ),
.m_axi_rdata (ddr3_axi_rdata ),
.m_axi_rresp (ddr3_axi_rresp ),
.m_axi_rlast (ddr3_axi_rlast ),
.m_axi_ruser (),
.m_axi_rvalid (ddr3_axi_rvalid),
.m_axi_rready (ddr3_axi_rready),
.s_eth0_tdata (e2v0_tdata ),
.s_eth0_tlast (e2v0_tlast ),
.s_eth0_tvalid (e2v0_tvalid),
.s_eth0_tready (e2v0_tready),
.m_eth0_tdata (v2e0_tdata ),
.m_eth0_tlast (v2e0_tlast ),
.m_eth0_tvalid (v2e0_tvalid),
.m_eth0_tready (v2e0_tready),
.s_eth1_tdata (e2v1_tdata ),
.s_eth1_tlast (e2v1_tlast ),
.s_eth1_tvalid (e2v1_tvalid),
.s_eth1_tready (e2v1_tready),
.m_eth1_tdata (v2e1_tdata ),
.m_eth1_tlast (v2e1_tlast ),
.m_eth1_tvalid (v2e1_tvalid),
.m_eth1_tready (v2e1_tready),
.s_pcie_tdata (p2c_tdata ),
.s_pcie_tlast (p2c_tlast ),
.s_pcie_tvalid (p2c_tvalid),
.s_pcie_tready (p2c_tready),
.m_pcie_tdata (c2p_tdata ),
.m_pcie_tlast (c2p_tlast ),
.m_pcie_tvalid (c2p_tvalid),
.m_pcie_tready (c2p_tready)
);
//---------------------------------------------------------------------------
// Convert Control Port to Settings Bus
//---------------------------------------------------------------------------
localparam NUM_CTRLPORTS_PER_DBOARD = 1;
ctrlport_to_settings_bus # (
.NUM_PORTS (NUM_CTRLPORTS_PER_DBOARD),
.USE_TIME (1)
) ctrlport0_to_settings_bus_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (m_ctrlport_req_wr_radio0),
.s_ctrlport_req_rd (m_ctrlport_req_rd_radio0),
.s_ctrlport_req_addr (m_ctrlport_req_addr_radio0),
.s_ctrlport_req_data (m_ctrlport_req_data_radio0),
.s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio0),
.s_ctrlport_req_time (m_ctrlport_req_time_radio0),
.s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio0),
.s_ctrlport_resp_data (m_ctrlport_resp_data_radio0),
.set_data (db_fe_set_data[31:0]),
.set_addr (db_fe_set_addr[7:0]),
.set_stb (db_fe_set_stb[0]),
.set_time (),
.set_has_time (),
.rb_stb (db_fe_rb_stb[0]),
.rb_addr (db_fe_rb_addr[7:0]),
.rb_data (db_fe_rb_data[63:0]),
.timestamp (radio_time_tb)
);
ctrlport_to_settings_bus # (
.NUM_PORTS (NUM_CTRLPORTS_PER_DBOARD),
.USE_TIME (1)
) ctrlport1_to_settings_bus_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (m_ctrlport_req_wr_radio1),
.s_ctrlport_req_rd (m_ctrlport_req_rd_radio1),
.s_ctrlport_req_addr (m_ctrlport_req_addr_radio1),
.s_ctrlport_req_data (m_ctrlport_req_data_radio1),
.s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio1),
.s_ctrlport_req_time (m_ctrlport_req_time_radio1),
.s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio1),
.s_ctrlport_resp_data (m_ctrlport_resp_data_radio1),
.set_data (db_fe_set_data[63:32]),
.set_addr (db_fe_set_addr[15:8]),
.set_stb (db_fe_set_stb[1]),
.set_time (),
.set_has_time (),
.rb_stb (db_fe_rb_stb[1]),
.rb_addr (db_fe_rb_addr[15:8]),
.rb_data (db_fe_rb_data[127:64]),
.timestamp (radio_time_tb)
);
endmodule // bus_int
top/x300/capture_ddrlvds.v
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//
// Copyright 2011-2014 Ettus Research LLC
// Copyright 2017 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// The two clocks are aligned externally in order to eliminate the need for a FIFO.
// A FIFO cannot be used to transition between clock domains because it can cause
// alignment issues between the output of multiple modules.
module capture_ddrlvds #(
parameter WIDTH = 14, //Width of the SS data bus
parameter PATT_CHECKER = "FALSE", //{TRUE, FALSE}: Is the integrated ramp pattern checker
parameter DATA_IDELAY_MODE = "BYPASSED", //{BYPASSED, FIXED, DYNAMIC}
parameter DATA_IDELAY_VAL = 16, //IDELAY value for FIXED mode. In DYNAMIC mode, this value is used by the timing analyzer
parameter DATA_IDELAY_FREF = 200.0 //Reference clock frequency for the IDELAYCTRL
) (
// ADC IO Pins
input adc_clk_p,
input adc_clk_n,
input [WIDTH-1:0] adc_data_p,
input [WIDTH-1:0] adc_data_n,
//System synchronous clock
input radio_clk,
//IDELAY settings
input data_delay_stb,
input [4:0] data_delay_val,
//Capture clock and output data
output adc_cap_clk,
output [(2*WIDTH)-1:0] data_out,
//Pattern checker options (sync to radio_clk)
input checker_en,
output [3:0] checker_locked,
output [3:0] checker_failed
);
//-------------------------------------------------------------------
// Clock Path
wire adc_buf_clk;
// Route source synchronous clock to differential input clock buffer
// then to a global clock buffer. We route to a global buffer because
// the data bus being capture spans multiple banks.
IBUFGDS ss_clk_ibufgds_i (
.I(adc_clk_p), .IB(adc_clk_n),
.O(adc_buf_clk)
);
BUFG ss_clk_bufg_i (
.I(adc_buf_clk),
.O(adc_cap_clk)
);
//-------------------------------------------------------------------
// Data Path
wire [WIDTH-1:0] adc_data_buf, adc_data_del;
wire [(2*WIDTH)-1:0] adc_data_aclk;
reg [(2*WIDTH)-1:0] adc_data_rclk, adc_data_rclk_sync;
genvar i;
generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins
// Use a differential IO buffer to get the data into the IOB
IBUFDS ibufds_i (
.I(adc_data_p[i]), .IB(adc_data_n[i]),
.O(adc_data_buf[i])
);
// Use an optional IDELAY to tune the capture interface from
// software. This is a clock to data delay calibration so all
// data bits are delayed by the same amount.
if (DATA_IDELAY_MODE != "BYPASSED") begin
// Pipeline IDELAY control signals to ease routing
reg data_delay_stb_reg;
reg [4:0] data_delay_val_reg;
always @(posedge radio_clk)
{data_delay_stb_reg, data_delay_val_reg} <= {data_delay_stb, data_delay_val};
IDELAYE2 #(
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.IDELAY_TYPE(DATA_IDELAY_MODE=="FIXED"?"FIXED":"VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.SIGNAL_PATTERN("DATA"), // DATA, CLOCK input signal
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.IDELAY_VALUE(DATA_IDELAY_VAL), // Input delay tap setting (0-31)
.REFCLK_FREQUENCY(DATA_IDELAY_FREF) // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
) idelay_i (
.DATAIN(1'b0), // Internal delay data input
.IDATAIN(adc_data_buf[i]), // Data input from the I/O
.DATAOUT(adc_data_del[i]), // Delayed data output
.C(radio_clk), // Clock input
.LD(data_delay_stb_reg), // Load IDELAY_VALUE input
.CE(1'b0), // Active high enable increment/decrement input
.INC(1'b0), // Increment / Decrement tap delay input
.CINVCTRL(1'b0), // Dynamic clock inversion input
.CNTVALUEIN(data_delay_val_reg), // Counter value input
.CNTVALUEOUT(), // Counter value output
.LDPIPEEN(1'b0), // Enable PIPELINE register to load data input
.REGRST(1'b0) // Reset for the pipeline register.Only used in VAR_LOAD_PIPE mode.
);
end else begin
assign adc_data_del[i] = adc_data_buf[i];
end
// Use the global ADC clock to capture delayed data into an IDDR.
// Each IQ sample is transferred in QDR mode i.e. odd and even on
// a rising and falling edge of the clock
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
) iddr_i (
.C(adc_cap_clk), .CE(1'b1),
.D(adc_data_del[i]), .R(1'b0), .S(1'b0),
.Q1(adc_data_aclk[2*i]), .Q2(adc_data_aclk[(2*i)+1])
);
end endgenerate
// Transfer data from the source-synchronous ADC clock domian to the
// system synchronous radio clock domain. We assume that adc_cap_clk
// and radio_clk are generated from the same source and have the same
// frequency however, they have an unknown but constant phase offset.
// In order to cross domains, we use a simple synchronizer to avoid any
// sample-sample delay uncertainty introduced by FIFOs.
// NOTE: The path between adc_data_aclk and adc_data_rclk must be
// constrained to prevent build to build variations. Also, the
// phase of the two clocks must be aligned ensure that the data
// capture is safe
always @(posedge radio_clk)
{adc_data_rclk_sync, adc_data_rclk} <= {adc_data_rclk, adc_data_aclk};
// The synchronized output is the output of this module
assign data_out = adc_data_rclk_sync;
//-------------------------------------------------------------------
// Checkers
generate if (PATT_CHECKER == "TRUE") begin
wire checker_en_aclk;
wire [1:0] checker_locked_aclk, checker_failed_aclk;
synchronizer #(.INITIAL_VAL(1'b0)) checker_en_aclk_sync_i (
.clk(adc_cap_clk), .rst(1'b0), .in(checker_en), .out(checker_en_aclk));
synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_0_sync_i (
.clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[0]), .out(checker_locked[0]));
synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_1_sync_i (
.clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[1]), .out(checker_locked[1]));
synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_0_sync_i (
.clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[0]), .out(checker_failed[0]));
synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_1_sync_i (
.clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[1]), .out(checker_failed[1]));
cap_pattern_verifier #( // Q Channel : Synchronous to SSCLK
.WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
.RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
) aclk_q_checker_i (
.clk(adc_cap_clk), .rst(~checker_en_aclk),
.valid(1'b1), .data(~adc_data_aclk[WIDTH-1:0]),
.count(), .errors(),
.locked(checker_locked_aclk[0]), .failed(checker_failed_aclk[0])
);
cap_pattern_verifier #( // I Channel : Synchronous to SSCLK
.WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
.RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
) aclk_i_checker_i (
.clk(adc_cap_clk), .rst(~checker_en_aclk),
.valid(1'b1), .data(~adc_data_aclk[(2*WIDTH)-1:WIDTH]),
.count(), .errors(),
.locked(checker_locked_aclk[1]), .failed(checker_failed_aclk[1])
);
cap_pattern_verifier #( // Q Channel : Synchronous to Radio CLK
.WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
.RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
) rclk_q_checker_i (
.clk(radio_clk), .rst(~checker_en),
.valid(1'b1), .data(~adc_data_rclk_sync[WIDTH-1:0]),
.count(), .errors(),
.locked(checker_locked[2]), .failed(checker_failed[2])
);
cap_pattern_verifier #( // I Channel : Synchronous to Radio CLK
.WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
.RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
) rclk_i_checker_i (
.clk(radio_clk), .rst(~checker_en),
.valid(1'b1), .data(~adc_data_rclk_sync[(2*WIDTH)-1:WIDTH]),
.count(), .errors(),
.locked(checker_locked[3]), .failed(checker_failed[3])
);
end endgenerate
endmodule // capture_ddrlvds
top/x300/coregen_dsp/.gitignore
+4
View File
@@ -0,0 +1,4 @@
_xmsgs
*.log
*.ncf
top/x300/coregen_dsp/.lso
+1
View File
@@ -0,0 +1 @@
fir_compiler_v5_0
top/x300/coregen_dsp/Makefile.srcs
+17
View File
@@ -0,0 +1,17 @@
#
# Copyright 2012 Ettus Research LLC
#
##################################################
# Coregen Sources
##################################################
COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x300/coregen_dsp/, \
hbdec1.v \
hbdec1.ngc \
hbdec2.v \
hbdec2.ngc \
hbdec3.v \
hbdec3.ngc \
))
top/x300/coregen_dsp/coregen.cgp
+9
View File
@@ -0,0 +1,9 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Other
SET package = ffg900
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
top/x300/coregen_dsp/filt2.coe
+36
View File
@@ -0,0 +1,36 @@
Radix=10;
CoefData = 282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282;
top/x300/coregen_dsp/hb31.coe
+32
View File
@@ -0,0 +1,32 @@
Radix=10;
CoefData = -581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581;
top/x300/coregen_dsp/hb35.coe
+36
View File
@@ -0,0 +1,36 @@
Radix=10;
CoefData = 282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282;
top/x300/coregen_dsp/hb39.coe
+40
View File
@@ -0,0 +1,40 @@
Radix=10;
CoefData = -102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102;
top/x300/coregen_dsp/hb43.coe
+44
View File
@@ -0,0 +1,44 @@
Radix=10;
CoefData = 100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100;
top/x300/coregen_dsp/hb47.coe
+51
View File
@@ -0,0 +1,51 @@
; Generated with round((2^18-2)*halfgen_test(.21,12,1))
; 83% effective BW, 64dB to 85dB rolloff
Radix=10;
CoefData =
-62,
0,
194,
0,
-440,
0,
855,
0,
-1505,
0,
2478,
0,
-3900,
0,
5990,
0,
-9187,
0,
14632,
0,
-26536,
0,
83009,
131071,
83009,
0,
-26536,
0,
14632,
0,
-9187,
0,
5990,
0,
-3900,
0,
2478,
0,
-1505,
0,
855,
0,
-440,
0,
194,
0,
-62;
top/x300/coregen_dsp/hb51.coe
+52
View File
@@ -0,0 +1,52 @@
Radix=10;
CoefData = 300,
0,
-200,
0,
100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100,
0,
-200,
0,
300;
top/x300/coregen_dsp/hb55.coe
+56
View File
@@ -0,0 +1,56 @@
Radix=10;
CoefData = -400,
0,
300,
0,
-200,
0,
100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100,
0,
-200,
0,
300,
0,
-400;
top/x300/coregen_dsp/hb59.coe
+60
View File
@@ -0,0 +1,60 @@
Radix=10;
CoefData = 500,
0,
-400,
0,
300,
0,
-200,
0,
100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100,
0,
-200,
0,
300,
0,
-400,
0
500;
top/x300/coregen_dsp/hb63.coe
+67
View File
@@ -0,0 +1,67 @@
; Generated with round((2^18-2)*halfgen_test(.22,16,1))
; 88% effective BW, 64dB to 87dB rolloff
Radix=10;
CoefData =
-35,
0,
95,
0,
-195,
0,
352,
0,
-582,
0,
907,
0,
-1354,
0,
1953,
0,
-2751,
0,
3813,
0,
-5249,
0,
7264,
0,
-10296,
0,
15494,
0,
-27083,
0,
83196,
131071,
83196,
0,
-27083,
0,
15494,
0,
-10296,
0,
7264,
0,
-5249,
0,
3813,
0,
-2751,
0,
1953,
0,
-1354,
0,
907,
0,
-582,
0,
352,
0,
-195,
0
95,
0
-35;
top/x300/coregen_dsp/hbdec1.asy
+61
View File
@@ -0,0 +1,61 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbdec1
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[46:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[46:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbdec1.mif
+47
View File
@@ -0,0 +1,47 @@
111111111111000010
000000000000000000
000000000011000010
000000000000000000
111111111001001000
000000000000000000
000000001101010111
000000000000000000
111111101000011111
000000000000000000
000000100110101110
000000000000000000
111111000011000100
000000000000000000
000001011101100110
000000000000000000
111101110000011101
000000000000000000
000011100100101000
000000000000000000
111001100001011000
000000000000000000
010100010001000001
011111111111111111
010100010001000001
000000000000000000
111001100001011000
000000000000000000
000011100100101000
000000000000000000
111101110000011101
000000000000000000
000001011101100110
000000000000000000
111111000011000100
000000000000000000
000000100110101110
000000000000000000
111111101000011111
000000000000000000
000000001101010111
000000000000000000
111111111001001000
000000000000000000
000000000011000010
000000000000000000
111111111111000010
top/x300/coregen_dsp/hbdec1.ngc
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen_dsp/hbdec1.v
+39998
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen_dsp/hbdec1.veo
+79
View File
@@ -0,0 +1,79 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec1 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec1.v when simulating
// the core, hbdec1. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbdec1.xco
+102
View File
@@ -0,0 +1,102 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Dec 4 21:34:29 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200.0
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb47.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=7
CSET component_name=hbdec1
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=200
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: 8b63d7c7
top/x300/coregen_dsp/hbdec1COEFF_auto0_0.mif
+5
View File
@@ -0,0 +1,5 @@
111111111111000010
000000000011000010
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_1.mif
+5
View File
@@ -0,0 +1,5 @@
111111111001001000
000000001101010111
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_2.mif
+5
View File
@@ -0,0 +1,5 @@
111111101000011111
000000100110101110
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_3.mif
+5
View File
@@ -0,0 +1,5 @@
111111000011000100
000001011101100110
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_4.mif
+5
View File
@@ -0,0 +1,5 @@
111101110000011101
000011100100101000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_5.mif
+5
View File
@@ -0,0 +1,5 @@
111001100001011000
010100010001000001
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
+3
View File
@@ -0,0 +1,3 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1_flist.txt
+22
View File
@@ -0,0 +1,22 @@
# Output products list for <hbdec1>
hbdec1.asy
hbdec1.gise
hbdec1.mif
hbdec1.ngc
hbdec1.v
hbdec1.veo
hbdec1.xco
hbdec1.xise
hbdec1COEFF_auto0_0.mif
hbdec1COEFF_auto0_1.mif
hbdec1COEFF_auto0_2.mif
hbdec1COEFF_auto0_3.mif
hbdec1COEFF_auto0_4.mif
hbdec1COEFF_auto0_5.mif
hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
hbdec1_flist.txt
hbdec1_readme.txt
hbdec1_reload_addrfilt_decode_rom.mif
hbdec1_reload_order.txt
hbdec1_xmdf.tcl
hbdec1filt_decode_rom.mif
top/x300/coregen_dsp/hbdec1_readme.txt
+67
View File
@@ -0,0 +1,67 @@
The following files were generated for 'hbdec1' in directory
/home/matt/fpgadev/usrp3/top/x300/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbdec1.mif
* hbdec1_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbdec1.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbdec1.ngc
* hbdec1.v
* hbdec1.veo
* hbdec1COEFF_auto0_0.mif
* hbdec1COEFF_auto0_1.mif
* hbdec1COEFF_auto0_2.mif
* hbdec1COEFF_auto0_3.mif
* hbdec1COEFF_auto0_4.mif
* hbdec1COEFF_auto0_5.mif
* hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
* hbdec1_reload_addrfilt_decode_rom.mif
* hbdec1filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbdec1.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbdec1.asy
* hbdec1.mif
* hbdec1_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbdec1_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbdec1.gise
* hbdec1.xise
Deliver Readme:
Readme file for the IP.
* hbdec1_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbdec1_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif
+17
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@@ -0,0 +1,17 @@
00
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
top/x300/coregen_dsp/hbdec1_reload_order.txt
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Reload index 0 = Index 20
Reload index 1 = Index 22
Reload index 2 = Index 16
Reload index 3 = Index 18
Reload index 4 = Index 12
Reload index 5 = Index 14
Reload index 6 = Index 8
Reload index 7 = Index 10
Reload index 8 = Index 4
Reload index 9 = Index 6
Reload index 10 = Index 0
Reload index 11 = Index 2
Reload index 12 = Index 23
Reload index 13 = Index 0
Reload index 14 = Index 0
Reload index 15 = Index 0
Reload index 16 = Index 0
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
top/x300/coregen_dsp/hbdec1_xmdf.tcl
+111
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# The package naming convention is <core_name>_xmdf
package provide hbdec1_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbdec1_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbdec1_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1
}
# ::hbdec1_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbdec1_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbdec1filt_decode_rom.mif
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00
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
top/x300/coregen_dsp/hbdec2.asy
+61
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@@ -0,0 +1,61 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbdec2
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[46:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[46:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbdec2.mif
+47
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@@ -0,0 +1,47 @@
111111111111000010
000000000000000000
000000000011000010
000000000000000000
111111111001001000
000000000000000000
000000001101010111
000000000000000000
111111101000011111
000000000000000000
000000100110101110
000000000000000000
111111000011000100
000000000000000000
000001011101100110
000000000000000000
111101110000011101
000000000000000000
000011100100101000
000000000000000000
111001100001011000
000000000000000000
010100010001000001
011111111111111111
010100010001000001
000000000000000000
111001100001011000
000000000000000000
000011100100101000
000000000000000000
111101110000011101
000000000000000000
000001011101100110
000000000000000000
111111000011000100
000000000000000000
000000100110101110
000000000000000000
111111101000011111
000000000000000000
000000001101010111
000000000000000000
111111111001001000
000000000000000000
000000000011000010
000000000000000000
111111111111000010
top/x300/coregen_dsp/hbdec2.ngc
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top/x300/coregen_dsp/hbdec2.v
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File diff suppressed because it is too large Load Diff
top/x300/coregen_dsp/hbdec2.veo
+79
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@@ -0,0 +1,79 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec2 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec2.v when simulating
// the core, hbdec2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbdec2.xco
+102
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Dec 4 21:33:01 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb47.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=4
CSET component_name=hbdec2
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=100
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: b27c3487
top/x300/coregen_dsp/hbdec2COEFF_auto0_0.mif
+9
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@@ -0,0 +1,9 @@
111111111111000010
000000000011000010
111111111001001000
000000001101010111
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2COEFF_auto0_1.mif
+9
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@@ -0,0 +1,9 @@
111111101000011111
000000100110101110
111111000011000100
000001011101100110
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2COEFF_auto0_2.mif
+9
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@@ -0,0 +1,9 @@
111101110000011101
000011100100101000
111001100001011000
010100010001000001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
+3
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@@ -0,0 +1,3 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2_flist.txt
+19
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@@ -0,0 +1,19 @@
# Output products list for <hbdec2>
hbdec2.asy
hbdec2.gise
hbdec2.mif
hbdec2.ngc
hbdec2.v
hbdec2.veo
hbdec2.xco
hbdec2.xise
hbdec2COEFF_auto0_0.mif
hbdec2COEFF_auto0_1.mif
hbdec2COEFF_auto0_2.mif
hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
hbdec2_flist.txt
hbdec2_readme.txt
hbdec2_reload_addrfilt_decode_rom.mif
hbdec2_reload_order.txt
hbdec2_xmdf.tcl
hbdec2filt_decode_rom.mif
top/x300/coregen_dsp/hbdec2_readme.txt
+64
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@@ -0,0 +1,64 @@
The following files were generated for 'hbdec2' in directory
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbdec2.mif
* hbdec2_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbdec2.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbdec2.ngc
* hbdec2.v
* hbdec2.veo
* hbdec2COEFF_auto0_0.mif
* hbdec2COEFF_auto0_1.mif
* hbdec2COEFF_auto0_2.mif
* hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
* hbdec2_reload_addrfilt_decode_rom.mif
* hbdec2filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbdec2.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbdec2.asy
* hbdec2.mif
* hbdec2_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbdec2_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbdec2.gise
* hbdec2.xise
Deliver Readme:
Readme file for the IP.
* hbdec2_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbdec2_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif
+17
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@@ -0,0 +1,17 @@
000
100
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
top/x300/coregen_dsp/hbdec2_reload_order.txt
+25
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@@ -0,0 +1,25 @@
Reload index 0 = Index 16
Reload index 1 = Index 18
Reload index 2 = Index 20
Reload index 3 = Index 22
Reload index 4 = Index 8
Reload index 5 = Index 10
Reload index 6 = Index 12
Reload index 7 = Index 14
Reload index 8 = Index 0
Reload index 9 = Index 2
Reload index 10 = Index 4
Reload index 11 = Index 6
Reload index 12 = Index 23
Reload index 13 = Index 0
Reload index 14 = Index 0
Reload index 15 = Index 0
Reload index 16 = Index 0
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
top/x300/coregen_dsp/hbdec2_xmdf.tcl
+99
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@@ -0,0 +1,99 @@
# The package naming convention is <core_name>_xmdf
package provide hbdec2_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbdec2_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbdec2_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2
}
# ::hbdec2_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbdec2_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbdec2filt_decode_rom.mif
+17
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@@ -0,0 +1,17 @@
000
100
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
top/x300/coregen_dsp/hbdec3.asy
+61
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@@ -0,0 +1,61 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbdec3
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[47:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[47:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbdec3.mif
+63
View File
@@ -0,0 +1,63 @@
111111111111011101
000000000000000000
000000000001011111
000000000000000000
111111111100111101
000000000000000000
000000000101100000
000000000000000000
111111110110111010
000000000000000000
000000001110001011
000000000000000000
111111101010110110
000000000000000000
000000011110100001
000000000000000000
111111010101000001
000000000000000000
000000111011100101
000000000000000000
111110101101111111
000000000000000000
000001110001100000
000000000000000000
111101011111001000
000000000000000000
000011110010000110
000000000000000000
111001011000110101
000000000000000000
010100010011111100
011111111111111111
010100010011111100
000000000000000000
111001011000110101
000000000000000000
000011110010000110
000000000000000000
111101011111001000
000000000000000000
000001110001100000
000000000000000000
111110101101111111
000000000000000000
000000111011100101
000000000000000000
111111010101000001
000000000000000000
000000011110100001
000000000000000000
111111101010110110
000000000000000000
000000001110001011
000000000000000000
111111110110111010
000000000000000000
000000000101100000
000000000000000000
111111111100111101
000000000000000000
000000000001011111
000000000000000000
111111111111011101
top/x300/coregen_dsp/hbdec3.ngc
+3
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top/x300/coregen_dsp/hbdec3.v
+20014
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top/x300/coregen_dsp/hbdec3.veo
+79
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@@ -0,0 +1,79 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec3 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [47 : 0] dout_1
.dout_2(dout_2)); // output [47 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec3.v when simulating
// the core, hbdec3. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbdec3.xco
+102
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@@ -0,0 +1,102 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Dec 4 21:31:43 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb63.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=3
CSET component_name=hbdec3
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=48
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=50
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: 86e0fdc7
top/x300/coregen_dsp/hbdec3COEFF_auto0_0.mif
+17
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@@ -0,0 +1,17 @@
111111111111011101
000000000001011111
111111111100111101
000000000101100000
111111110110111010
000000001110001011
111111101010110110
000000011110100001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec3COEFF_auto0_1.mif
+17
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@@ -0,0 +1,17 @@
111111010101000001
000000111011100101
111110101101111111
000001110001100000
111101011111001000
000011110010000110
111001011000110101
010100010011111100
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
+3
View File
@@ -0,0 +1,3 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec3_flist.txt
+18
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@@ -0,0 +1,18 @@
# Output products list for <hbdec3>
hbdec3.asy
hbdec3.gise
hbdec3.mif
hbdec3.ngc
hbdec3.v
hbdec3.veo
hbdec3.xco
hbdec3.xise
hbdec3COEFF_auto0_0.mif
hbdec3COEFF_auto0_1.mif
hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
hbdec3_flist.txt
hbdec3_readme.txt
hbdec3_reload_addrfilt_decode_rom.mif
hbdec3_reload_order.txt
hbdec3_xmdf.tcl
hbdec3filt_decode_rom.mif
top/x300/coregen_dsp/hbdec3_readme.txt
+63
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@@ -0,0 +1,63 @@
The following files were generated for 'hbdec3' in directory
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbdec3.mif
* hbdec3_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbdec3.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbdec3.ngc
* hbdec3.v
* hbdec3.veo
* hbdec3COEFF_auto0_0.mif
* hbdec3COEFF_auto0_1.mif
* hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
* hbdec3_reload_addrfilt_decode_rom.mif
* hbdec3filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbdec3.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbdec3.asy
* hbdec3.mif
* hbdec3_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbdec3_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbdec3.gise
* hbdec3.xise
Deliver Readme:
Readme file for the IP.
* hbdec3_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbdec3_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbdec3_reload_addrfilt_decode_rom.mif
+17
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@@ -0,0 +1,17 @@
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
top/x300/coregen_dsp/hbdec3_reload_order.txt
+33
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@@ -0,0 +1,33 @@
Reload index 0 = Index 16
Reload index 1 = Index 18
Reload index 2 = Index 20
Reload index 3 = Index 22
Reload index 4 = Index 24
Reload index 5 = Index 26
Reload index 6 = Index 28
Reload index 7 = Index 30
Reload index 8 = Index 0
Reload index 9 = Index 2
Reload index 10 = Index 4
Reload index 11 = Index 6
Reload index 12 = Index 8
Reload index 13 = Index 10
Reload index 14 = Index 12
Reload index 15 = Index 14
Reload index 16 = Index 31
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
Reload index 24 = Index 0
Reload index 25 = Index 0
Reload index 26 = Index 0
Reload index 27 = Index 0
Reload index 28 = Index 0
Reload index 29 = Index 0
Reload index 30 = Index 0
Reload index 31 = Index 0
top/x300/coregen_dsp/hbdec3_xmdf.tcl
+95
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@@ -0,0 +1,95 @@
# The package naming convention is <core_name>_xmdf
package provide hbdec3_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbdec3_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbdec3_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec3
}
# ::hbdec3_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbdec3_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec3
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbdec3filt_decode_rom.mif
+17
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@@ -0,0 +1,17 @@
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
top/x300/dev_config.json
+3
View File
@@ -0,0 +1,3 @@
{
"warning": { "ignore": ["."]}
}
top/x300/gen_ddrlvds.v
+106
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@@ -0,0 +1,106 @@
module gen_ddrlvds
(
// 1X Radio Clock
input tx_clk_1x,
// 2X Radio clock
input tx_clk_2x,
// Clk to drive DCI ODDR. This is a phase shifted version of
// tx_clk_2x. The phase shift is to center the DCI edge in the
// valid window of the data in the DAC.
input tx_dci_clk,
// Reset signal synchronous to radio clock
input reset,
// Source synchronous differential clocks to DAC
output tx_clk_2x_p,
output tx_clk_2x_n,
// Differential frame sync to DAC
output tx_frame_p,
output tx_frame_n,
// Differential byte wide data to DAC.
// Alternates I[15:8],I[7:0],Q[15:8],Q[7:0]
output [7:0] tx_d_p,
output [7:0] tx_d_n,
// Input data
input [15:0] i,
input [15:0] q,
// Rising edge sampled on sync_dacs triggers frame sync sequence
input sync_dacs
);
reg [15:0] i_reg, q_reg;
reg [15:0] i_2x, q_2x;
reg rising_edge;
wire [15:0] i_and_q_2x;
reg sync_2x;
genvar z;
wire [7:0] tx_int;
wire tx_clk_2x_int;
wire tx_frame_int;
// Keep constraint to ensure these signals are not resource shared which can cause timing failures
(* keep = "true" *) reg phase, phase_2x, sync_dacs_reg;
wire phase_eq_phase2x = (phase == phase_2x);
always @(posedge tx_clk_1x)
if (reset)
phase <= 1'b0;
else
phase <= ~phase;
//
// Pipeline input data so that 1x to 2x clock domain jump includes no logic external to this module.
//
always @(posedge tx_clk_1x)
begin
i_reg <= i;
q_reg <= q;
sync_dacs_reg <= sync_dacs;
end
always @(posedge tx_clk_2x)
begin
// Move 1x data to 2x domain, mostly just to add pipeline regs
// for timing closure.
i_2x <= i_reg;
q_2x <= q_reg;
// Sample phase to determine when 1x clock edges occur.
// To sync multiple AD9146 DAC's an extended assertion of FRAME is required,
// when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME,
// also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for.
sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
rising_edge <= (phase_eq_phase2x && ~sync_2x);
phase_2x <= phase;
end
// Interleave I and Q as SDR signals
assign i_and_q_2x = rising_edge ? q_2x : i_2x;
generate
for(z = 0; z < 8; z = z + 1)
begin : gen_pins
OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z]));
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr
(.Q(tx_int[z]), .C(tx_clk_2x),
.CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0));
end
endgenerate
// Generate framing signal to identify I and Q
OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n));
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame
(.Q(tx_frame_int), .C(tx_clk_2x),
.CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0));
// Source synchronous clk
OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n));
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk
(.Q(tx_clk_2x_int), .C(tx_dci_clk),
.CE(1'b1), .D1(1'b1), .D2(1'b0), .S(1'b0), .R(1'b0));
endmodule // gen_ddrlvds
top/x300/ip/Makefile.inc
+81
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@@ -0,0 +1,81 @@
#
# Copyright 2014 Ettus Research
#
include $(IP_DIR)/axi4_dualport_sram/Makefile.inc
include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc
include $(IP_DIR)/axi_intercon_2x64_128_bd/Makefile.inc
include $(IP_DIR)/bootram/Makefile.inc
include $(IP_DIR)/bus_clk_gen/Makefile.inc
include $(IP_DIR)/ddr3_32bit/Makefile.inc
include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
include $(IP_DIR)/fifo_short_2clk/Makefile.inc
include $(IP_DIR)/input_sample_fifo/Makefile.inc
include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc
include $(IP_DIR)/pcie_clk_gen/Makefile.inc
include $(IP_DIR)/radio_clk_gen/Makefile.inc
include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc
include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc
IP_XCI_SRCS = \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
$(IP_AXI64_8K_2CLK_FIFO_SRCS) \
$(IP_BOOTRAM_SRCS) \
$(IP_BUS_CLK_GEN_SRCS) \
$(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_PCIE_CLK_GEN_SRCS) \
$(IP_RADIO_CLK_GEN_SRCS)
# $(IP_AXI4_BRAM_SRCS) \
BD_SRCS = \
$(IP_AXI_INTERCON_2X64_128_BD_SRCS)
IP_ONE_GIGE_PHY_XCI_SRCS = \
$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \
IP_TEN_GIGE_PHY_XCI_SRCS = \
$(IP_TEN_GIG_ETH_PCS_PMA_SRCS)
IP_AURORA_XCI_SRCS = \
$(IP_AURORA_64B66B_PCS_PMA_SRCS)
IP_DRAM_XCI_SRCS = \
$(IP_DDR3_32BIT_SRCS)
# Currently unused
# $(IP_INPUT_SAMPLE_FIFO_SRCS) \
# $(IP_AXI_INTERCON_4X64_128_SRCS) \
# $(IP_AXI_INTERCON_2X64_128_SRCS) \
IP_CODEGEN_SRCS = \
$(ONE_GIGE_PHY_SRCS) \
$(TEN_GIGE_PHY_SRCS)
IP_SYNTH_OUTPUTS = \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
$(IP_AXI64_8K_2CLK_FIFO_OUTS) \
$(IP_BOOTRAM_OUTS) \
$(IP_BUS_CLK_GEN_OUTS) \
$(IP_FIFO_4K_2CLK_OUTS) \
$(IP_FIFO_SHORT_2CLK_OUTS) \
$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \
$(IP_PCIE_CLK_GEN_OUTS) \
$(IP_RADIO_CLK_GEN_OUTS) \
$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \
$(IP_AURORA_64B66B_PCS_PMA_OUTS)
# $(IP_AXI4_BRAM_OUTS) \
BD_OUTPUTS = \
$(IP_AXI_INTERCON_2X64_128_BD_OUTS)
# Currently unused
# $(IP_INPUT_SAMPLE_FIFO_OUTS) \
# $(IP_AXI_INTERCON_4X64_128_OUTS) \
# $(IP_AXI_INTERCON_2X64_128_OUTS) \
ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS)
.PHONY: ip
top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc
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#
# Copyright 2016 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \
aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \
aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \
aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \
aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \
imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \
imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \
imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \
imports/aurora_64b66b_pcs_pma_exdes.v \
imports/aurora_64b66b_pcs_pma_exdes.xdc \
imports/aurora_64b66b_pcs_pma_frame_check.v \
imports/aurora_64b66b_pcs_pma_frame_gen.v \
)
AURORA_PHY_SRCS = \
$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \
$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v \
$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \
$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS)
IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \
aurora_64b66b_pcs_pma.xci.out \
)
$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
$(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
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top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v
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//
// Copyright 2016 Ettus Research LLC
//
module aurora_axis_mac #(
parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"}
parameter PACKET_MODE = 0,
parameter MAX_PACKET_SIZE = 512,
parameter BIST_ENABLED = 1
) (
// Clocks and resets
input phy_clk,
input phy_rst,
input sys_clk,
input sys_rst,
input clear,
// PHY TX Interface (Synchronous to phy_clk)
output [63:0] phy_m_axis_tdata,
output phy_m_axis_tvalid,
input phy_m_axis_tready,
// PHY RX Interface (Synchronous to phy_clk)
input [63:0] phy_s_axis_tdata,
input phy_s_axis_tvalid,
// User TX Interface (Synchronous to sys_clk)
input [63:0] s_axis_tdata,
input s_axis_tlast,
input s_axis_tvalid,
output s_axis_tready,
// User RX Interface (Synchronous to sys_clk)
output [63:0] m_axis_tdata,
output m_axis_tlast,
output m_axis_tvalid,
input m_axis_tready,
// PHY Status Inputs (Synchronous to phy_clk)
input channel_up,
input hard_err,
input soft_err,
// Status and Error Outputs (Synchronous to sys_clk)
output [31:0] overruns,
output [31:0] soft_errors,
output reg [31:0] checksum_errors,
output critical_err,
// BIST Interface (Synchronous to sys_clk)
input bist_gen_en,
input [5:0] bist_gen_rate,
input bist_checker_en,
input bist_loopback_en,
output reg bist_checker_locked,
output reg [47:0] bist_checker_samps,
output reg [47:0] bist_checker_errors
);
// ----------------------------------------------
// Resets, Clears, Clock crossings
// ----------------------------------------------
wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal.
// Stay idle if the PHY is not up or if it experiences a fatal error
wire clear_sysclk, clear_phyclk;
synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i (
.clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk));
synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i (
.clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk));
// ----------------------------------------------
// Counters
// ----------------------------------------------
reg [31:0] overruns_reg;
reg [31:0] soft_errors_reg;
// Counter for recoverable errors. For reporting only.
always @(posedge phy_clk)
if (phy_rst | clear_phyclk)
soft_errors_reg <= 32'd0;
else if (soft_err)
soft_errors_reg <= soft_errors_reg + 32'd1;
// Tag an overrun if the FIFO is full. Samples will get dropped
always @(posedge phy_clk)
if (phy_rst | clear_phyclk)
overruns_reg <= 32'd0;
else if (phy_s_axis_tvalid & ~phy_s_axis_tready)
overruns_reg <= overruns_reg + 32'd1;
wire [7:0] dummy0;
fifo_short_2clk status_counters_2clk_i (
.rst(phy_rst),
.wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(),
.rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count()
);
// ----------------------------------------------
// BIST Wires
// ----------------------------------------------
wire [63:0] bist_o_tdata;
wire bist_o_tvalid, bist_o_tready;
wire [63:0] bist_i_tdata;
wire bist_i_tvalid, bist_i_tready;
wire [63:0] loopback_tdata;
wire loopback_tvalid, loopback_tready;
reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0;
reg [5:0] bist_gen_rate_reg = 'd0;
generate if (BIST_ENABLED == 1) begin
// Pipeline control signals
always @(posedge sys_clk) begin
if (sys_rst | clear_sysclk) begin
bist_gen_en_reg <= 1'b0;
bist_checker_en_reg <= 1'b0;
bist_loopback_en_reg <= 1'b0;
bist_gen_rate_reg <= 'd0;
end else begin
bist_gen_en_reg <= bist_gen_en;
bist_checker_en_reg <= bist_checker_en;
bist_loopback_en_reg <= bist_loopback_en;
bist_gen_rate_reg <= bist_gen_rate;
end
end
end endgenerate
// ----------------------------------------------
// RX Data Path
// ----------------------------------------------
wire [63:0] i_raw_tdata;
wire i_raw_tvalid, i_raw_tready;
wire [63:0] i_pip_tdata;
wire i_pip_tvalid, i_pip_tready;
wire [63:0] i_pkt_tdata;
wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready;
wire [63:0] i_gt_tdata;
wire i_gt_tlast, i_gt_tvalid, i_gt_tready;
wire checksum_err;
wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian;
generate if (PHY_ENDIANNESS == "BIG") begin
assign phy_s_axis_tdata_endian = {
phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24],
phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56]
};
assign phy_m_axis_tdata = {
phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24],
phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56]
};
end else begin
assign phy_s_axis_tdata_endian = phy_s_axis_tdata;
assign phy_m_axis_tdata = phy_m_axis_tdata_endian;
end endgenerate
// Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx.
axi64_4k_2clk_fifo ingress_fifo_i (
.s_aresetn(~phy_rst), .s_aclk(phy_clk),
.s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0),
.s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(),
.m_aclk(sys_clk),
.m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(),
.m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count()
);
// AXI-Flop to ease timing
axi_fifo_flop2 #(.WIDTH(64)) input_pipe_i0 (
.clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
.i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready),
.o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid),
.o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)),
.space(), .occupied()
);
assign bist_i_tdata = i_pip_tdata;
assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg;
assign loopback_tdata = i_pip_tdata;
assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg;
axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i (
.clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
.i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready),
.o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready),
.crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err)
);
axi_fifo_flop2 #(.WIDTH(65)) input_pipe_i1 (
.clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
.i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready),
.o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
.space(), .occupied()
);
always @(posedge sys_clk)
if (sys_rst | clear_sysclk)
checksum_errors <= 32'd0;
else if (checksum_err)
checksum_errors <= checksum_errors + 32'd1;
// ----------------------------------------------
// TX Data Path
// ----------------------------------------------
wire [63:0] o_pkt_tdata;
wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready;
wire [63:0] o_pip_tdata;
wire o_pip_tvalid, o_pip_tready;
wire [63:0] o_raw_tdata;
wire o_raw_tvalid, o_raw_tready;
// AXI-Flop to ease timing
axi_fifo_flop2 #(.WIDTH(65)) output_pipe_i0 (
.clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
.i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
.o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready),
.space(), .occupied()
);
// Insert preamble and EOP
axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i (
.clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
.i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready),
.o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg)
);
// AXI-Flop to ease timing
axi_fifo_flop2 #(.WIDTH(64)) output_pipe_i1 (
.clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
.i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)),
.i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)),
.i_tready(o_pip_tready),
.o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready),
.space(), .occupied()
);
assign bist_o_tready = o_pip_tready;
assign loopback_tready = o_pip_tready;
// Egress FIFO
axi64_4k_2clk_fifo egress_fifo_i (
.s_aresetn(~phy_rst), .s_aclk(sys_clk),
.s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0),
.s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(),
.m_aclk(phy_clk),
.m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(),
.m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count()
);
// -------------------------------------------------
// BIST: Generator and checker for a LFSR polynomial
// -------------------------------------------------
localparam LFSR_LEN = 32;
localparam LFSR_SEED = {LFSR_LEN{1'b1}};
function [LFSR_LEN-1:0] compute_lfsr_next;
input [LFSR_LEN-1:0] current;
// Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1
compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]};
endfunction
function [63:0] lfsr_to_axis;
input [LFSR_LEN-1:0] lfsr;
lfsr_to_axis = {~lfsr, lfsr};
endfunction
function [LFSR_LEN-1:0] axis_to_lfsr;
input [63:0] axis;
axis_to_lfsr = axis[LFSR_LEN-1:0];
endfunction
generate if (BIST_ENABLED == 1) begin
// Throttle outgoing LFSR to based on the specified rate
// BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64
reg [5:0] throttle_cnt;
always @(posedge sys_clk) begin
if (sys_rst | clear_sysclk)
throttle_cnt <= 6'd0;
else if (bist_gen_en_reg)
throttle_cnt <= throttle_cnt + 6'd1;
end
// NOTE: This techinically violates AXIS spec (valid revocation)
assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg);
// Unsynchronized LFSR generator (for BIST output)
reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED;
always @(posedge sys_clk) begin
if (sys_rst | clear_sysclk | ~bist_gen_en_reg)
lfsr_gen <= LFSR_SEED;
else if (bist_o_tready & bist_o_tvalid)
lfsr_gen <= compute_lfsr_next(lfsr_gen);
end
assign bist_o_tdata = lfsr_to_axis(lfsr_gen);
// Synchronized LFSR checker (for BIST input)
wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);;
always @(posedge sys_clk) begin
if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin
bist_checker_locked <= 1'b0;
lfsr_check <= LFSR_SEED;
end else if (bist_i_tvalid && bist_i_tready) begin
lfsr_check <= axis_to_lfsr(bist_i_tdata);
if (bist_i_tdata == lfsr_to_axis(LFSR_SEED))
bist_checker_locked <= 1'b1;
end
end
// LFSR checker
always @(posedge sys_clk) begin
if (bist_checker_locked) begin
if (bist_i_tvalid & bist_i_tready) begin
bist_checker_samps <= bist_checker_samps + 48'd1;
if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin
bist_checker_errors <= bist_checker_errors + 48'd1;
end
end
end else begin
bist_checker_samps <= 48'd0;
bist_checker_errors <= 48'd0;
end
end
assign bist_i_tready = 1'b1;
end endgenerate
endmodule
top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v
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//
// Copyright 2016 Ettus Research LLC
//
module aurora_phy_clk_gen
(
input areset,
input refclk_p,
input refclk_n,
output refclk,
output clk156,
output init_clk
);
wire clk156_buf;
wire init_clk_buf;
wire clkfbout;
IBUFDS_GTE2 ibufds_inst (
.O (refclk),
.ODIV2 (),
.CEB (1'b0),
.I (refclk_p),
.IB (refclk_n)
);
BUFG clk156_bufg_inst (
.I (refclk),
.O (clk156)
);
// Divding independent clock by 2 as source for DRP clock
BUFR # (
.BUFR_DIVIDE ("2")
) dclk_divide_by_2_buf (
.I (clk156),
.O (init_clk_buf),
.CE (1'b1),
.CLR (1'b0)
);
BUFG dclk_bufg_i (
.I (init_clk_buf),
.O (init_clk)
);
endmodule
top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v
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//
// Copyright 2016 Ettus Research LLC
//
module aurora_phy_x1 #(
parameter SIMULATION = 0
)(
// Clocks and Resets
input areset,
input refclk,
input init_clk,
output user_clk,
output user_rst,
// GTX Serial I/O
input rx_p,
input rx_n,
output tx_p,
output tx_n,
// AXI4-Stream TX Interface
input [63:0] s_axis_tdata,
input s_axis_tvalid,
output s_axis_tready,
// AXI4-Stream RX Interface
output [63:0] m_axis_tdata,
output m_axis_tvalid,
// AXI4-Lite Config Interface
input [31:0] s_axi_awaddr,
input [31:0] s_axi_araddr,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_awvalid,
input s_axi_rready,
output [31:0] s_axi_rdata,
output s_axi_awready,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
output [1:0] s_axi_rresp,
input s_axi_bready,
output s_axi_arready,
output s_axi_rvalid,
input s_axi_arvalid,
input s_axi_wvalid,
// Status and Error Reporting Interface
output reg channel_up,
output reg hard_err,
output reg soft_err
);
//--------------------------------------------------------------
// Status and Error Signals
//--------------------------------------------------------------
wire hard_err_i, soft_err_i, channel_up_i, lane_up_i;
always @(posedge user_clk) begin
hard_err <= hard_err_i;
soft_err <= soft_err_i;
channel_up <= channel_up_i && lane_up_i;
end
//--------------------------------------------------------------
// Reset and PMA Init Sequence
//--------------------------------------------------------------
// Requirements from PG074:
// - It is expected that user_clock is stable when the reset_pb signal is applied.
// - During the board power-on sequence, both the pma_init and reset_pb signals are
// expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during
// power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are
// stable, pma_init is deasserted followed by the deassertion of reset_pb.
// - Normal Operation Reset Sequence:
// 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period.
// 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent
// the transmission of CC characters and ensure that the remote agent detects a hot plug event.
// 3. Deassert pma_init.
// 4. Deassert reset_pb.
localparam PWRON_PMA_INIT_CYC = 32'd1024;
localparam SYSRST_ASSERT_CYC = 32'd128;
localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26;
localparam SYSRST_DEASSERT_CYC = 32'd20;
wire reset_iclk, pma_init, reset_pb;
wire gt_pll_lock, gt_pll_lock_iclk, mmcm_locked, mmcm_locked_iclk;
synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i (
.clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk)
);
synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i (
.clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk)
);
synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i (
.clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk)
);
localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0;
localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1;
localparam [2:0] RST_ST_IDLE = 3'd2;
localparam [2:0] RST_ST_SYSRST_PRE = 3'd3;
localparam [2:0] RST_ST_PMA_INIT = 3'd4;
localparam [2:0] RST_ST_SYSRST_POST = 3'd5;
reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT;
reg [31:0] rst_counter = PWRON_PMA_INIT_CYC;
always @(posedge init_clk) begin
case (rst_state)
RST_ST_PWRON_PMA_INIT: begin
if (rst_counter == 32'd0) begin
rst_state <= RST_ST_PWRON_PMA_SYSRST;
rst_counter <= SYSRST_DEASSERT_CYC;
end else begin
rst_counter <= rst_counter - 32'd1;
end
end
RST_ST_PWRON_PMA_SYSRST: begin
if (rst_counter == 32'd0) begin
rst_state <= RST_ST_IDLE;
end else begin
rst_counter <= rst_counter - 32'd1;
end
end
RST_ST_IDLE: begin
if (reset_iclk) begin
rst_state <= RST_ST_SYSRST_PRE;
rst_counter <= SYSRST_ASSERT_CYC;
end
end
RST_ST_SYSRST_PRE: begin
if (rst_counter == 32'd0) begin
rst_state <= RST_ST_PMA_INIT;
rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}};
end else if (mmcm_locked_iclk) begin
rst_counter <= rst_counter - 32'd1;
end
end
RST_ST_PMA_INIT: begin
if (rst_counter == 32'd0) begin
rst_state <= RST_ST_SYSRST_POST;
rst_counter <= SYSRST_DEASSERT_CYC;
end else begin
rst_counter <= rst_counter - 32'd1;
end
end
RST_ST_SYSRST_POST: begin
if (rst_counter == 32'd0) begin
rst_state <= RST_ST_IDLE;
end else begin
rst_counter <= rst_counter - 32'd1;
end
end
endcase
end
assign reset_pb = (rst_state != RST_ST_IDLE);
assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT);
//--------------------------------------------------------------
// Clocking
//--------------------------------------------------------------
wire tx_out_clk, tx_out_clk_bufg;
wire sync_clk_i;
wire user_clk_i;
wire mmcm_fb_clk;
wire sync_clk;
localparam MULT = 10;
localparam DIVIDE = 5;
localparam CLK_PERIOD = 3.103;
localparam OUT0_DIVIDE = 4;
localparam OUT1_DIVIDE = 2;
localparam OUT2_DIVIDE = 6;
localparam OUT3_DIVIDE = 8;
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVIDE),
.CLKFBOUT_MULT_F (MULT),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (OUT0_DIVIDE),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLK_PERIOD),
.CLKOUT1_DIVIDE (OUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (OUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (OUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.REF_JITTER1 (0.010)
) mmcm_adv_inst (
.CLKFBOUT (mmcm_fb_clk),
.CLKFBOUTB (),
.CLKOUT0 (user_clk_i),
.CLKOUT0B (),
.CLKOUT1 (sync_clk_i),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (mmcm_fb_clk),
.CLKIN1 (tx_out_clk_bufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (mmcm_locked),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (!gt_pll_lock)
);
// BUFG for the feedback clock. The feedback signal is phase aligned to the input
// and must come from the CLK0 or CLK2X output of the PLL. In this case, we use
// the CLK0 output.
BUFG txout_clock_net_i (
.I(tx_out_clk),
.O(tx_out_clk_bufg)
);
BUFG user_clk_net_i (
.I(user_clk_i),
.O(user_clk)
);
BUFG sync_clock_net_i (
.I(sync_clk_i),
.O(sync_clk)
);
//--------------------------------------------------------------
// GT Common
//--------------------------------------------------------------
wire gt_qpllclk_quad1_i;
wire gt_qpllrefclk_quad1_i;
wire gt_to_common_qpllreset_i;
wire gt_qpllrefclklost_i;
wire gt_qplllock_i;
wire [7:0] qpll_drpaddr_in_i = 8'h0;
wire [15:0] qpll_drpdi_in_i = 16'h0;
wire qpll_drpen_in_i = 1'b0;
wire qpll_drpwe_in_i = 1'b0;
wire [15:0] qpll_drpdo_out_i;
wire qpll_drprdy_out_i;
aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support (
.gt_qpllclk_quad1_out (gt_qpllclk_quad1_i),
.gt_qpllrefclk_quad1_out (gt_qpllrefclk_quad1_i),
.GT0_GTREFCLK0_COMMON_IN (refclk),
//----------------------- Common Block - QPLL Ports ------------------------
.GT0_QPLLLOCK_OUT (gt_qplllock_i),
.GT0_QPLLRESET_IN (gt_to_common_qpllreset_i),
.GT0_QPLLLOCKDETCLK_IN (init_clk),
.GT0_QPLLREFCLKLOST_OUT (gt_qpllrefclklost_i),
//---------------------- Common DRP Ports ----------------------
.qpll_drpaddr_in (qpll_drpaddr_in_i),
.qpll_drpdi_in (qpll_drpdi_in_i),
.qpll_drpclk_in (init_clk),
.qpll_drpdo_out (qpll_drpdo_out_i),
.qpll_drprdy_out (qpll_drprdy_out_i),
.qpll_drpen_in (qpll_drpen_in_i),
.qpll_drpwe_in (qpll_drpwe_in_i)
);
//--------------------------------------------------------------
// IP Instantiation
//--------------------------------------------------------------
wire gt_rxcdrovrden_i = 1'b0;
wire [2:0] loopback_i = 3'b000;
wire power_down_i = 1'b0;
aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i (
.refclk1_in (refclk),
// TX AXI4-S Interface
.s_axi_tx_tdata (s_axis_tdata),
.s_axi_tx_tvalid (s_axis_tvalid),
.s_axi_tx_tready (s_axis_tready),
// RX AXI4-S Interface
.m_axi_rx_tdata (m_axis_tdata),
.m_axi_rx_tvalid (m_axis_tvalid),
// GTX Serial I/O
.rxp (rx_p),
.rxn (rx_n),
.txp (tx_p),
.txn (tx_n),
// Status and Error
.hard_err (hard_err_i),
.soft_err (soft_err_i),
.channel_up (channel_up_i),
.lane_up (lane_up_i),
// System Interface
.mmcm_not_locked (!mmcm_locked),
.user_clk (user_clk),
.sync_clk (sync_clk),
.reset_pb (reset_pb),
.gt_rxcdrovrden_in (gt_rxcdrovrden_i),
.power_down (power_down_i),
.loopback (loopback_i),
.pma_init (pma_init),
.gt_pll_lock (gt_pll_lock),
.drp_clk_in (init_clk),
.gt_qpllclk_quad1_in (gt_qpllclk_quad1_i),
.gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i),
.gt_to_common_qpllreset_out(gt_to_common_qpllreset_i),
.gt_qplllock_in (gt_qplllock_i),
.gt_qpllrefclklost_in (gt_qpllrefclklost_i),
// AXI4-Lite config
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rready (s_axi_rready),
// GTXE2 COMMON DRP Ports
.qpll_drpaddr_in (qpll_drpaddr_in_i),
.qpll_drpdi_in (qpll_drpdi_in_i),
.qpll_drpdo_out (),
.qpll_drprdy_out (),
.qpll_drpen_in (qpll_drpen_in_i),
.qpll_drpwe_in (qpll_drpwe_in_i),
.init_clk (init_clk),
.link_reset_out (),
.sys_reset_out (user_rst),
.tx_out_clk (tx_out_clk)
);
endmodule
top/x300/ip/axi4_dualport_sram/Makefile.inc
+15
View File
@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI4_BRAM_SRCS = $(IP_BUILD_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci
IP_AXI4_BRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_dualport_sram/, \
axi4_dualport_sram.xci.out \
synth/axi4_dualport_sram.vhd \
)
$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS) : $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci
$(call BUILD_VIVADO_IP,axi4_dualport_sram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci
+314
View File
@@ -0,0 +1,314 @@
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi4_dualport_sram</spirit:instanceName>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_AXI_ID" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_RSTB_Pin" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc
+15
View File
@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \
axi64_4k_2clk_fifo.xci.out \
synth/axi64_4k_2clk_fifo.vhd \
)
$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
$(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
+584
View File
@@ -0,0 +1,584 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi64_4k_2clk_fifo</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">69</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
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</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc
+15
View File
@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \
axi64_8k_2clk_fifo.xci.out \
synth/axi64_8k_2clk_fifo.vhd \
)
$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
$(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
+582
View File
@@ -0,0 +1,582 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi64_8k_2clk_fifo</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Independent_Clock</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi64_8k_2clk_fifo</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1021</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1021</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1021</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">AXI_STREAM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc
+19
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#
# Copyright 2016 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTERCON_2X64_128_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd \
$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml \
$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v
BD_AXI_INTERCON_2X64_128_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/, \
axi_intercon_2x64_128_bd.bd.out \
axi_intercon_2x64_128_bd_ooc.xdc \
)
# The cp below is a workaround for a Vivado issue where it is pulling in wrong sources
$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd
$(call BUILD_VIVADO_BD,axi_intercon_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
cp -f $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/synth/axi_intercon_2x64_128_bd.v $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/hdl/axi_intercon_2x64_128_bd.v
top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd
Executable
+1326
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File diff suppressed because it is too large Load Diff
top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml
Executable
+132
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@@ -0,0 +1,132 @@
<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="axi_intercon_2x64_128_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1513970884"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1513970884"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1513970884"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="hdl/axi_intercon_2x64_128_bd.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="axi_intercon_2x64_128_bd_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
</File>
<File Name="hw_handoff/axi_intercon_2x64_128_bd.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
</File>
<File Name="hw_handoff/axi_intercon_2x64_128_bd_bd.tcl">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
</File>
<File Name="hdl/axi_intercon_2x64_128_bd.hwdef">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s00_width_conv_0/axi_intercon_2x64_128_bd_s00_width_conv_0.xci" Type="IP">
<Instance HierarchyPath="s00_width_conv"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s01_width_conv_0/axi_intercon_2x64_128_bd_s01_width_conv_0.xci" Type="IP">
<Instance HierarchyPath="s01_width_conv"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_xbar_0/axi_intercon_2x64_128_bd_xbar_0.xci" Type="IP">
<Instance HierarchyPath="xbar"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_m00_rs_0/axi_intercon_2x64_128_bd_m00_rs_0.xci" Type="IP">
<Instance HierarchyPath="m00_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s01_rs_0_0/axi_intercon_2x64_128_bd_s01_rs_0_0.xci" Type="IP">
<Instance HierarchyPath="s01_rs_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s00_rs_0_0/axi_intercon_2x64_128_bd_s00_rs_0_0.xci" Type="IP">
<Instance HierarchyPath="s00_rs_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s00_cc_0/axi_intercon_2x64_128_bd_s00_cc_0.xci" Type="IP">
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s01_cc_0/axi_intercon_2x64_128_bd_s01_cc_0.xci" Type="IP">
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s00_rs_2_0/axi_intercon_2x64_128_bd_s00_rs_2_0.xci" Type="IP">
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s01_rs_2_0/axi_intercon_2x64_128_bd_s01_rs_2_0.xci" Type="IP">
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s00_rs_1_0/axi_intercon_2x64_128_bd_s00_rs_1_0.xci" Type="IP">
<Instance HierarchyPath="s00_rs_1"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_128_bd_s01_rs_1_0/axi_intercon_2x64_128_bd_s01_rs_1_0.xci" Type="IP">
<Instance HierarchyPath="s01_rs_1"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v
+508
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@@ -0,0 +1,508 @@
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
//Date : Mon Oct 24 19:58:35 2016
//Host : ubuntu-VM running 64-bit Ubuntu 14.04.5 LTS
//Command : generate_target axi_intercon_2x64_128_bd_wrapper.bd
//Design : axi_intercon_2x64_128_bd_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module axi_intercon_2x64_128_bd_wrapper
(M00_AXI_ACLK,
M00_AXI_ARESETN,
M00_AXI_ARADDR,
M00_AXI_ARBURST,
M00_AXI_ARCACHE,
M00_AXI_ARID,
M00_AXI_ARLEN,
M00_AXI_ARLOCK,
M00_AXI_ARPROT,
M00_AXI_ARQOS,
M00_AXI_ARREADY,
M00_AXI_ARREGION,
M00_AXI_ARSIZE,
M00_AXI_ARVALID,
M00_AXI_AWADDR,
M00_AXI_AWBURST,
M00_AXI_AWCACHE,
M00_AXI_AWID,
M00_AXI_AWLEN,
M00_AXI_AWLOCK,
M00_AXI_AWPROT,
M00_AXI_AWQOS,
M00_AXI_AWREADY,
M00_AXI_AWREGION,
M00_AXI_AWSIZE,
M00_AXI_AWVALID,
M00_AXI_BID,
M00_AXI_BREADY,
M00_AXI_BRESP,
M00_AXI_BVALID,
M00_AXI_RDATA,
M00_AXI_RID,
M00_AXI_RLAST,
M00_AXI_RREADY,
M00_AXI_RRESP,
M00_AXI_RVALID,
M00_AXI_WDATA,
M00_AXI_WLAST,
M00_AXI_WREADY,
M00_AXI_WSTRB,
M00_AXI_WVALID,
S00_AXI_ACLK,
S00_AXI_ARESETN,
S00_AXI_ARADDR,
S00_AXI_ARBURST,
S00_AXI_ARCACHE,
S00_AXI_ARID,
S00_AXI_ARLEN,
S00_AXI_ARLOCK,
S00_AXI_ARPROT,
S00_AXI_ARQOS,
S00_AXI_ARREADY,
S00_AXI_ARREGION,
S00_AXI_ARSIZE,
S00_AXI_ARVALID,
S00_AXI_AWADDR,
S00_AXI_AWBURST,
S00_AXI_AWCACHE,
S00_AXI_AWID,
S00_AXI_AWLEN,
S00_AXI_AWLOCK,
S00_AXI_AWPROT,
S00_AXI_AWQOS,
S00_AXI_AWREADY,
S00_AXI_AWREGION,
S00_AXI_AWSIZE,
S00_AXI_AWVALID,
S00_AXI_BID,
S00_AXI_BREADY,
S00_AXI_BRESP,
S00_AXI_BVALID,
S00_AXI_RDATA,
S00_AXI_RID,
S00_AXI_RLAST,
S00_AXI_RREADY,
S00_AXI_RRESP,
S00_AXI_RVALID,
S00_AXI_WDATA,
S00_AXI_WLAST,
S00_AXI_WREADY,
S00_AXI_WSTRB,
S00_AXI_WVALID,
S01_AXI_ACLK,
S01_AXI_ARESETN,
S01_AXI_ARADDR,
S01_AXI_ARBURST,
S01_AXI_ARCACHE,
S01_AXI_ARID,
S01_AXI_ARLEN,
S01_AXI_ARLOCK,
S01_AXI_ARPROT,
S01_AXI_ARQOS,
S01_AXI_ARREADY,
S01_AXI_ARREGION,
S01_AXI_ARSIZE,
S01_AXI_ARVALID,
S01_AXI_AWADDR,
S01_AXI_AWBURST,
S01_AXI_AWCACHE,
S01_AXI_AWID,
S01_AXI_AWLEN,
S01_AXI_AWLOCK,
S01_AXI_AWPROT,
S01_AXI_AWQOS,
S01_AXI_AWREADY,
S01_AXI_AWREGION,
S01_AXI_AWSIZE,
S01_AXI_AWVALID,
S01_AXI_BID,
S01_AXI_BREADY,
S01_AXI_BRESP,
S01_AXI_BVALID,
S01_AXI_RDATA,
S01_AXI_RID,
S01_AXI_RLAST,
S01_AXI_RREADY,
S01_AXI_RRESP,
S01_AXI_RVALID,
S01_AXI_WDATA,
S01_AXI_WLAST,
S01_AXI_WREADY,
S01_AXI_WSTRB,
S01_AXI_WVALID);
input M00_AXI_ACLK;
input M00_AXI_ARESETN;
output [31:0]M00_AXI_ARADDR;
output [1:0]M00_AXI_ARBURST;
output [3:0]M00_AXI_ARCACHE;
output [0:0]M00_AXI_ARID;
output [7:0]M00_AXI_ARLEN;
output [0:0]M00_AXI_ARLOCK;
output [2:0]M00_AXI_ARPROT;
output [3:0]M00_AXI_ARQOS;
input M00_AXI_ARREADY;
output [3:0]M00_AXI_ARREGION;
output [2:0]M00_AXI_ARSIZE;
output M00_AXI_ARVALID;
output [31:0]M00_AXI_AWADDR;
output [1:0]M00_AXI_AWBURST;
output [3:0]M00_AXI_AWCACHE;
output [0:0]M00_AXI_AWID;
output [7:0]M00_AXI_AWLEN;
output [0:0]M00_AXI_AWLOCK;
output [2:0]M00_AXI_AWPROT;
output [3:0]M00_AXI_AWQOS;
input M00_AXI_AWREADY;
output [3:0]M00_AXI_AWREGION;
output [2:0]M00_AXI_AWSIZE;
output M00_AXI_AWVALID;
input [0:0]M00_AXI_BID;
output M00_AXI_BREADY;
input [1:0]M00_AXI_BRESP;
input M00_AXI_BVALID;
input [255:0]M00_AXI_RDATA;
input [0:0]M00_AXI_RID;
input M00_AXI_RLAST;
output M00_AXI_RREADY;
input [1:0]M00_AXI_RRESP;
input M00_AXI_RVALID;
output [255:0]M00_AXI_WDATA;
output M00_AXI_WLAST;
input M00_AXI_WREADY;
output [31:0]M00_AXI_WSTRB;
output M00_AXI_WVALID;
input S00_AXI_ACLK;
input S00_AXI_ARESETN;
input [31:0]S00_AXI_ARADDR;
input [1:0]S00_AXI_ARBURST;
input [3:0]S00_AXI_ARCACHE;
input [0:0]S00_AXI_ARID;
input [7:0]S00_AXI_ARLEN;
input [0:0]S00_AXI_ARLOCK;
input [2:0]S00_AXI_ARPROT;
input [3:0]S00_AXI_ARQOS;
output S00_AXI_ARREADY;
input [3:0]S00_AXI_ARREGION;
input [2:0]S00_AXI_ARSIZE;
input S00_AXI_ARVALID;
input [31:0]S00_AXI_AWADDR;
input [1:0]S00_AXI_AWBURST;
input [3:0]S00_AXI_AWCACHE;
input [0:0]S00_AXI_AWID;
input [7:0]S00_AXI_AWLEN;
input [0:0]S00_AXI_AWLOCK;
input [2:0]S00_AXI_AWPROT;
input [3:0]S00_AXI_AWQOS;
output S00_AXI_AWREADY;
input [3:0]S00_AXI_AWREGION;
input [2:0]S00_AXI_AWSIZE;
input S00_AXI_AWVALID;
output [0:0]S00_AXI_BID;
input S00_AXI_BREADY;
output [1:0]S00_AXI_BRESP;
output S00_AXI_BVALID;
output [63:0]S00_AXI_RDATA;
output [0:0]S00_AXI_RID;
output S00_AXI_RLAST;
input S00_AXI_RREADY;
output [1:0]S00_AXI_RRESP;
output S00_AXI_RVALID;
input [63:0]S00_AXI_WDATA;
input S00_AXI_WLAST;
output S00_AXI_WREADY;
input [7:0]S00_AXI_WSTRB;
input S00_AXI_WVALID;
input S01_AXI_ACLK;
input S01_AXI_ARESETN;
input [31:0]S01_AXI_ARADDR;
input [1:0]S01_AXI_ARBURST;
input [3:0]S01_AXI_ARCACHE;
input [0:0]S01_AXI_ARID;
input [7:0]S01_AXI_ARLEN;
input [0:0]S01_AXI_ARLOCK;
input [2:0]S01_AXI_ARPROT;
input [3:0]S01_AXI_ARQOS;
output S01_AXI_ARREADY;
input [3:0]S01_AXI_ARREGION;
input [2:0]S01_AXI_ARSIZE;
input S01_AXI_ARVALID;
input [31:0]S01_AXI_AWADDR;
input [1:0]S01_AXI_AWBURST;
input [3:0]S01_AXI_AWCACHE;
input [0:0]S01_AXI_AWID;
input [7:0]S01_AXI_AWLEN;
input [0:0]S01_AXI_AWLOCK;
input [2:0]S01_AXI_AWPROT;
input [3:0]S01_AXI_AWQOS;
output S01_AXI_AWREADY;
input [3:0]S01_AXI_AWREGION;
input [2:0]S01_AXI_AWSIZE;
input S01_AXI_AWVALID;
output [0:0]S01_AXI_BID;
input S01_AXI_BREADY;
output [1:0]S01_AXI_BRESP;
output S01_AXI_BVALID;
output [63:0]S01_AXI_RDATA;
output [0:0]S01_AXI_RID;
output S01_AXI_RLAST;
input S01_AXI_RREADY;
output [1:0]S01_AXI_RRESP;
output S01_AXI_RVALID;
input [63:0]S01_AXI_WDATA;
input S01_AXI_WLAST;
output S01_AXI_WREADY;
input [7:0]S01_AXI_WSTRB;
input S01_AXI_WVALID;
wire M00_AXI_ACLK;
wire M00_AXI_ARESETN;
wire [31:0]M00_AXI_ARADDR;
wire [1:0]M00_AXI_ARBURST;
wire [3:0]M00_AXI_ARCACHE;
wire [0:0]M00_AXI_ARID;
wire [7:0]M00_AXI_ARLEN;
wire [0:0]M00_AXI_ARLOCK;
wire [2:0]M00_AXI_ARPROT;
wire [3:0]M00_AXI_ARQOS;
wire M00_AXI_ARREADY;
wire [3:0]M00_AXI_ARREGION;
wire [2:0]M00_AXI_ARSIZE;
wire M00_AXI_ARVALID;
wire [31:0]M00_AXI_AWADDR;
wire [1:0]M00_AXI_AWBURST;
wire [3:0]M00_AXI_AWCACHE;
wire [0:0]M00_AXI_AWID;
wire [7:0]M00_AXI_AWLEN;
wire [0:0]M00_AXI_AWLOCK;
wire [2:0]M00_AXI_AWPROT;
wire [3:0]M00_AXI_AWQOS;
wire M00_AXI_AWREADY;
wire [3:0]M00_AXI_AWREGION;
wire [2:0]M00_AXI_AWSIZE;
wire M00_AXI_AWVALID;
wire [0:0]M00_AXI_BID;
wire M00_AXI_BREADY;
wire [1:0]M00_AXI_BRESP;
wire M00_AXI_BVALID;
wire [255:0]M00_AXI_RDATA;
wire [0:0]M00_AXI_RID;
wire M00_AXI_RLAST;
wire M00_AXI_RREADY;
wire [1:0]M00_AXI_RRESP;
wire M00_AXI_RVALID;
wire [255:0]M00_AXI_WDATA;
wire M00_AXI_WLAST;
wire M00_AXI_WREADY;
wire [31:0]M00_AXI_WSTRB;
wire M00_AXI_WVALID;
wire S00_AXI_ACLK;
wire S00_AXI_ARESETN;
wire [31:0]S00_AXI_ARADDR;
wire [1:0]S00_AXI_ARBURST;
wire [3:0]S00_AXI_ARCACHE;
wire [0:0]S00_AXI_ARID;
wire [7:0]S00_AXI_ARLEN;
wire [0:0]S00_AXI_ARLOCK;
wire [2:0]S00_AXI_ARPROT;
wire [3:0]S00_AXI_ARQOS;
wire S00_AXI_ARREADY;
wire [3:0]S00_AXI_ARREGION;
wire [2:0]S00_AXI_ARSIZE;
wire S00_AXI_ARVALID;
wire [31:0]S00_AXI_AWADDR;
wire [1:0]S00_AXI_AWBURST;
wire [3:0]S00_AXI_AWCACHE;
wire [0:0]S00_AXI_AWID;
wire [7:0]S00_AXI_AWLEN;
wire [0:0]S00_AXI_AWLOCK;
wire [2:0]S00_AXI_AWPROT;
wire [3:0]S00_AXI_AWQOS;
wire S00_AXI_AWREADY;
wire [3:0]S00_AXI_AWREGION;
wire [2:0]S00_AXI_AWSIZE;
wire S00_AXI_AWVALID;
wire [0:0]S00_AXI_BID;
wire S00_AXI_BREADY;
wire [1:0]S00_AXI_BRESP;
wire S00_AXI_BVALID;
wire [63:0]S00_AXI_RDATA;
wire [0:0]S00_AXI_RID;
wire S00_AXI_RLAST;
wire S00_AXI_RREADY;
wire [1:0]S00_AXI_RRESP;
wire S00_AXI_RVALID;
wire [63:0]S00_AXI_WDATA;
wire S00_AXI_WLAST;
wire S00_AXI_WREADY;
wire [7:0]S00_AXI_WSTRB;
wire S00_AXI_WVALID;
wire S01_AXI_ACLK;
wire S01_AXI_ARESETN;
wire [31:0]S01_AXI_ARADDR;
wire [1:0]S01_AXI_ARBURST;
wire [3:0]S01_AXI_ARCACHE;
wire [0:0]S01_AXI_ARID;
wire [7:0]S01_AXI_ARLEN;
wire [0:0]S01_AXI_ARLOCK;
wire [2:0]S01_AXI_ARPROT;
wire [3:0]S01_AXI_ARQOS;
wire S01_AXI_ARREADY;
wire [3:0]S01_AXI_ARREGION;
wire [2:0]S01_AXI_ARSIZE;
wire S01_AXI_ARVALID;
wire [31:0]S01_AXI_AWADDR;
wire [1:0]S01_AXI_AWBURST;
wire [3:0]S01_AXI_AWCACHE;
wire [0:0]S01_AXI_AWID;
wire [7:0]S01_AXI_AWLEN;
wire [0:0]S01_AXI_AWLOCK;
wire [2:0]S01_AXI_AWPROT;
wire [3:0]S01_AXI_AWQOS;
wire S01_AXI_AWREADY;
wire [3:0]S01_AXI_AWREGION;
wire [2:0]S01_AXI_AWSIZE;
wire S01_AXI_AWVALID;
wire [0:0]S01_AXI_BID;
wire S01_AXI_BREADY;
wire [1:0]S01_AXI_BRESP;
wire S01_AXI_BVALID;
wire [63:0]S01_AXI_RDATA;
wire [0:0]S01_AXI_RID;
wire S01_AXI_RLAST;
wire S01_AXI_RREADY;
wire [1:0]S01_AXI_RRESP;
wire S01_AXI_RVALID;
wire [63:0]S01_AXI_WDATA;
wire S01_AXI_WLAST;
wire S01_AXI_WREADY;
wire [7:0]S01_AXI_WSTRB;
wire S01_AXI_WVALID;
axi_intercon_2x64_128_bd axi_intercon_2x64_128_bd_i
(.M00_AXI_ACLK(M00_AXI_ACLK),
.M00_AXI_ARESETN(M00_AXI_ARESETN),
.M00_AXI_araddr(M00_AXI_ARADDR),
.M00_AXI_arburst(M00_AXI_ARBURST),
.M00_AXI_arcache(M00_AXI_ARCACHE),
.M00_AXI_arid(M00_AXI_ARID),
.M00_AXI_arlen(M00_AXI_ARLEN),
.M00_AXI_arlock(M00_AXI_ARLOCK),
.M00_AXI_arprot(M00_AXI_ARPROT),
.M00_AXI_arqos(M00_AXI_ARQOS),
.M00_AXI_arready(M00_AXI_ARREADY),
.M00_AXI_arregion(M00_AXI_ARREGION),
.M00_AXI_arsize(M00_AXI_ARSIZE),
.M00_AXI_arvalid(M00_AXI_ARVALID),
.M00_AXI_awaddr(M00_AXI_AWADDR),
.M00_AXI_awburst(M00_AXI_AWBURST),
.M00_AXI_awcache(M00_AXI_AWCACHE),
.M00_AXI_awid(M00_AXI_AWID),
.M00_AXI_awlen(M00_AXI_AWLEN),
.M00_AXI_awlock(M00_AXI_AWLOCK),
.M00_AXI_awprot(M00_AXI_AWPROT),
.M00_AXI_awqos(M00_AXI_AWQOS),
.M00_AXI_awready(M00_AXI_AWREADY),
.M00_AXI_awregion(M00_AXI_AWREGION),
.M00_AXI_awsize(M00_AXI_AWSIZE),
.M00_AXI_awvalid(M00_AXI_AWVALID),
.M00_AXI_bid(M00_AXI_BID),
.M00_AXI_bready(M00_AXI_BREADY),
.M00_AXI_bresp(M00_AXI_BRESP),
.M00_AXI_bvalid(M00_AXI_BVALID),
.M00_AXI_rdata(M00_AXI_RDATA),
.M00_AXI_rid(M00_AXI_RID),
.M00_AXI_rlast(M00_AXI_RLAST),
.M00_AXI_rready(M00_AXI_RREADY),
.M00_AXI_rresp(M00_AXI_RRESP),
.M00_AXI_rvalid(M00_AXI_RVALID),
.M00_AXI_wdata(M00_AXI_WDATA),
.M00_AXI_wlast(M00_AXI_WLAST),
.M00_AXI_wready(M00_AXI_WREADY),
.M00_AXI_wstrb(M00_AXI_WSTRB),
.M00_AXI_wvalid(M00_AXI_WVALID),
.S00_AXI_ACLK(S00_AXI_ACLK),
.S00_AXI_ARESETN(S00_AXI_ARESETN),
.S00_AXI_araddr(S00_AXI_ARADDR),
.S00_AXI_arburst(S00_AXI_ARBURST),
.S00_AXI_arcache(S00_AXI_ARCACHE),
.S00_AXI_arid(S00_AXI_ARID),
.S00_AXI_arlen(S00_AXI_ARLEN),
.S00_AXI_arlock(S00_AXI_ARLOCK),
.S00_AXI_arprot(S00_AXI_ARPROT),
.S00_AXI_arqos(S00_AXI_ARQOS),
.S00_AXI_arready(S00_AXI_ARREADY),
.S00_AXI_arregion(S00_AXI_ARREGION),
.S00_AXI_arsize(S00_AXI_ARSIZE),
.S00_AXI_arvalid(S00_AXI_ARVALID),
.S00_AXI_awaddr(S00_AXI_AWADDR),
.S00_AXI_awburst(S00_AXI_AWBURST),
.S00_AXI_awcache(S00_AXI_AWCACHE),
.S00_AXI_awid(S00_AXI_AWID),
.S00_AXI_awlen(S00_AXI_AWLEN),
.S00_AXI_awlock(S00_AXI_AWLOCK),
.S00_AXI_awprot(S00_AXI_AWPROT),
.S00_AXI_awqos(S00_AXI_AWQOS),
.S00_AXI_awready(S00_AXI_AWREADY),
.S00_AXI_awregion(S00_AXI_AWREGION),
.S00_AXI_awsize(S00_AXI_AWSIZE),
.S00_AXI_awvalid(S00_AXI_AWVALID),
.S00_AXI_bid(S00_AXI_BID),
.S00_AXI_bready(S00_AXI_BREADY),
.S00_AXI_bresp(S00_AXI_BRESP),
.S00_AXI_bvalid(S00_AXI_BVALID),
.S00_AXI_rdata(S00_AXI_RDATA),
.S00_AXI_rid(S00_AXI_RID),
.S00_AXI_rlast(S00_AXI_RLAST),
.S00_AXI_rready(S00_AXI_RREADY),
.S00_AXI_rresp(S00_AXI_RRESP),
.S00_AXI_rvalid(S00_AXI_RVALID),
.S00_AXI_wdata(S00_AXI_WDATA),
.S00_AXI_wlast(S00_AXI_WLAST),
.S00_AXI_wready(S00_AXI_WREADY),
.S00_AXI_wstrb(S00_AXI_WSTRB),
.S00_AXI_wvalid(S00_AXI_WVALID),
.S01_AXI_ACLK(S01_AXI_ACLK),
.S01_AXI_ARESETN(S01_AXI_ARESETN),
.S01_AXI_araddr(S01_AXI_ARADDR),
.S01_AXI_arburst(S01_AXI_ARBURST),
.S01_AXI_arcache(S01_AXI_ARCACHE),
.S01_AXI_arid(S01_AXI_ARID),
.S01_AXI_arlen(S01_AXI_ARLEN),
.S01_AXI_arlock(S01_AXI_ARLOCK),
.S01_AXI_arprot(S01_AXI_ARPROT),
.S01_AXI_arqos(S01_AXI_ARQOS),
.S01_AXI_arready(S01_AXI_ARREADY),
.S01_AXI_arregion(S01_AXI_ARREGION),
.S01_AXI_arsize(S01_AXI_ARSIZE),
.S01_AXI_arvalid(S01_AXI_ARVALID),
.S01_AXI_awaddr(S01_AXI_AWADDR),
.S01_AXI_awburst(S01_AXI_AWBURST),
.S01_AXI_awcache(S01_AXI_AWCACHE),
.S01_AXI_awid(S01_AXI_AWID),
.S01_AXI_awlen(S01_AXI_AWLEN),
.S01_AXI_awlock(S01_AXI_AWLOCK),
.S01_AXI_awprot(S01_AXI_AWPROT),
.S01_AXI_awqos(S01_AXI_AWQOS),
.S01_AXI_awready(S01_AXI_AWREADY),
.S01_AXI_awregion(S01_AXI_AWREGION),
.S01_AXI_awsize(S01_AXI_AWSIZE),
.S01_AXI_awvalid(S01_AXI_AWVALID),
.S01_AXI_bid(S01_AXI_BID),
.S01_AXI_bready(S01_AXI_BREADY),
.S01_AXI_bresp(S01_AXI_BRESP),
.S01_AXI_bvalid(S01_AXI_BVALID),
.S01_AXI_rdata(S01_AXI_RDATA),
.S01_AXI_rid(S01_AXI_RID),
.S01_AXI_rlast(S01_AXI_RLAST),
.S01_AXI_rready(S01_AXI_RREADY),
.S01_AXI_rresp(S01_AXI_RRESP),
.S01_AXI_rvalid(S01_AXI_RVALID),
.S01_AXI_wdata(S01_AXI_WDATA),
.S01_AXI_wlast(S01_AXI_WLAST),
.S01_AXI_wready(S01_AXI_WREADY),
.S01_AXI_wstrb(S01_AXI_WSTRB),
.S01_AXI_wvalid(S01_AXI_WVALID));
endmodule
top/x300/ip/bootram/Makefile.inc
+15
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@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_BOOTRAM_SRCS = $(IP_BUILD_DIR)/bootram/bootram.xci
IP_BOOTRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/bootram/, \
bootram.xci.out \
synth/bootram.vhd \
)
$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS) : $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe
$(call BUILD_VIVADO_IP,bootram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/bootram/bootram.coe
+8194
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File diff suppressed because it is too large Load Diff
top/x300/ip/bootram/bootram.xci
+318
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@@ -0,0 +1,318 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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</spirit:design>
top/x300/ip/bus_clk_gen/Makefile.inc
+15
View File
@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_BUS_CLK_GEN_SRCS = $(IP_BUILD_DIR)/bus_clk_gen/bus_clk_gen.xci
IP_BUS_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/bus_clk_gen/, \
bus_clk_gen.xci.out \
bus_clk_gen.v \
)
$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS) : $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci
$(call BUILD_VIVADO_IP,bus_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/bus_clk_gen/bus_clk_gen.xci
+786
View File
@@ -0,0 +1,786 @@
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">CLKFB_STOPPED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">187.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">125.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">187.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">187.5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.00</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">93.750</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">125.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">125.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">214.286</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">93.750</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">93.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">214.286</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">215</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">CLK_OUT2_UNBUF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">DADDR</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">DCLK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">DEN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">DIN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">1.5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.872093023255814</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">1.875</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">1.875</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">1.875</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">DOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">DRDY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">DWE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_ONCHIP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________125.000____________0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">LOCKED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">12.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">8.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2_UNBUF___125.000______0.000______50.0_______91.831_____73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">125.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">PSCLK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">PSDONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">PSEN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">RESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">bus_clk_gen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">DONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">CLKFB_STOPPED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">85.263</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">187.5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.00</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">91.831</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">125.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">96.813</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">93.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">83.210</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">73.940</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">215</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">CLK_OUT2_UNBUF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">MANUAL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bus_clk_gen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">DADDR</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">DCLK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">DEN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">DIN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">DOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">DRDY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">DWE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_ONCHIP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">LOCKED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">MMCM_ADV</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">125.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">PSCLK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">PSDONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">PSEN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">RESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CALC_DONE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_IN_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_OUT_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT3_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT4_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT5_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT6_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT7_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DADDR_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DCLK_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DEN_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DOUT_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DRDY_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DWE_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCKED_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PLATFORM" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.POWER_DOWN_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMARY_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMTYPE_SEL" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PSCLK_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PSDONE_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PSEN_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PSINCDEC_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SECONDARY_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x300/ip/ddr3_32bit/Makefile.inc
+26
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#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_DDR3_32BIT_SRCS = \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v
IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \
ddr3_32bit.xci.out \
ddr3_32bit/user_design/rtl/ddr3_32bit.v \
ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \
)
IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \
ddr3_32bit/example_design/sim/ddr3_model.sv \
ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \
)
$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj
cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds
$(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj
top/x300/ip/ddr3_32bit/ddr3_32bit.xci
+2645
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File diff suppressed because it is too large Load Diff
top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj
+163
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@@ -0,0 +1,163 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>ddr3_32bit</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
<Version>4.0</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<FPGADevice>
<selected>7k/xc7k325t-ffg900</selected>
</FPGADevice>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-125</MemoryDevice>
<TimePeriod>1666</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100.04</InputClkFreq>
<UIExtraClocks>1</UIExtraClocks>
<MMCM_VCO>1200</MMCM_VCO>
<MMCMClkOut0>4.000</MMCMClkOut0>
<MMCMClkOut1>6</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>32</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD11" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD12" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="AE10(SRCC_P)" IOSTANDARD="LVCMOS15" Bank="32" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >9</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >7</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj
+163
View File
@@ -0,0 +1,163 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>ddr3_32bit</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7k410t-ffg900/-2</TargetFPGA>
<Version>4.0</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<FPGADevice>
<selected>7k/xc7k325t-ffg900</selected>
</FPGADevice>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-125</MemoryDevice>
<TimePeriod>1666</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100.04</InputClkFreq>
<UIExtraClocks>1</UIExtraClocks>
<MMCM_VCO>1200</MMCM_VCO>
<MMCMClkOut0>4.000</MMCMClkOut0>
<MMCMClkOut1>6</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>32</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD11" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD12" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="AE10(SRCC_P)" IOSTANDARD="LVCMOS15" Bank="32" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >9</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >7</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
top/x300/ip/fifo_4k_2clk/Makefile.inc
+15
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@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
fifo_4k_2clk.xci.out \
synth/fifo_4k_2clk.vhd \
)
$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
$(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci
+576
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@@ -0,0 +1,576 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>fifo_4k_2clk</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_4k_2clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Disable_Timing_Violations" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x300/ip/fifo_short_2clk/Makefile.inc
+15
View File
@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci
IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \
fifo_short_2clk.xci.out \
synth/fifo_short_2clk.vhd \
)
$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci
$(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)

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