Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,70 @@
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#
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# Copyright 2015 Ettus Research LLC
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../..)
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynq
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PART_ID = xc7z100/ffg900/-2
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = ../../ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(IP_DIR)/ddr3_32bit/Makefile.inc
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include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(IP_DDR3_32BIT_SRCS) \
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$(IP_AXI_INTERCON_4X64_256_SRCS) \
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$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \
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$(IP_FIFO_4K_2CLK_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = dram_fifo_bist_tb
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SIM_SRCS = \
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$(abspath dram_fifo_bist_tb.sv) \
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$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
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$(IP_DDR3_32BIT_SIM_OUTS)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,348 @@
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//
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// Copyright 2015 Ettus Research LLC
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//
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`timescale 1ns/1ps
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`define SIM_RUNTIME_US 3000
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`define NS_PER_TICK 1
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`define NUM_TEST_CASES 8
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`include "sim_clks_rsts.vh"
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`include "sim_exec_report.vh"
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`include "sim_cvita_lib.svh"
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`include "sim_axi4_lib.svh"
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`include "sim_set_rb_lib.svh"
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module dram_fifo_bist_tb();
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`TEST_BENCH_INIT("dram_fifo_bist_tb",`NUM_TEST_CASES,`NS_PER_TICK)
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// Define all clocks and resets
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`DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clocking
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`DEFINE_CLK(bus_clk, 1000/200, 50) //200MHz bus_clk
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`DEFINE_CLK(dma_engine_clk, 1000/300, 50) //300MHz dma_engine_clk
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`DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert
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`DEFINE_RESET_N(sys_rst_n, 0, 100) //100ns for GSR to deassert
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localparam EXTENDED_TEST = 0;
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// Initialize DUT
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wire calib_complete;
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wire running, done;
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wire [1:0] error;
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wire [31:0] rb_data;
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reg [63:0] forced_bit_err;
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settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk));
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cvita_master cvita_fifo_in (.clk(bus_clk));
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cvita_slave cvita_fifo_out (.clk(bus_clk));
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// AXI DRAM FIFO Topology (Inline production BIST for DRAM FIFO):
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//
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// User Data ====> |---------| |---------------| |-----------| ====> User Data Out
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// | AXI MUX | ====> | AXI DRAM FIFO | ====> | AXI DEMUX |
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// BIST Data ====> |---------| |---------------| |-----------| ====> BIST Data Out
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// ||
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// |--------------|
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// | MIG (D/S)RAM |
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// |--------------|
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localparam SR_FIFO_BASE = 0;
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localparam SR_BIST_BASE = SR_FIFO_BASE + 4;
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axis_dram_fifo_single dut_single (
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.bus_clk(bus_clk),
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.bus_rst(bus_rst),
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.sys_clk_p(sys_clk_p),//use differential clock on N310
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.sys_clk_n(sys_clk_n),
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.sys_rst_n(sys_rst_n),
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.dma_engine_clk(dma_engine_clk),
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.i_tdata(cvita_fifo_in.axis.tdata),
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.i_tlast(cvita_fifo_in.axis.tlast),
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.i_tvalid(cvita_fifo_in.axis.tvalid),
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.i_tready(cvita_fifo_in.axis.tready),
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.o_tdata(cvita_fifo_out.axis.tdata),
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.o_tlast(cvita_fifo_out.axis.tlast),
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.o_tvalid(cvita_fifo_out.axis.tvalid),
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.o_tready(cvita_fifo_out.axis.tready),
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.set_stb(tst_set.settings_bus.set_stb),
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.set_addr(tst_set.settings_bus.set_addr),
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.set_data(tst_set.settings_bus.set_data),
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.rb_data(rb_data),
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.forced_bit_err(forced_bit_err),
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.init_calib_complete(calib_complete)
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);
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assign {error, done, running} = rb_data[3:0];
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//Testbench variables
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cvita_hdr_t header;
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cvita_pkt_t pkt_out;
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integer i;
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integer single_run_time;
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integer xfer_cnt, cyc_cnt;
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//------------------------------------------
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//Main thread for testbench execution
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//------------------------------------------
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initial begin : tb_main
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string s;
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`TEST_CASE_START("Wait for reset");
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while (bus_rst) @(posedge bus_clk);
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while (~sys_rst_n) @(posedge sys_clk_p);
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`TEST_CASE_DONE(~bus_rst & sys_rst_n);
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forced_bit_err <= 64'h0;
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repeat (200) @(posedge sys_clk_p);
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`TEST_CASE_START("Wait for initial calibration to complete");
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while (calib_complete !== 1'b1) @(posedge bus_clk);
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`TEST_CASE_DONE(calib_complete);
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`TEST_CASE_START("Clear FIFO");
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tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1});
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repeat (200) @(posedge bus_clk);
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tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0});
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repeat (200) @(posedge bus_clk);
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`TEST_CASE_DONE(1);
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//Select BIST status as the readback output
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tst_set.write(SR_FIFO_BASE + 0, 3'd1);
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header = '{
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pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666,
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length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};
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`TEST_CASE_START("Fill up empty FIFO then drain (long packet)");
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cvita_fifo_in.push_ramp_pkt(100, 64'd0, 64'h100, header);
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cvita_fifo_out.pull_pkt(pkt_out);
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$sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",100,pkt_out.payload.size());
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`ASSERT_ERROR(pkt_out.payload.size()==100, s);
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$sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x",
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{header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid});
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`ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s);
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i = 0;
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repeat (100) begin
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$sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x",
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i,(i * 64'h100),pkt_out.payload[i]);
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`ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s);
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end
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Setup BIST: 10 x 40byte packets");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 3, 32'h01234567);
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tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0});
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tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd40, 18'd10});
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`TEST_CASE_DONE(~done & ~running);
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`TEST_CASE_START("Run BIST");
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tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1});
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while (~done) @(posedge bus_clk);
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`ASSERT_ERROR(error==2'b00, "BIST failed!");
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@(posedge bus_clk);
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`TEST_CASE_DONE(done & ~running);
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`TEST_CASE_START("Run BIST ... again (should fail)");
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forced_bit_err <= 64'h8000000000000000;
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1});
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while (~done) @(posedge bus_clk);
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`ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!");
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forced_bit_err <= 64'h0;
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@(posedge bus_clk);
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`TEST_CASE_DONE(done & ~running);
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`TEST_CASE_START("Run BIST ... and again (should pass)");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b0, 1'b1});
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while (~done) @(posedge bus_clk);
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`ASSERT_ERROR(error==2'b00, "BIST failed!");
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@(posedge bus_clk);
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`TEST_CASE_DONE(done & ~running);
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if (EXTENDED_TEST) begin // Extended test mode
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`TEST_CASE_START("Setup BIST: 8000 x 40byte ramping packets");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 3, 32'h01234567);
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tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0});
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tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd40, 18'd8000});
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`TEST_CASE_DONE(~done & ~running);
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`TEST_CASE_START("Run BIST");
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tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1});
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while (~done) @(posedge bus_clk);
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`ASSERT_ERROR(error==2'b00, "BIST failed!");
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@(posedge bus_clk);
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`TEST_CASE_DONE(done & ~running);
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`TEST_CASE_START("Setup BIST: 256 x 1000byte packets");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0);
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tst_set.write(SR_BIST_BASE + 2, {8'd4, 16'd256});
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tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd1000, 18'd256});
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`TEST_CASE_DONE(~done & ~running);
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`TEST_CASE_START("Run BIST");
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tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1});
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while (~done) @(negedge bus_clk);
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`ASSERT_ERROR(error==2'b00, "BIST failed!");
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@(posedge bus_clk);
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`TEST_CASE_DONE(done & ~running);
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`TEST_CASE_START("User Data: Concurrent read and write");
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cvita_fifo_out.axis.tready = 1;
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fork
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begin
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cvita_fifo_in.push_ramp_pkt(20, 64'd0, 64'h100, header);
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end
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begin
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cvita_fifo_out.pull_pkt(pkt_out);
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end
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join
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$sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size());
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`ASSERT_ERROR(pkt_out.payload.size()==20, s);
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Setup BIST: 256 x 600byte ramping packets");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 3, 32'h01234567);
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tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0});
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tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd600, 18'd256});
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`TEST_CASE_DONE(~done & ~running);
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`TEST_CASE_START("Run BIST");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1});
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while (~done) @(posedge bus_clk);
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`ASSERT_ERROR(error==2'b00, "BIST failed!");
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@(posedge bus_clk);
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`TEST_CASE_DONE(done & ~running);
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`TEST_CASE_START("Setup BIST: 30 x 8000byte packets");
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tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
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tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0);
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tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0});
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tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd8000, 18'd30});
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`TEST_CASE_DONE(~done & ~running);
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`TEST_CASE_START("Run BIST");
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tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1});
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while (~done) @(negedge bus_clk);
|
||||
`ASSERT_ERROR(error==2'b00, "BIST failed!");
|
||||
@(posedge bus_clk);
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
|
||||
`TEST_CASE_START("Setup BIST: 100 x 8000byte ramping packets");
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0);
|
||||
tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0});
|
||||
tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd8000, 18'd100});
|
||||
`TEST_CASE_DONE(~done & ~running);
|
||||
|
||||
`TEST_CASE_START("Run BIST");
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1});
|
||||
while (~done) @(negedge bus_clk);
|
||||
`ASSERT_ERROR(error==2'b00, "BIST failed!");
|
||||
@(posedge bus_clk);
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
|
||||
`TEST_CASE_START("Validate Throughput");
|
||||
tst_set.write(SR_FIFO_BASE + 0, 3'd2);
|
||||
xfer_cnt = rb_data;
|
||||
tst_set.write(SR_FIFO_BASE + 0, 3'd3);
|
||||
cyc_cnt = rb_data;
|
||||
`ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0");
|
||||
`ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0");
|
||||
$display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt));
|
||||
`ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%");
|
||||
tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
|
||||
`TEST_CASE_START("Setup BIST: 10 x 256byte packets");
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
tst_set.write(SR_BIST_BASE + 3, 32'hFFFFFFFF);
|
||||
tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0});
|
||||
tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd256, 18'd30});
|
||||
`TEST_CASE_DONE(~done & ~running);
|
||||
|
||||
fork
|
||||
begin
|
||||
integer curr_time = $time;
|
||||
`TEST_CASE_START("Run BIST Continuous (Early interrupt)");
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1});
|
||||
while (~done) @(negedge bus_clk);
|
||||
`ASSERT_ERROR(error==2'b00, "BIST failed!");
|
||||
@(posedge bus_clk);
|
||||
single_run_time = $time - curr_time;
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
end
|
||||
begin
|
||||
//Wait then clear
|
||||
#2000;
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
end
|
||||
join
|
||||
|
||||
fork
|
||||
begin
|
||||
`TEST_CASE_START("Run BIST Continuous (Force error)");
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1});
|
||||
while (~done) @(negedge bus_clk);
|
||||
`ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!");
|
||||
@(posedge bus_clk);
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
end
|
||||
begin
|
||||
//Wait then force error
|
||||
#10000;
|
||||
forced_bit_err <= 64'h1;
|
||||
end
|
||||
join
|
||||
//Recover from failure
|
||||
forced_bit_err <= 64'h0;
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
repeat (2000) @(posedge bus_clk);
|
||||
|
||||
fork
|
||||
begin
|
||||
integer curr_time = $time;
|
||||
`TEST_CASE_START("Run BIST Continuous");
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1});
|
||||
while (~done) @(negedge bus_clk);
|
||||
`ASSERT_ERROR(error==2'b00, "BIST failed!");
|
||||
@(posedge bus_clk);
|
||||
`ASSERT_ERROR((($time - curr_time) > 2 * single_run_time), "Continuous test most likely stopped early!");
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
end
|
||||
begin
|
||||
//Wait then clear
|
||||
#100000;
|
||||
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
|
||||
end
|
||||
join
|
||||
|
||||
`TEST_CASE_START("Validate Throughput");
|
||||
tst_set.write(SR_FIFO_BASE + 0, 3'd2);
|
||||
xfer_cnt = rb_data;
|
||||
tst_set.write(SR_FIFO_BASE + 0, 3'd3);
|
||||
cyc_cnt = rb_data;
|
||||
`ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0");
|
||||
`ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0");
|
||||
$display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt));
|
||||
`ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%");
|
||||
tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore
|
||||
`TEST_CASE_DONE(done & ~running);
|
||||
end
|
||||
|
||||
`TEST_BENCH_DONE;
|
||||
|
||||
end
|
||||
endmodule
|
||||
Reference in New Issue
Block a user