Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f

top/n3xx/n3xx_wr.xdc

@@ -0,0 +1,78 @@
+#
+# Copyright 2018 Ettus Research, A National Instruments Company
+# SPDX-License-Identifier: LGPL-3.0
+#
+
+
+# 20 MHz White Rabbit reference
+create_clock -name wr_refclk -period 50.000 [get_ports WB_20MHZ_P]
+
+# 62.5M TXOUTCLK from the MGT that does most of the heavy lifting
+create_clock -name wr_txoutclk -period 16.000 \
+  [get_pins -hierarchical -filter \
+    {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK}]
+
+# 62.5M RXOUTCLK from the MGT that doesn't do as much as the TXOUTCLK
+create_clock -name wr_rxoutclk -period 16.000 \
+  [get_pins -hierarchical -filter \
+    {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK}]
+
+# Rename the WR 62.5M system clock
+create_generated_clock -name wr_sysclk \
+  [get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_sys_clk_pll/CLKOUT0}]
+
+# Rename the WR ~62.5M DMTD clock
+create_generated_clock -name wr_dmtdclk \
+  [get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0}]
+
+
+
+# Clock Interaction Matrix : ------------------------------------------------------------
+# Everything is basically async to everything else, except for the net_clk group.
+# Blanks mean there are no paths there (in the WR v4.2 build).
+#
+# The wr_sysclk (62.5 MHz) is derived from the 125 MHz MGT Reference clock (NETCLK).
+# On the other hand, the wr_dmtdclk, also a 62.5 MHz clock, is derived from the 20 MHz
+# WR VCXO. This two clock groups could be considered asynchronous due to its different
+# source and different MMCM primitive (which unrelates them even more).
+#
+#             | wr_RXOUTCLK | wr_TXOUTCLK | wr_dmtdclk | wr_sysclk | net_clk
+# wr_RXOUTCLK |    timed    |   async     |   async    |  async    |
+# wr_TXOUTCLK |    async    |   timed     |   async    |  async    |
+# wr_dmtdclk  |             |             |   timed    |  async    |
+# wr_sysclk   |    async    |   async     |   async    |  timed    |  timed
+# net_clk     |    async    |             |            |  timed    |  timed
+
+set_clock_groups -asynchronous  -group [get_clocks wr_rxoutclk] \
+                                -group [get_clocks wr_txoutclk] \
+                                -group [get_clocks wr_dmtdclk]  \
+                                -group [get_clocks net_clk]
+
+set_clock_groups -asynchronous  -group [get_clocks wr_sysclk] \
+                                -group [get_clocks wr_txoutclk] \
+                                -group [get_clocks wr_rxoutclk] \
+                                -group [get_clocks wr_dmtdclk]
+
+# Safe paths : --------------------------------------------------------------------------
+# There is a mix of safe and unknown clock interactions between wr_sysclk and wr_dmtdclk.
+# The safe crossings refer to those using a synchronizer structure; and to avoid
+# failing timing on those paths, we ignore them (i.e. false paths), and allow the tools
+# to time the rest.
+#
+# The WR IP uses easily identifiable single-bit synchronizers to transfer strobes from
+# the wr_dmtdclk to the wr_sysclk domain.
+#
+# Commenting out command since the asynchronous groups were updated and paths ignored.
+# set_false_path -from [get_clocks wr_dmtdclk] \
+#                -to   [get_pins -hierarchical -filter {NAME =~ */sync_posedge.sync0_reg/D}]
+#
+#
+# The tags generated by the DDMTD (wr_dmtdclk domain) are deglitched before being output
+# to the upstream logic in the wr_sysclk domain. Thus, a safe multi-bit crossing is
+# expected between these two domains, and we tell the tools to ignore those paths.
+# See usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd for
+# implementation details.
+#
+# Commenting out command since the asynchronous groups were updated and paths ignored.
+# set_false_path -from [get_clocks wr_dmtdclk] \
+#                -to   [get_pins -hierarchical -filter {NAME =~ */U_Wrapped_Softpll/tags_masked_reg*/D}]