Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,42 @@
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#
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# Copyright 2008-2013 Ettus Research LLC
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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TEN_GIGE_PHY_SRCS = \
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$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \
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$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \
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$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v \
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$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS)
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IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/imports/, \
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ten_gig_eth_pcs_pma_example_design.v \
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ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \
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ten_gig_eth_pcs_pma_shared_clock_and_reset.v \
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ten_gig_eth_pcs_pma_support.v \
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)
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IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
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IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \
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ten_gig_eth_pcs_pma.xci.out \
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synth/ten_gig_eth_pcs_pma_block.v \
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synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \
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synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \
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synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \
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synth/ten_gig_eth_pcs_pma_clocks.xdc \
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synth/ten_gig_eth_pcs_pma_ooc.xdc \
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synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \
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synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \
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synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \
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synth/ten_gig_eth_pcs_pma.v \
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synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
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synth/ten_gig_eth_pcs_pma.xdc \
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)
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$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS)
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$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
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$(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
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@@ -0,0 +1,192 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>xci</spirit:library>
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<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>ten_gig_eth_pcs_pma</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ten_gig_eth_pcs_pma" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_CORECLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_CORECLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_DATAPATHCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_RXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTRXRESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTRXRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTTXRESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTTXRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFRESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_INTERFACE.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCS_RESETOUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESETOUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_DIFF_PORT.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET_TX_BUFG_GT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRESET_RXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXRESET_TXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ten_gig_eth_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dclkrate">100.00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gtif_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gttype">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_an">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_fec">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_32bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_kr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_ebuff">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk">clk0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclkrate">156</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_speed10_25">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sub_core_name">ten_gig_eth_pcs_pma_gt</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ten_gig_eth_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DClkRate">100.00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IEEE_1588">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Locations">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_Management">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClk">clk0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkRate">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverInExample">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.autonegotiation">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.base_kr">BASE-R</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.baser32">64bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fec">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.no_ebuff">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.speed10_25">10Gig</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu_gt_type">GTH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,202 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Title : GT Common wrapper
|
||||
// Project : 10GBASE-R
|
||||
//-----------------------------------------------------------------------------
|
||||
// File : ten_gig_eth_pcs_pma_gt_common.v
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: This file contains the
|
||||
// 10GBASE-R Transceiver GT Common block.
|
||||
//-----------------------------------------------------------------------------
|
||||
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
`timescale 1ps / 1ps
|
||||
|
||||
module ten_gig_eth_pcs_pma_gt_common # (
|
||||
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware
|
||||
(
|
||||
input refclk,
|
||||
input qpllreset,
|
||||
output qplllock,
|
||||
output qplloutclk,
|
||||
output qplloutrefclk,
|
||||
input [2:0] qpllrefclksel
|
||||
);
|
||||
|
||||
|
||||
//***************************** Parameter Declarations ************************
|
||||
localparam QPLL_FBDIV_TOP = 66;
|
||||
|
||||
localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
|
||||
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
|
||||
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
|
||||
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
|
||||
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
|
||||
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
|
||||
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
|
||||
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
|
||||
|
||||
localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
|
||||
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
|
||||
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
|
||||
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
|
||||
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
|
||||
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
|
||||
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
|
||||
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
|
||||
|
||||
//***************************** Wire Declarations *****************************
|
||||
|
||||
// ground and vcc signals
|
||||
wire tied_to_ground_i;
|
||||
wire [63:0] tied_to_ground_vec_i;
|
||||
wire tied_to_vcc_i;
|
||||
wire [63:0] tied_to_vcc_vec_i;
|
||||
|
||||
//********************************* Main Body of Code**************************
|
||||
|
||||
assign tied_to_ground_i = 1'b0;
|
||||
assign tied_to_ground_vec_i = 64'h0000000000000000;
|
||||
assign tied_to_vcc_i = 1'b1;
|
||||
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
|
||||
|
||||
|
||||
wire gt0_gtrefclk0_common_in;
|
||||
wire gt0_qpllreset_in;
|
||||
wire gt0_qplllock_out;
|
||||
wire gt0_qplloutclk_i;
|
||||
wire gt0_qplloutrefclk_i;
|
||||
|
||||
assign gt0_gtrefclk0_common_in = refclk;
|
||||
assign gt0_qpllreset_in = qpllreset;
|
||||
assign qplllock = gt0_qplllock_out;
|
||||
assign qplloutclk = gt0_qplloutclk_i;
|
||||
assign qplloutrefclk = gt0_qplloutrefclk_i;
|
||||
|
||||
|
||||
//_________________________________________________________________________
|
||||
//_________________________________________________________________________
|
||||
//_________________________GTXE2_COMMON____________________________________
|
||||
|
||||
GTXE2_COMMON #
|
||||
(
|
||||
// Simulation attributes
|
||||
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
|
||||
.SIM_QPLLREFCLK_SEL (3'b001),
|
||||
.SIM_VERSION ("4.0"),
|
||||
|
||||
|
||||
//----------------COMMON BLOCK Attributes---------------
|
||||
.BIAS_CFG (64'h0000040000001000),
|
||||
.COMMON_CFG (32'h00000000),
|
||||
.QPLL_CFG (27'h0680181),
|
||||
.QPLL_CLKOUT_CFG (4'b0000),
|
||||
.QPLL_COARSE_FREQ_OVRD (6'b010000),
|
||||
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
|
||||
.QPLL_CP (10'b0000011111),
|
||||
.QPLL_CP_MONITOR_EN (1'b0),
|
||||
.QPLL_DMONITOR_SEL (1'b0),
|
||||
.QPLL_FBDIV (QPLL_FBDIV_IN),
|
||||
.QPLL_FBDIV_MONITOR_EN (1'b0),
|
||||
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
|
||||
.QPLL_INIT_CFG (24'h000006),
|
||||
.QPLL_LOCK_CFG (16'h21E8),
|
||||
.QPLL_LPF (4'b1111),
|
||||
.QPLL_REFCLK_DIV (1)
|
||||
)
|
||||
gtxe2_common_0_i
|
||||
(
|
||||
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
|
||||
.DRPADDR (tied_to_ground_vec_i[7:0]),
|
||||
.DRPCLK (tied_to_ground_i),
|
||||
.DRPDI (tied_to_ground_vec_i[15:0]),
|
||||
.DRPDO (),
|
||||
.DRPEN (tied_to_ground_i),
|
||||
.DRPRDY (),
|
||||
.DRPWE (tied_to_ground_i),
|
||||
//-------------------- Common Block - Ref Clock Ports ---------------------
|
||||
.GTGREFCLK (tied_to_ground_i),
|
||||
.GTNORTHREFCLK0 (tied_to_ground_i),
|
||||
.GTNORTHREFCLK1 (tied_to_ground_i),
|
||||
.GTREFCLK0 (gt0_gtrefclk0_common_in),
|
||||
.GTREFCLK1 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK0 (tied_to_ground_i),
|
||||
.GTSOUTHREFCLK1 (tied_to_ground_i),
|
||||
//--------------------- Common Block - Clocking Ports ----------------------
|
||||
.QPLLOUTCLK (gt0_qplloutclk_i),
|
||||
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
|
||||
.REFCLKOUTMONITOR (),
|
||||
//----------------------- Common Block - QPLL Ports ------------------------
|
||||
.QPLLDMONITOR (),
|
||||
.QPLLFBCLKLOST (),
|
||||
.QPLLLOCK (gt0_qplllock_out),
|
||||
.QPLLLOCKDETCLK (1'b0),
|
||||
.QPLLLOCKEN (tied_to_vcc_i),
|
||||
.QPLLOUTRESET (tied_to_ground_i),
|
||||
.QPLLPD (tied_to_ground_i),
|
||||
.QPLLREFCLKLOST (),
|
||||
.QPLLREFCLKSEL (qpllrefclksel),
|
||||
.QPLLRESET (gt0_qpllreset_in),
|
||||
.QPLLRSVD1 (16'b0000000000000000),
|
||||
.QPLLRSVD2 (5'b11111),
|
||||
//------------------------------- QPLL Ports -------------------------------
|
||||
.BGBYPASSB (tied_to_vcc_i),
|
||||
.BGMONITORENB (tied_to_vcc_i),
|
||||
.BGPDB (tied_to_vcc_i),
|
||||
.BGRCALOVRD (5'b11111),
|
||||
.PMARSVD (8'b00000000),
|
||||
.RCALENB (tied_to_vcc_i)
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,241 @@
|
||||
//
|
||||
// Copyright 2008-2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
module ten_gige_phy
|
||||
(
|
||||
input refclk,
|
||||
input clk156,
|
||||
input dclk,
|
||||
input areset,
|
||||
input sim_speedup_control,
|
||||
input [63:0] xgmii_txd,
|
||||
input [7:0] xgmii_txc,
|
||||
output reg [63:0] xgmii_rxd,
|
||||
output reg [7:0] xgmii_rxc,
|
||||
output txp,
|
||||
output txn,
|
||||
input rxp,
|
||||
input rxn,
|
||||
input mdc,
|
||||
input mdio_in,
|
||||
output reg mdio_out,
|
||||
output reg mdio_tri,
|
||||
input [4:0] prtad,
|
||||
output [7:0] core_status,
|
||||
output resetdone,
|
||||
input signal_detect,
|
||||
input tx_fault,
|
||||
output tx_disable,
|
||||
output qpllreset,
|
||||
input qplllock,
|
||||
input qplloutclk,
|
||||
input qplloutrefclk,
|
||||
output tx_out_clk
|
||||
);
|
||||
|
||||
reg [63:0] xgmii_txd_reg;
|
||||
reg [7:0] xgmii_txc_reg;
|
||||
wire [63:0] xgmii_rxd_int;
|
||||
wire [7:0] xgmii_rxc_int;
|
||||
|
||||
// Add a pipeline to the xmgii_tx inputs, to aid timing closure
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
xgmii_txd_reg <= xgmii_txd;
|
||||
xgmii_txc_reg <= xgmii_txc;
|
||||
end
|
||||
|
||||
// Add a pipeline to the xmgii_rx outputs, to aid timing closure
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
xgmii_rxd <= xgmii_rxd_int;
|
||||
xgmii_rxc <= xgmii_rxc_int;
|
||||
end
|
||||
|
||||
wire mdio_out_int;
|
||||
wire mdio_tri_int;
|
||||
reg mdc_reg;
|
||||
reg mdio_in_reg;
|
||||
|
||||
// Add a pipeline to the mdio in/outputs, to aid timing closure
|
||||
// This is safe because the mdio clock is running so slowly
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
mdio_out <= mdio_out_int;
|
||||
mdio_tri <= mdio_tri_int;
|
||||
mdc_reg <= mdc;
|
||||
mdio_in_reg <= mdio_in;
|
||||
end
|
||||
|
||||
// Signal declarations
|
||||
wire txclk322;
|
||||
|
||||
wire drp_gnt;
|
||||
wire drp_req;
|
||||
wire drp_den_o;
|
||||
wire drp_dwe_o;
|
||||
wire [15:0] drp_daddr_o;
|
||||
wire [15:0] drp_di_o;
|
||||
wire drp_drdy_o;
|
||||
wire [15:0] drp_drpdo_o;
|
||||
wire drp_den_i;
|
||||
wire drp_dwe_i;
|
||||
wire [15:0] drp_daddr_i;
|
||||
wire [15:0] drp_di_i;
|
||||
wire drp_drdy_i;
|
||||
wire [15:0] drp_drpdo_i;
|
||||
|
||||
wire tx_resetdone_int;
|
||||
wire rx_resetdone_int;
|
||||
|
||||
wire areset_clk156;
|
||||
wire gttxreset;
|
||||
wire gtrxreset;
|
||||
wire qplllock_txusrclk2;
|
||||
wire gttxreset_txusrclk2;
|
||||
wire reset_counter_done;
|
||||
wire txusrclk;
|
||||
wire txusrclk2;
|
||||
reg txuserrdy;
|
||||
|
||||
assign resetdone = tx_resetdone_int && rx_resetdone_int;
|
||||
|
||||
// If no arbitration is required on the GT DRP ports then connect REQ to GNT
|
||||
// and connect other signals i <= o;
|
||||
assign drp_gnt = drp_req;
|
||||
assign drp_den_i = drp_den_o;
|
||||
assign drp_dwe_i = drp_dwe_o;
|
||||
assign drp_daddr_i = drp_daddr_o;
|
||||
assign drp_di_i = drp_di_o;
|
||||
assign drp_drdy_i = drp_drdy_o;
|
||||
assign drp_drpdo_i = drp_drpdo_o;
|
||||
|
||||
// Asynch reset synchronizers...
|
||||
ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #(
|
||||
.C_NUM_SYNC_REGS(4),
|
||||
.C_RVAL(1'b1)
|
||||
) areset_clk156_sync_i (
|
||||
.clk(clk156),
|
||||
.rst(areset),
|
||||
.data_in(1'b0),
|
||||
.data_out(areset_clk156)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #(
|
||||
.C_NUM_SYNC_REGS(4),
|
||||
.C_RVAL(1'b0)
|
||||
) qplllock_txusrclk2_sync_i (
|
||||
.clk(txusrclk2),
|
||||
.rst(!qplllock),
|
||||
.data_in(1'b1),
|
||||
.data_out(qplllock_txusrclk2)
|
||||
);
|
||||
|
||||
reg [7:0] reset_counter = 8'h00;
|
||||
reg [3:0] reset_pulse = 4'b1110;
|
||||
assign reset_counter_done = reset_counter[7];
|
||||
|
||||
// Hold off the GT resets until 500ns after configuration.
|
||||
// 128 ticks at 6.4ns period will be >> 500 ns.
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if (!reset_counter[7])
|
||||
reset_counter <= reset_counter + 1'b1;
|
||||
else
|
||||
reset_counter <= reset_counter;
|
||||
end
|
||||
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if (areset_clk156 == 1'b1)
|
||||
reset_pulse <= 4'b1110;
|
||||
else if(reset_counter[7])
|
||||
reset_pulse <= {1'b0, reset_pulse[3:1]};
|
||||
end
|
||||
|
||||
assign qpllreset = reset_pulse[0];
|
||||
assign gttxreset = reset_pulse[0];
|
||||
assign gtrxreset = reset_pulse[0];
|
||||
|
||||
ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #(
|
||||
.C_NUM_SYNC_REGS(4),
|
||||
.C_RVAL(1'b1)
|
||||
) gttxreset_txusrclk2_sync_i (
|
||||
.clk(txusrclk2),
|
||||
.rst(gttxreset),
|
||||
.data_in(1'b0),
|
||||
.data_out(gttxreset_txusrclk2)
|
||||
);
|
||||
|
||||
always @(posedge txusrclk2 or posedge gttxreset_txusrclk2)
|
||||
begin
|
||||
if(gttxreset_txusrclk2)
|
||||
txuserrdy <= 1'b0;
|
||||
else
|
||||
txuserrdy <= qplllock_txusrclk2;
|
||||
end
|
||||
|
||||
BUFG tx322clk_bufg_i (
|
||||
.I (txclk322),
|
||||
.O (txusrclk)
|
||||
);
|
||||
|
||||
assign txusrclk2 = txusrclk;
|
||||
assign tx_out_clk = txclk322;
|
||||
|
||||
// Instantiate the 10GBASER/KR Block Level
|
||||
ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i (
|
||||
.coreclk(clk156),
|
||||
.dclk(dclk),
|
||||
.rxrecclk_out(),
|
||||
.txusrclk(txusrclk),
|
||||
.txusrclk2(txusrclk2),
|
||||
.txoutclk(txclk322),
|
||||
.areset_coreclk(areset_clk156),
|
||||
.txuserrdy(txuserrdy),
|
||||
.areset(areset),
|
||||
.gttxreset(gttxreset),
|
||||
.gtrxreset(gtrxreset),
|
||||
.sim_speedup_control(sim_speedup_control),
|
||||
.qplllock(qplllock),
|
||||
.qplloutclk(qplloutclk),
|
||||
.qplloutrefclk(qplloutrefclk),
|
||||
.reset_counter_done(reset_counter_done),
|
||||
.xgmii_txd(xgmii_txd_reg),
|
||||
.xgmii_txc(xgmii_txc_reg),
|
||||
.xgmii_rxd(xgmii_rxd_int),
|
||||
.xgmii_rxc(xgmii_rxc_int),
|
||||
.txp(txp),
|
||||
.txn(txn),
|
||||
.rxp(rxp),
|
||||
.rxn(rxn),
|
||||
.mdc(mdc_reg),
|
||||
.mdio_in(mdio_in_reg),
|
||||
.mdio_out(mdio_out_int),
|
||||
.mdio_tri(mdio_tri_int),
|
||||
.prtad(prtad),
|
||||
.core_status(core_status),
|
||||
.tx_resetdone(tx_resetdone_int),
|
||||
.rx_resetdone(rx_resetdone_int),
|
||||
.signal_detect(signal_detect),
|
||||
.tx_fault(tx_fault),
|
||||
.drp_req(drp_req),
|
||||
.drp_gnt(drp_gnt),
|
||||
.drp_den_o(drp_den_o),
|
||||
.drp_dwe_o(drp_dwe_o),
|
||||
.drp_daddr_o(drp_daddr_o),
|
||||
.drp_di_o(drp_di_o),
|
||||
.drp_drdy_o(drp_drdy_o),
|
||||
.drp_drpdo_o(drp_drpdo_o),
|
||||
.drp_den_i(drp_den_i),
|
||||
.drp_dwe_i(drp_dwe_i),
|
||||
.drp_daddr_i(drp_daddr_i),
|
||||
.drp_di_i(drp_di_i),
|
||||
.drp_drdy_i(drp_drdy_i),
|
||||
.drp_drpdo_i(drp_drpdo_i),
|
||||
.pma_pmd_type(3'b101),
|
||||
.tx_disable(tx_disable)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,91 @@
|
||||
## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
create_clock -period 6.400 [get_ports {dclk}]
|
||||
|
||||
create_clock -period 6.400 [get_ports refclk_p]
|
||||
|
||||
create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk]
|
||||
set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}]
|
||||
set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}]
|
||||
set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}]
|
||||
set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}]
|
||||
|
||||
# False paths for async reset removal synchronizers
|
||||
set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}]
|
||||
set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}]
|
||||
|
||||
|
||||
## Sample constraint for GT location
|
||||
#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i]
|
||||
#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i]
|
||||
|
||||
set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}]
|
||||
set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}]
|
||||
|
||||
set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}]
|
||||
set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}]
|
||||
|
||||
set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}]
|
||||
set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}]
|
||||
|
||||
set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk]
|
||||
|
||||
|
||||
##################################################################
|
||||
# MDIO-related constraints #
|
||||
##################################################################
|
||||
set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}]
|
||||
set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}]
|
||||
###################################################################
|
||||
|
||||
##################################################################
|
||||
# MDIO-related constraints #
|
||||
##################################################################
|
||||
set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}]
|
||||
set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}]
|
||||
###################################################################
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
//
|
||||
// Copyright 2008-2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
module ten_gige_phy_clk_gen
|
||||
(
|
||||
input refclk_ibuf,
|
||||
output clk156,
|
||||
output dclk
|
||||
);
|
||||
|
||||
wire dclk_buf;
|
||||
|
||||
BUFG clk156_bufg_inst (
|
||||
.I (refclk_ibuf),
|
||||
.O (clk156)
|
||||
);
|
||||
|
||||
// Dividing independent clock by 2 as source for DRP clock
|
||||
BUFR # (
|
||||
.BUFR_DIVIDE ("2")
|
||||
) dclk_divide_by_2_buf (
|
||||
.I (clk156),
|
||||
.O (dclk_buf),
|
||||
.CE (1'b1),
|
||||
.CLR (1'b0)
|
||||
);
|
||||
|
||||
BUFG dclk_bufg_i (
|
||||
.I (dclk_buf),
|
||||
.O (dclk)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user