Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,45 @@
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#
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# Copyright 2008-2013 Ettus Research LLC
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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ONE_GIGE_PHY_SRCS = \
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$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \
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$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v \
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$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v \
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$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS)
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IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \
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one_gig_eth_pcs_pma_example_design.v \
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one_gig_eth_pcs_pma_reset_sync_ex.v \
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one_gig_eth_pcs_pma_sync_block_ex.v \
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one_gig_eth_pcs_pma_tx_elastic_buffer.v \
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one_gig_eth_pcs_pma_gt_common.v \
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one_gig_eth_pcs_pma_resets.v \
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)
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IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
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IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \
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one_gig_eth_pcs_pma.xci.out \
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synth/one_gig_eth_pcs_pma_block.v \
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synth/one_gig_eth_pcs_pma_reset_sync.v \
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synth/one_gig_eth_pcs_pma.v \
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synth/one_gig_eth_pcs_pma_ooc.xdc \
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synth/one_gig_eth_pcs_pma_sync_block.v \
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synth/one_gig_eth_pcs_pma.xdc \
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synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \
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synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \
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synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \
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synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \
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synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \
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synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \
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synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \
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synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \
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)
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$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS)
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$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
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$(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
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@@ -0,0 +1,353 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>xci</spirit:library>
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<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>one_gig_eth_pcs_pma</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gig_ethernet_pcs_pma" spirit:version="16.1"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT.PortWidth">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT_0.PortWidth">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT_1.PortWidth">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT_2.PortWidth">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125M_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125M_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125M_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA_0.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA_1.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA_2.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT0_PLL0RESET_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_IN.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA_0.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA_1.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA_2.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESET_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK125_IN.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK156_25_IN.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK625_IN.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST_125_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_0_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_1_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_2_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EMAC_IF_TEMAC">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXAMPLE_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_8_or_9_family">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_InstantiateBitslice0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_RxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_RxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_RxNibbleBitslice0Used">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_TxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_TxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_architecture">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_clock_selection">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">one_gig_eth_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_drpclkrate">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dynamic_switching">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_elaboration_transient_dir">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_async_lvds">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_async_lvds_rx_only">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_async_sgmii">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_tx_userclk_reset_port">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_dmonitorout_width">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_drpaddr_width">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_rxmonitorout_width">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_txdiffctrl_width">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_type">GTH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gtinex">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_an">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_axil">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_ext_mdio">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_2_5g">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_sgmii">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_num_of_lanes">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_src">clk0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclkrate">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rx_gmii_clk_src">TXOUTCLK</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sgmii_fabric_buffer">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sgmii_phy_mode">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sub_core_name">one_gig_eth_pcs_pma_gt</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_support_level">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_transceiver_type">GTXE2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_transceivercontrol">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_in_upper_nibble">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_lvds">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_tbi">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_transceiver">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevicefamily">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.characterization">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_rx_byte_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXILite_Interface">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Auto_Negotiation">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ClockSelection">Sync</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">one_gig_eth_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFFCLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DrpClkRate">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMAC_IF_TEMAC">TEMAC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXAMPLE_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EnableAsyncSGMII">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_1588">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_1588_1step">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ext_Management_Interface">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_Location">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_Type">GTH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GTinEx">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.InstantiateBitslice0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LvdsRefClk">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Management_Interface">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MaxDataRate">1G</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NumOfLanes">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Physical_Interface">Transceiver</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkRate">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkSrc">clk0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxGmiiClkSrc">TXOUTCLK</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxNibbleBitslice0Used">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SGMII_Mode">10_100_1000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SGMII_PHY_Mode">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Standard">1000BASEX</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">Include_Shared_Logic_in_Example_Design</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Tx_In_Upper_Nibble">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Auto_Negotiation" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DrpClkRate" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,188 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// File : one_gig_eth_pcs_pma_clocking.v
|
||||
// Author : Xilinx Inc.
|
||||
//------------------------------------------------------------------------------
|
||||
// (c) Copyright 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
// Description: This module holds the Clocking logic for pcs/pma core.
|
||||
|
||||
|
||||
`timescale 1 ps/1 ps
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// The module declaration for the example design
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
module one_gig_eth_pcs_pma_clocking
|
||||
(
|
||||
input txoutclk, // txoutclk from GT transceiver.
|
||||
input rxoutclk, // rxoutclk from GT transceiver.
|
||||
input mmcm_reset, // MMCM Reset
|
||||
output wire mmcm_locked, // MMCM locked
|
||||
|
||||
output userclk, // for GT PMA reference clock
|
||||
output userclk2, // 125MHz clock for core reference clock.
|
||||
output rxuserclk, // for GT PMA reference clock
|
||||
output rxuserclk2 // 125MHz clock for core reference clock.
|
||||
);
|
||||
|
||||
wire clkout0; // MMCM output clock
|
||||
wire clkout1; // MMCM output clock
|
||||
wire clkfbout; // MMCM Feedback clock
|
||||
// Route txoutclk input through a BUFG
|
||||
wire txoutclk_bufg;
|
||||
wire userclk_i;
|
||||
wire rxoutclk_buf;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Transceiver Clock Management
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Route txoutclk input through a BUFG
|
||||
BUFG bufg_txoutclk (
|
||||
.I (txoutclk),
|
||||
.O (txoutclk_bufg)
|
||||
);
|
||||
|
||||
// The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
|
||||
// routed to an MMCM module where it is used to create phase and frequency
|
||||
// related 62.5MHz and 125MHz clock sources
|
||||
MMCME2_ADV # (
|
||||
.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.5),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.5),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (16.0),
|
||||
.CLKFBOUT_MULT_F (16.000),
|
||||
.CLKOUT0_DIVIDE_F (8.000),
|
||||
.CLKOUT1_DIVIDE (16),
|
||||
|
||||
.REF_JITTER1 (0.010)
|
||||
) mmcm_adv_inst (
|
||||
// Output clocks
|
||||
.CLKFBOUT (clkfbout),
|
||||
.CLKFBOUTB (),
|
||||
.CLKOUT0 (clkout0),
|
||||
.CLKOUT0B (),
|
||||
.CLKOUT1 (clkout1),
|
||||
.CLKOUT1B (),
|
||||
.CLKOUT2 (),
|
||||
.CLKOUT2B (),
|
||||
.CLKOUT3 (),
|
||||
.CLKOUT3B (),
|
||||
.CLKOUT4 (),
|
||||
.CLKOUT5 (),
|
||||
.CLKOUT6 (),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout),
|
||||
.CLKIN1 (txoutclk_bufg),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (),
|
||||
.DRDY (),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (),
|
||||
// Other control and status signals
|
||||
.LOCKED (mmcm_locked),
|
||||
.CLKINSTOPPED (),
|
||||
.CLKFBSTOPPED (),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (mmcm_reset)
|
||||
);
|
||||
// This 62.5MHz clock is placed onto global clock routing and is then used
|
||||
// for tranceiver TXUSRCLK/RXUSRCLK.
|
||||
BUFG bufg_userclk (
|
||||
.I (clkout1),
|
||||
.O (userclk_i)
|
||||
);
|
||||
|
||||
|
||||
// This 125MHz clock is placed onto global clock routing and is then used
|
||||
// to clock all Ethernet core logic.
|
||||
BUFG bufg_userclk2 (
|
||||
.I (clkout0),
|
||||
.O (userclk2)
|
||||
);
|
||||
|
||||
|
||||
|
||||
assign userclk = userclk_i;
|
||||
|
||||
|
||||
// Place the Rx recovered clock on a Global Clock Buffer (it may be possible
|
||||
// to switch this for a BUFHCE/BUFR and BUFMR combination)
|
||||
BUFG rxrecclkbufg (
|
||||
.I (rxoutclk),
|
||||
.O (rxoutclk_buf)
|
||||
);
|
||||
|
||||
assign rxuserclk2 = rxoutclk_buf;
|
||||
assign rxuserclk = rxoutclk_buf;
|
||||
|
||||
endmodule // one_gig_eth_pcs_pma_clocking
|
||||
@@ -0,0 +1,238 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// File : one_gig_eth_pcs_pma_support.v
|
||||
// Author : Xilinx Inc.
|
||||
//------------------------------------------------------------------------------
|
||||
// (c) Copyright 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
// Description: This module holds the support level for the pcs/pma core
|
||||
// This can be used as-is in a single core design, or adapted
|
||||
// for use with multi-core implementations
|
||||
|
||||
`timescale 1 ps/1 ps
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// The module declaration for the Core Block wrapper.
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
module one_gig_eth_pcs_pma_support
|
||||
(
|
||||
// Transceiver Interface
|
||||
//----------------------
|
||||
|
||||
|
||||
input gtrefclk, // gtrefclk routed through an IBUFG.
|
||||
input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic.
|
||||
output txp, // Differential +ve of serial transmission from PMA to PMD.
|
||||
output txn, // Differential -ve of serial transmission from PMA to PMD.
|
||||
input rxp, // Differential +ve for serial reception from PMD to PMA.
|
||||
input rxn, // Differential -ve for serial reception from PMD to PMA.
|
||||
output userclk_out,
|
||||
output userclk2_out,
|
||||
output rxuserclk_out,
|
||||
output rxuserclk2_out,
|
||||
input independent_clock_bufg, // Freerun Independent clock,
|
||||
output pma_reset_out, // transceiver PMA reset signal
|
||||
output mmcm_locked_out, // MMCM Locked
|
||||
output resetdone,
|
||||
// GMII Interface
|
||||
//---------------
|
||||
input [7:0] gmii_txd, // Transmit data from client MAC.
|
||||
input gmii_tx_en, // Transmit control signal from client MAC.
|
||||
input gmii_tx_er, // Transmit control signal from client MAC.
|
||||
output [7:0] gmii_rxd, // Received Data to client MAC.
|
||||
output gmii_rx_dv, // Received control signal to client MAC.
|
||||
output gmii_rx_er, // Received control signal to client MAC.
|
||||
output gmii_isolate, // Tristate control to electrically isolate GMII.
|
||||
|
||||
// Management: MDIO Interface
|
||||
//---------------------------
|
||||
|
||||
input mdc, // Management Data Clock
|
||||
input mdio_i, // Management Data In
|
||||
output mdio_o, // Management Data Out
|
||||
output mdio_t, // Management Data Tristate
|
||||
input [4:0] phyaddr, // MDIO address
|
||||
input [4:0] configuration_vector, // Alternative to MDIO interface.
|
||||
input configuration_valid, // Validation signal for Config vector
|
||||
|
||||
// General IO's
|
||||
//-------------
|
||||
output [15:0] status_vector, // Core status.
|
||||
input reset, // Asynchronous reset for entire core.
|
||||
|
||||
input signal_detect, // Input from PMD to indicate presence of optical input.
|
||||
input gt0_qplloutclk_in,
|
||||
input gt0_qplloutrefclk_in
|
||||
|
||||
|
||||
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Internal signals used in this block level wrapper.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Core <=> Transceiver interconnect
|
||||
wire cplllock; // reset done indication from transceiver
|
||||
wire mmcm_reset; // Reset to MMCM based on resetdone
|
||||
wire mmcm_locked; // Signal indicating that MMCM has locked
|
||||
wire pma_reset; // Reset synchronized to system clock
|
||||
wire txoutclk; // txoutclk from GT transceiver (62.5MHz)
|
||||
wire rxoutclk; // txoutclk from GT transceiver (62.5MHz)
|
||||
wire userclk;
|
||||
wire userclk2;
|
||||
wire rxuserclk;
|
||||
wire rxuserclk2;
|
||||
|
||||
// GT Interface
|
||||
//-------------
|
||||
//wire gt0_qplloutclk;
|
||||
//wire gt0_qplloutrefclk;
|
||||
|
||||
one_gig_eth_pcs_pma
|
||||
pcs_pma_i
|
||||
(
|
||||
|
||||
// Transceiver Interface
|
||||
//----------------------
|
||||
|
||||
.gtrefclk (gtrefclk), // Very high quality clock for GT transceiver.
|
||||
.gtrefclk_bufg (gtrefclk_bufg),
|
||||
.txp (txp), // Differential +ve of serial transmission from PMA to PMD.
|
||||
.txn (txn), // Differential -ve of serial transmission from PMA to PMD.
|
||||
.rxp (rxp), // Differential +ve for serial reception from PMD to PMA.
|
||||
.rxn (rxn), // Differential -ve for serial reception from PMD to PMA.
|
||||
|
||||
.txoutclk (txoutclk),
|
||||
.rxoutclk (rxoutclk),
|
||||
.resetdone (resetdone),
|
||||
.cplllock (cplllock),
|
||||
.mmcm_reset (mmcm_reset),
|
||||
.userclk (userclk),
|
||||
.userclk2 (userclk2),
|
||||
.rxuserclk (rxuserclk),
|
||||
.rxuserclk2 (rxuserclk2),
|
||||
.independent_clock_bufg (independent_clock_bufg),
|
||||
.pma_reset (pma_reset),
|
||||
.mmcm_locked (mmcm_locked),
|
||||
|
||||
.gmii_txd (gmii_txd),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_tx_er (gmii_tx_er),
|
||||
.gmii_rxd (gmii_rxd),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rx_er (gmii_rx_er),
|
||||
.gmii_isolate (gmii_isolate),
|
||||
|
||||
// Management: MDIO Interface
|
||||
//---------------------------
|
||||
|
||||
.mdc (mdc),
|
||||
.mdio_i (mdio_i),
|
||||
.mdio_o (mdio_o),
|
||||
.mdio_t (mdio_t),
|
||||
.phyaddr (phyaddr),
|
||||
.configuration_vector (configuration_vector),
|
||||
.configuration_valid (configuration_valid),
|
||||
|
||||
|
||||
// General IO's
|
||||
//-------------
|
||||
.status_vector (status_vector), // Core status.
|
||||
.reset (pma_reset), // Asynchronous reset for entire core.
|
||||
|
||||
.signal_detect (signal_detect) , // Input from PMD to indicate presence of optical input.
|
||||
.gt0_qplloutclk_in (gt0_qplloutclk_in),
|
||||
.gt0_qplloutrefclk_in (gt0_qplloutrefclk_in)
|
||||
);
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Instantiate the clocking module.
|
||||
//----------------------------------------------------------------------------
|
||||
one_gig_eth_pcs_pma_clocking core_clocking_i
|
||||
(
|
||||
.txoutclk (txoutclk),
|
||||
.rxoutclk (rxoutclk),
|
||||
.mmcm_reset (mmcm_reset),
|
||||
.mmcm_locked (mmcm_locked),
|
||||
.userclk (userclk),
|
||||
.userclk2 (userclk2),
|
||||
.rxuserclk (rxuserclk),
|
||||
.rxuserclk2 (rxuserclk2)
|
||||
);
|
||||
|
||||
assign gtrefclk_out = gtrefclk;
|
||||
assign gtrefclk_bufg_out = gtrefclk_bufg;
|
||||
assign userclk_out = userclk;
|
||||
assign userclk2_out = userclk2;
|
||||
assign rxuserclk_out = rxuserclk;
|
||||
assign rxuserclk2_out = rxuserclk2;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Transceiver PMA reset circuitry
|
||||
//---------------------------------------------------------------------------
|
||||
one_gig_eth_pcs_pma_resets core_resets_i
|
||||
(
|
||||
.reset (reset),
|
||||
.independent_clock_bufg (independent_clock_bufg),
|
||||
|
||||
.pma_reset (pma_reset)
|
||||
);
|
||||
|
||||
assign pma_reset_out = pma_reset;
|
||||
|
||||
|
||||
assign mmcm_locked_out = mmcm_locked;
|
||||
|
||||
endmodule // one_gig_eth_pcs_pma_support
|
||||
|
||||
@@ -0,0 +1,105 @@
|
||||
//
|
||||
// Copyright 2014 Ettus Research LLC
|
||||
//
|
||||
|
||||
module one_gige_phy
|
||||
(
|
||||
input independent_clock,
|
||||
input gt0_qplloutclk_in,
|
||||
input gt0_qplloutrefclk_in,
|
||||
|
||||
// Tranceiver Interface
|
||||
//---------------------
|
||||
input gtrefclk, // Reference clock for MGT: 125MHz, very high quality.
|
||||
input gtrefclk_bufg, // Reference clock routed through a BUFG
|
||||
output txp, // Differential +ve of serial transmission from PMA to PMD.
|
||||
output txn, // Differential -ve of serial transmission from PMA to PMD.
|
||||
input rxp, // Differential +ve for serial reception from PMD to PMA.
|
||||
input rxn, // Differential -ve for serial reception from PMD to PMA.
|
||||
|
||||
// GMII Interface (client MAC <=> PCS)
|
||||
//------------------------------------
|
||||
output gmii_clk, // Receive clock to client MAC.
|
||||
input [7:0] gmii_txd, // Transmit data from client MAC.
|
||||
input gmii_tx_en, // Transmit control signal from client MAC.
|
||||
input gmii_tx_er, // Transmit control signal from client MAC.
|
||||
output reg [7:0] gmii_rxd, // Received Data to client MAC.
|
||||
output reg gmii_rx_dv, // Received control signal to client MAC.
|
||||
output reg gmii_rx_er, // Received control signal to client MAC.
|
||||
|
||||
// Management: MDIO Interface
|
||||
//---------------------------
|
||||
input mdc, // Management Data Clock
|
||||
input mdio_i, // Management Data In
|
||||
output mdio_o, // Management Data Out
|
||||
output mdio_t, // Management Data Tristate
|
||||
input [4:0] phyaddr, // MDIO PHY Address
|
||||
input [4:0] configuration_vector, // Alternative to MDIO interface.
|
||||
input configuration_valid, // Validation signal for Config vector
|
||||
|
||||
// General IO's
|
||||
//-------------
|
||||
output [15:0] status_vector, // Core status.
|
||||
input reset, // Asynchronous reset for entire core.
|
||||
input signal_detect, // Input from PMD to indicate presence of optical input.
|
||||
output pma_reset_out
|
||||
);
|
||||
|
||||
wire resetdone; // To indicate that the GT transceiver has completed its reset cycle
|
||||
wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks
|
||||
wire userclk2; // 125MHz clock for core reference clock.
|
||||
wire rxuserclk2;
|
||||
wire gmii_isolate; // internal gmii_isolate signal.
|
||||
|
||||
wire [7:0] gmii_rxd_int;
|
||||
wire gmii_rx_dv_int;
|
||||
wire gmii_rx_er_int;
|
||||
|
||||
always @(posedge gmii_clk) begin
|
||||
gmii_rxd <= gmii_rxd_int;
|
||||
gmii_rx_dv <= gmii_rx_dv_int;
|
||||
gmii_rx_er <= gmii_rx_er_int;
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Instantiate core wrapper
|
||||
//----------------------------------------------------------------------------
|
||||
one_gig_eth_pcs_pma_support core_support_i (
|
||||
.gtrefclk (gtrefclk),
|
||||
.gtrefclk_bufg (gtrefclk_bufg),
|
||||
.txp (txp),
|
||||
.txn (txn),
|
||||
.rxp (rxp),
|
||||
.rxn (rxn),
|
||||
.mmcm_locked_out (),
|
||||
.userclk_out (userclk),
|
||||
.userclk2_out (userclk2),
|
||||
.rxuserclk_out (),
|
||||
.rxuserclk2_out (rxuserclk2),
|
||||
.independent_clock_bufg(independent_clock),
|
||||
.pma_reset_out (pma_reset_out),
|
||||
.resetdone (resetdone),
|
||||
.gmii_txd (gmii_txd),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_tx_er (gmii_tx_er),
|
||||
.gmii_rxd (gmii_rxd_int),
|
||||
.gmii_rx_dv (gmii_rx_dv_int),
|
||||
.gmii_rx_er (gmii_rx_er_int),
|
||||
.gmii_isolate (gmii_isolate),
|
||||
.mdc (mdc),
|
||||
.mdio_i (mdio_i),
|
||||
.mdio_o (mdio_o),
|
||||
.mdio_t (mdio_t),
|
||||
.phyaddr (phyaddr),
|
||||
.configuration_vector (configuration_vector),
|
||||
.configuration_valid (configuration_valid),
|
||||
.status_vector (status_vector),
|
||||
.reset (reset),
|
||||
.signal_detect (signal_detect),
|
||||
.gt0_qplloutclk_in (gt0_qplloutclk_in),
|
||||
.gt0_qplloutrefclk_in (gt0_qplloutrefclk_in)
|
||||
);
|
||||
|
||||
assign gmii_clk = userclk2;
|
||||
|
||||
endmodule // one_gige_phy
|
||||
@@ -0,0 +1,164 @@
|
||||
|
||||
|
||||
#***********************************************************
|
||||
# The following constraints target the Transceiver Physical*
|
||||
# Interface which is instantiated in the Example Design. *
|
||||
#***********************************************************
|
||||
#-----------------------------------------------------------
|
||||
# Transceiver I/O placement: -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
|
||||
# Place the transceiver components, chosen for this example design
|
||||
# *** These values should be modified according to your specific design ***
|
||||
|
||||
#set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i]
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# Clock source used for the IDELAY Controller (if present) -
|
||||
# and for the transceiver reset circuitry -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
|
||||
create_clock -name independent_clock -period 5.000 [get_ports independent_clock]
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# PCS/PMA Clock period Constraints: please do not relax -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p]
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# Transceiver I/O placement: -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
# Place the transceiver components, chosen for this example design
|
||||
# *** These values should be modified according to your specific design ***
|
||||
|
||||
#set_property LOC H6 [get_ports gtrefclk_p]
|
||||
#set_property LOC H5 [get_ports gtrefclk_n]
|
||||
|
||||
|
||||
#***********************************************************
|
||||
# The following constraints target the GMII implemented in *
|
||||
# the Example Design. *
|
||||
#***********************************************************
|
||||
# If the GMII is intended to be an internal interface, *
|
||||
# the GMII signals can be connected directly to user *
|
||||
# logic and all of the following constraints in this file *
|
||||
# should be removed. *
|
||||
# *
|
||||
# If the GMII is intended to be an external interface, *
|
||||
# all of the following constraints in this file should be *
|
||||
# maintained. *
|
||||
#***********************************************************
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# GMII IOSTANDARD Constraints: please select an I/O -
|
||||
# Standard (LVTTL is suggested). -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
# Please update the IOSTANDARD according to that available in the device
|
||||
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er]
|
||||
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er]
|
||||
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk]
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# Lock down the GMII Tx signals to the same bank for low -
|
||||
# skew. This is an example placement only. -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# To Adjust GMII Tx Input Setup/Hold Timing -
|
||||
#-----------------------------------------------------------
|
||||
# These constraints will be set at a later date when device speed files have matured
|
||||
|
||||
#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en]
|
||||
#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er]
|
||||
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}]
|
||||
#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}]
|
||||
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# To check (analyze) GMII Tx Input Setup/Hold Timing -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk]
|
||||
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# Fast Skew maximises output setup and hold timing -
|
||||
#-----------------------------------------------------------
|
||||
set_property SLEW FAST [get_ports {gmii_rxd[*]}]
|
||||
set_property SLEW FAST [get_ports gmii_rx_dv]
|
||||
set_property SLEW FAST [get_ports gmii_rx_er]
|
||||
set_property SLEW FAST [get_ports gmii_rx_clk]
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# GMII Transmitter Constraints: place flip-flops in IOB -
|
||||
#-----------------------------------------------------------
|
||||
#set_property IOB TRUE [get_cells gmii_txd_IBUF*]
|
||||
#set_property IOB TRUE [get_cells gmii_tx_en_IBUF*]
|
||||
#set_property IOB TRUE [get_cells gmii_tx_er_IBUF*]
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# GMII Receiver Constraints: place flip-flops in IOB -
|
||||
#-----------------------------------------------------------
|
||||
#set_property IOB TRUE [get_cells gmii_rxd_obuf_reg*]
|
||||
#set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg]
|
||||
#set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg]
|
||||
|
||||
|
||||
|
||||
#-----------------------------------------------------------
|
||||
# GMII Tx Elastic Buffer Constraints -
|
||||
#-----------------------------------------------------------
|
||||
|
||||
# Control Gray Code delay and skew across clock boundary
|
||||
set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}]
|
||||
set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}]
|
||||
|
||||
# Constrain between Distributed Memory (output data) and the 1st set of flip-flops
|
||||
set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1*/D}]
|
||||
set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1*/D}]
|
||||
set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*/D}]
|
||||
|
||||
set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
|
||||
|
||||
set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}]
|
||||
set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
|
||||
Reference in New Issue
Block a user