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Merge FPGA repository back into UHD repository

Browse Source 
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
2020-01-28 09:35:36 -08:00
co-authored by Alex Williams Andrej Rode Ashish Chaudhari Ben Hilburn Ciro Nishiguchi Daniel Jepson Derek Kozel EJ Kreinar Humberto Jimenez Ian Buckley Jörg Hofrichter Jon Kiser Josh Blum Jonathon Pendlum Matt Ettus Michael West Moritz Fischer Nick Foster Nicolas Cuervo Paul Butler Paul David Ryan Marlow Sugandha Gupta Sylvain Munaut Trung Tran Vidush Vishwanath Wade Fife
parent 74893643ca
commit 6b67702ad7
2157 changed files with 1282567 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc
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#
# Copyright 2016 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTERCON_4X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v
BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \
axi_intercon_4x64_256_bd.bd.out \
axi_intercon_4x64_256_bd_ooc.xdc \
)
$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd
$(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd
+2191
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top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
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<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="axi_intercon_4x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/axi_intercon_4x64_256_bd_m00_rs_0/axi_intercon_4x64_256_bd_m00_rs_0.xci" Type="IP">
<Instance HierarchyPath="m00_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s00_rs_0/axi_intercon_4x64_256_bd_s00_rs_0.xci" Type="IP">
<Instance HierarchyPath="s00_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s00_width_conv_0/axi_intercon_4x64_256_bd_s00_width_conv_0.xci" Type="IP">
<Instance HierarchyPath="s00_width_conv"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s01_rs_0/axi_intercon_4x64_256_bd_s01_rs_0.xci" Type="IP">
<Instance HierarchyPath="s01_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s01_width_conv_0/axi_intercon_4x64_256_bd_s01_width_conv_0.xci" Type="IP">
<Instance HierarchyPath="s01_width_conv"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_xbar_0/axi_intercon_4x64_256_bd_xbar_0.xci" Type="IP">
<Instance HierarchyPath="xbar"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s01_rs_256_0/axi_intercon_4x64_256_bd_s01_rs_256_0.xci" Type="IP">
<Instance HierarchyPath="s01_rs_256"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s00_rs_256_0/axi_intercon_4x64_256_bd_s00_rs_256_0.xci" Type="IP">
<Instance HierarchyPath="s00_rs_256"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s02_rs_0/axi_intercon_4x64_256_bd_s02_rs_0.xci" Type="IP">
<Instance HierarchyPath="s02_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s03_rs_0/axi_intercon_4x64_256_bd_s03_rs_0.xci" Type="IP">
<Instance HierarchyPath="s03_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s02_width_conv_0/axi_intercon_4x64_256_bd_s02_width_conv_0.xci" Type="IP">
<Instance HierarchyPath="s02_width_conv"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s03_width_conv_0/axi_intercon_4x64_256_bd_s03_width_conv_0.xci" Type="IP">
<Instance HierarchyPath="s03_width_conv"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s03_rs_256_0/axi_intercon_4x64_256_bd_s03_rs_256_0.xci" Type="IP">
<Instance HierarchyPath="s03_rs_256"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_4x64_256_bd_s02_rs_256_0/axi_intercon_4x64_256_bd_s02_rs_256_0.xci" Type="IP">
<Instance HierarchyPath="s02_rs_256"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v
+419
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//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
`timescale 1 ps / 1 ps
module axi_intercon_4x64_256_bd_wrapper (
input M00_AXI_ACLK,
input M00_AXI_ARESETN,
output [31:0]M00_AXI_ARADDR,
output [1:0]M00_AXI_ARBURST,
output [3:0]M00_AXI_ARCACHE,
output [3:0]M00_AXI_ARID,
output [7:0]M00_AXI_ARLEN,
output [0:0]M00_AXI_ARLOCK,
output [2:0]M00_AXI_ARPROT,
output [3:0]M00_AXI_ARQOS,
input M00_AXI_ARREADY,
output [3:0]M00_AXI_ARREGION,
output [2:0]M00_AXI_ARSIZE,
output M00_AXI_ARVALID,
output [31:0]M00_AXI_AWADDR,
output [1:0]M00_AXI_AWBURST,
output [3:0]M00_AXI_AWCACHE,
output [3:0]M00_AXI_AWID,
output [7:0]M00_AXI_AWLEN,
output [0:0]M00_AXI_AWLOCK,
output [2:0]M00_AXI_AWPROT,
output [3:0]M00_AXI_AWQOS,
input M00_AXI_AWREADY,
output [3:0]M00_AXI_AWREGION,
output [2:0]M00_AXI_AWSIZE,
output M00_AXI_AWVALID,
input [3:0]M00_AXI_BID,
output M00_AXI_BREADY,
input [1:0]M00_AXI_BRESP,
input M00_AXI_BVALID,
input [255:0]M00_AXI_RDATA,
input [3:0]M00_AXI_RID,
input M00_AXI_RLAST,
output M00_AXI_RREADY,
input [1:0]M00_AXI_RRESP,
input M00_AXI_RVALID,
output [255:0]M00_AXI_WDATA,
output M00_AXI_WLAST,
input M00_AXI_WREADY,
output [31:0]M00_AXI_WSTRB,
output M00_AXI_WVALID,
input S00_AXI_ACLK,
input S00_AXI_ARESETN,
input [31:0]S00_AXI_ARADDR,
input [1:0]S00_AXI_ARBURST,
input [3:0]S00_AXI_ARCACHE,
input [0:0]S00_AXI_ARID,
input [7:0]S00_AXI_ARLEN,
input [0:0]S00_AXI_ARLOCK,
input [2:0]S00_AXI_ARPROT,
input [3:0]S00_AXI_ARQOS,
output S00_AXI_ARREADY,
input [3:0]S00_AXI_ARREGION,
input [2:0]S00_AXI_ARSIZE,
input S00_AXI_ARVALID,
input [31:0]S00_AXI_AWADDR,
input [1:0]S00_AXI_AWBURST,
input [3:0]S00_AXI_AWCACHE,
input [0:0]S00_AXI_AWID,
input [7:0]S00_AXI_AWLEN,
input [0:0]S00_AXI_AWLOCK,
input [2:0]S00_AXI_AWPROT,
input [3:0]S00_AXI_AWQOS,
output S00_AXI_AWREADY,
input [3:0]S00_AXI_AWREGION,
input [2:0]S00_AXI_AWSIZE,
input S00_AXI_AWVALID,
output [0:0]S00_AXI_BID,
input S00_AXI_BREADY,
output [1:0]S00_AXI_BRESP,
output S00_AXI_BVALID,
output [63:0]S00_AXI_RDATA,
output [0:0]S00_AXI_RID,
output S00_AXI_RLAST,
input S00_AXI_RREADY,
output [1:0]S00_AXI_RRESP,
output S00_AXI_RVALID,
input [63:0]S00_AXI_WDATA,
input S00_AXI_WLAST,
output S00_AXI_WREADY,
input [7:0]S00_AXI_WSTRB,
input S00_AXI_WVALID,
input S01_AXI_ACLK,
input S01_AXI_ARESETN,
input [31:0]S01_AXI_ARADDR,
input [1:0]S01_AXI_ARBURST,
input [3:0]S01_AXI_ARCACHE,
input [0:0]S01_AXI_ARID,
input [7:0]S01_AXI_ARLEN,
input [0:0]S01_AXI_ARLOCK,
input [2:0]S01_AXI_ARPROT,
input [3:0]S01_AXI_ARQOS,
output S01_AXI_ARREADY,
input [3:0]S01_AXI_ARREGION,
input [2:0]S01_AXI_ARSIZE,
input S01_AXI_ARVALID,
input [31:0]S01_AXI_AWADDR,
input [1:0]S01_AXI_AWBURST,
input [3:0]S01_AXI_AWCACHE,
input [0:0]S01_AXI_AWID,
input [7:0]S01_AXI_AWLEN,
input [0:0]S01_AXI_AWLOCK,
input [2:0]S01_AXI_AWPROT,
input [3:0]S01_AXI_AWQOS,
output S01_AXI_AWREADY,
input [3:0]S01_AXI_AWREGION,
input [2:0]S01_AXI_AWSIZE,
input S01_AXI_AWVALID,
output [0:0]S01_AXI_BID,
input S01_AXI_BREADY,
output [1:0]S01_AXI_BRESP,
output S01_AXI_BVALID,
output [63:0]S01_AXI_RDATA,
output [0:0]S01_AXI_RID,
output S01_AXI_RLAST,
input S01_AXI_RREADY,
output [1:0]S01_AXI_RRESP,
output S01_AXI_RVALID,
input [63:0]S01_AXI_WDATA,
input S01_AXI_WLAST,
output S01_AXI_WREADY,
input [7:0]S01_AXI_WSTRB,
input S01_AXI_WVALID,
input S02_AXI_ACLK,
input S02_AXI_ARESETN,
input [31:0]S02_AXI_ARADDR,
input [1:0]S02_AXI_ARBURST,
input [3:0]S02_AXI_ARCACHE,
input [0:0]S02_AXI_ARID,
input [7:0]S02_AXI_ARLEN,
input [0:0]S02_AXI_ARLOCK,
input [2:0]S02_AXI_ARPROT,
input [3:0]S02_AXI_ARQOS,
output S02_AXI_ARREADY,
input [3:0]S02_AXI_ARREGION,
input [2:0]S02_AXI_ARSIZE,
input S02_AXI_ARVALID,
input [31:0]S02_AXI_AWADDR,
input [1:0]S02_AXI_AWBURST,
input [3:0]S02_AXI_AWCACHE,
input [0:0]S02_AXI_AWID,
input [7:0]S02_AXI_AWLEN,
input [0:0]S02_AXI_AWLOCK,
input [2:0]S02_AXI_AWPROT,
input [3:0]S02_AXI_AWQOS,
output S02_AXI_AWREADY,
input [3:0]S02_AXI_AWREGION,
input [2:0]S02_AXI_AWSIZE,
input S02_AXI_AWVALID,
output [0:0]S02_AXI_BID,
input S02_AXI_BREADY,
output [1:0]S02_AXI_BRESP,
output S02_AXI_BVALID,
output [63:0]S02_AXI_RDATA,
output [0:0]S02_AXI_RID,
output S02_AXI_RLAST,
input S02_AXI_RREADY,
output [1:0]S02_AXI_RRESP,
output S02_AXI_RVALID,
input [63:0]S02_AXI_WDATA,
input S02_AXI_WLAST,
output S02_AXI_WREADY,
input [7:0]S02_AXI_WSTRB,
input S02_AXI_WVALID,
input S03_AXI_ACLK,
input S03_AXI_ARESETN,
input [31:0]S03_AXI_ARADDR,
input [1:0]S03_AXI_ARBURST,
input [3:0]S03_AXI_ARCACHE,
input [0:0]S03_AXI_ARID,
input [7:0]S03_AXI_ARLEN,
input [0:0]S03_AXI_ARLOCK,
input [2:0]S03_AXI_ARPROT,
input [3:0]S03_AXI_ARQOS,
output S03_AXI_ARREADY,
input [3:0]S03_AXI_ARREGION,
input [2:0]S03_AXI_ARSIZE,
input S03_AXI_ARVALID,
input [31:0]S03_AXI_AWADDR,
input [1:0]S03_AXI_AWBURST,
input [3:0]S03_AXI_AWCACHE,
input [0:0]S03_AXI_AWID,
input [7:0]S03_AXI_AWLEN,
input [0:0]S03_AXI_AWLOCK,
input [2:0]S03_AXI_AWPROT,
input [3:0]S03_AXI_AWQOS,
output S03_AXI_AWREADY,
input [3:0]S03_AXI_AWREGION,
input [2:0]S03_AXI_AWSIZE,
input S03_AXI_AWVALID,
output [0:0]S03_AXI_BID,
input S03_AXI_BREADY,
output [1:0]S03_AXI_BRESP,
output S03_AXI_BVALID,
output [63:0]S03_AXI_RDATA,
output [0:0]S03_AXI_RID,
output S03_AXI_RLAST,
input S03_AXI_RREADY,
output [1:0]S03_AXI_RRESP,
output S03_AXI_RVALID,
input [63:0]S03_AXI_WDATA,
input S03_AXI_WLAST,
output S03_AXI_WREADY,
input [7:0]S03_AXI_WSTRB,
input S03_AXI_WVALID
);
axi_intercon_4x64_256_bd axi_intercon_4x64_256_bd_i (
.M00_AXI_ACLK(M00_AXI_ACLK),
.M00_AXI_ARESETN(M00_AXI_ARESETN),
.M00_AXI_araddr(M00_AXI_ARADDR),
.M00_AXI_arburst(M00_AXI_ARBURST),
.M00_AXI_arcache(M00_AXI_ARCACHE),
.M00_AXI_arid(M00_AXI_ARID),
.M00_AXI_arlen(M00_AXI_ARLEN),
.M00_AXI_arlock(M00_AXI_ARLOCK),
.M00_AXI_arprot(M00_AXI_ARPROT),
.M00_AXI_arqos(M00_AXI_ARQOS),
.M00_AXI_arready(M00_AXI_ARREADY),
.M00_AXI_arregion(M00_AXI_ARREGION),
.M00_AXI_arsize(M00_AXI_ARSIZE),
.M00_AXI_arvalid(M00_AXI_ARVALID),
.M00_AXI_awaddr(M00_AXI_AWADDR),
.M00_AXI_awburst(M00_AXI_AWBURST),
.M00_AXI_awcache(M00_AXI_AWCACHE),
.M00_AXI_awid(M00_AXI_AWID),
.M00_AXI_awlen(M00_AXI_AWLEN),
.M00_AXI_awlock(M00_AXI_AWLOCK),
.M00_AXI_awprot(M00_AXI_AWPROT),
.M00_AXI_awqos(M00_AXI_AWQOS),
.M00_AXI_awready(M00_AXI_AWREADY),
.M00_AXI_awregion(M00_AXI_AWREGION),
.M00_AXI_awsize(M00_AXI_AWSIZE),
.M00_AXI_awvalid(M00_AXI_AWVALID),
.M00_AXI_bid(M00_AXI_BID),
.M00_AXI_bready(M00_AXI_BREADY),
.M00_AXI_bresp(M00_AXI_BRESP),
.M00_AXI_bvalid(M00_AXI_BVALID),
.M00_AXI_rdata(M00_AXI_RDATA),
.M00_AXI_rid(M00_AXI_RID),
.M00_AXI_rlast(M00_AXI_RLAST),
.M00_AXI_rready(M00_AXI_RREADY),
.M00_AXI_rresp(M00_AXI_RRESP),
.M00_AXI_rvalid(M00_AXI_RVALID),
.M00_AXI_wdata(M00_AXI_WDATA),
.M00_AXI_wlast(M00_AXI_WLAST),
.M00_AXI_wready(M00_AXI_WREADY),
.M00_AXI_wstrb(M00_AXI_WSTRB),
.M00_AXI_wvalid(M00_AXI_WVALID),
.S00_AXI_ACLK(S00_AXI_ACLK),
.S00_AXI_ARESETN(S00_AXI_ARESETN),
.S00_AXI_araddr(S00_AXI_ARADDR),
.S00_AXI_arburst(S00_AXI_ARBURST),
.S00_AXI_arcache(S00_AXI_ARCACHE),
.S00_AXI_arid(S00_AXI_ARID),
.S00_AXI_arlen(S00_AXI_ARLEN),
.S00_AXI_arlock(S00_AXI_ARLOCK),
.S00_AXI_arprot(S00_AXI_ARPROT),
.S00_AXI_arqos(S00_AXI_ARQOS),
.S00_AXI_arready(S00_AXI_ARREADY),
.S00_AXI_arregion(S00_AXI_ARREGION),
.S00_AXI_arsize(S00_AXI_ARSIZE),
.S00_AXI_arvalid(S00_AXI_ARVALID),
.S00_AXI_awaddr(S00_AXI_AWADDR),
.S00_AXI_awburst(S00_AXI_AWBURST),
.S00_AXI_awcache(S00_AXI_AWCACHE),
.S00_AXI_awid(S00_AXI_AWID),
.S00_AXI_awlen(S00_AXI_AWLEN),
.S00_AXI_awlock(S00_AXI_AWLOCK),
.S00_AXI_awprot(S00_AXI_AWPROT),
.S00_AXI_awqos(S00_AXI_AWQOS),
.S00_AXI_awready(S00_AXI_AWREADY),
.S00_AXI_awregion(S00_AXI_AWREGION),
.S00_AXI_awsize(S00_AXI_AWSIZE),
.S00_AXI_awvalid(S00_AXI_AWVALID),
.S00_AXI_bid(S00_AXI_BID),
.S00_AXI_bready(S00_AXI_BREADY),
.S00_AXI_bresp(S00_AXI_BRESP),
.S00_AXI_bvalid(S00_AXI_BVALID),
.S00_AXI_rdata(S00_AXI_RDATA),
.S00_AXI_rid(S00_AXI_RID),
.S00_AXI_rlast(S00_AXI_RLAST),
.S00_AXI_rready(S00_AXI_RREADY),
.S00_AXI_rresp(S00_AXI_RRESP),
.S00_AXI_rvalid(S00_AXI_RVALID),
.S00_AXI_wdata(S00_AXI_WDATA),
.S00_AXI_wlast(S00_AXI_WLAST),
.S00_AXI_wready(S00_AXI_WREADY),
.S00_AXI_wstrb(S00_AXI_WSTRB),
.S00_AXI_wvalid(S00_AXI_WVALID),
.S01_AXI_ACLK(S01_AXI_ACLK),
.S01_AXI_ARESETN(S01_AXI_ARESETN),
.S01_AXI_araddr(S01_AXI_ARADDR),
.S01_AXI_arburst(S01_AXI_ARBURST),
.S01_AXI_arcache(S01_AXI_ARCACHE),
.S01_AXI_arid(S01_AXI_ARID),
.S01_AXI_arlen(S01_AXI_ARLEN),
.S01_AXI_arlock(S01_AXI_ARLOCK),
.S01_AXI_arprot(S01_AXI_ARPROT),
.S01_AXI_arqos(S01_AXI_ARQOS),
.S01_AXI_arready(S01_AXI_ARREADY),
.S01_AXI_arregion(S01_AXI_ARREGION),
.S01_AXI_arsize(S01_AXI_ARSIZE),
.S01_AXI_arvalid(S01_AXI_ARVALID),
.S01_AXI_awaddr(S01_AXI_AWADDR),
.S01_AXI_awburst(S01_AXI_AWBURST),
.S01_AXI_awcache(S01_AXI_AWCACHE),
.S01_AXI_awid(S01_AXI_AWID),
.S01_AXI_awlen(S01_AXI_AWLEN),
.S01_AXI_awlock(S01_AXI_AWLOCK),
.S01_AXI_awprot(S01_AXI_AWPROT),
.S01_AXI_awqos(S01_AXI_AWQOS),
.S01_AXI_awready(S01_AXI_AWREADY),
.S01_AXI_awregion(S01_AXI_AWREGION),
.S01_AXI_awsize(S01_AXI_AWSIZE),
.S01_AXI_awvalid(S01_AXI_AWVALID),
.S01_AXI_bid(S01_AXI_BID),
.S01_AXI_bready(S01_AXI_BREADY),
.S01_AXI_bresp(S01_AXI_BRESP),
.S01_AXI_bvalid(S01_AXI_BVALID),
.S01_AXI_rdata(S01_AXI_RDATA),
.S01_AXI_rid(S01_AXI_RID),
.S01_AXI_rlast(S01_AXI_RLAST),
.S01_AXI_rready(S01_AXI_RREADY),
.S01_AXI_rresp(S01_AXI_RRESP),
.S01_AXI_rvalid(S01_AXI_RVALID),
.S01_AXI_wdata(S01_AXI_WDATA),
.S01_AXI_wlast(S01_AXI_WLAST),
.S01_AXI_wready(S01_AXI_WREADY),
.S01_AXI_wstrb(S01_AXI_WSTRB),
.S01_AXI_wvalid(S01_AXI_WVALID),
.S02_AXI_ACLK(S02_AXI_ACLK),
.S02_AXI_ARESETN(S02_AXI_ARESETN),
.S02_AXI_araddr(S02_AXI_ARADDR),
.S02_AXI_arburst(S02_AXI_ARBURST),
.S02_AXI_arcache(S02_AXI_ARCACHE),
.S02_AXI_arid(S02_AXI_ARID),
.S02_AXI_arlen(S02_AXI_ARLEN),
.S02_AXI_arlock(S02_AXI_ARLOCK),
.S02_AXI_arprot(S02_AXI_ARPROT),
.S02_AXI_arqos(S02_AXI_ARQOS),
.S02_AXI_arready(S02_AXI_ARREADY),
.S02_AXI_arregion(S02_AXI_ARREGION),
.S02_AXI_arsize(S02_AXI_ARSIZE),
.S02_AXI_arvalid(S02_AXI_ARVALID),
.S02_AXI_awaddr(S02_AXI_AWADDR),
.S02_AXI_awburst(S02_AXI_AWBURST),
.S02_AXI_awcache(S02_AXI_AWCACHE),
.S02_AXI_awid(S02_AXI_AWID),
.S02_AXI_awlen(S02_AXI_AWLEN),
.S02_AXI_awlock(S02_AXI_AWLOCK),
.S02_AXI_awprot(S02_AXI_AWPROT),
.S02_AXI_awqos(S02_AXI_AWQOS),
.S02_AXI_awready(S02_AXI_AWREADY),
.S02_AXI_awregion(S02_AXI_AWREGION),
.S02_AXI_awsize(S02_AXI_AWSIZE),
.S02_AXI_awvalid(S02_AXI_AWVALID),
.S02_AXI_bid(S02_AXI_BID),
.S02_AXI_bready(S02_AXI_BREADY),
.S02_AXI_bresp(S02_AXI_BRESP),
.S02_AXI_bvalid(S02_AXI_BVALID),
.S02_AXI_rdata(S02_AXI_RDATA),
.S02_AXI_rid(S02_AXI_RID),
.S02_AXI_rlast(S02_AXI_RLAST),
.S02_AXI_rready(S02_AXI_RREADY),
.S02_AXI_rresp(S02_AXI_RRESP),
.S02_AXI_rvalid(S02_AXI_RVALID),
.S02_AXI_wdata(S02_AXI_WDATA),
.S02_AXI_wlast(S02_AXI_WLAST),
.S02_AXI_wready(S02_AXI_WREADY),
.S02_AXI_wstrb(S02_AXI_WSTRB),
.S02_AXI_wvalid(S02_AXI_WVALID),
.S03_AXI_ACLK(S03_AXI_ACLK),
.S03_AXI_ARESETN(S03_AXI_ARESETN),
.S03_AXI_araddr(S03_AXI_ARADDR),
.S03_AXI_arburst(S03_AXI_ARBURST),
.S03_AXI_arcache(S03_AXI_ARCACHE),
.S03_AXI_arid(S03_AXI_ARID),
.S03_AXI_arlen(S03_AXI_ARLEN),
.S03_AXI_arlock(S03_AXI_ARLOCK),
.S03_AXI_arprot(S03_AXI_ARPROT),
.S03_AXI_arqos(S03_AXI_ARQOS),
.S03_AXI_arready(S03_AXI_ARREADY),
.S03_AXI_arregion(S03_AXI_ARREGION),
.S03_AXI_arsize(S03_AXI_ARSIZE),
.S03_AXI_arvalid(S03_AXI_ARVALID),
.S03_AXI_awaddr(S03_AXI_AWADDR),
.S03_AXI_awburst(S03_AXI_AWBURST),
.S03_AXI_awcache(S03_AXI_AWCACHE),
.S03_AXI_awid(S03_AXI_AWID),
.S03_AXI_awlen(S03_AXI_AWLEN),
.S03_AXI_awlock(S03_AXI_AWLOCK),
.S03_AXI_awprot(S03_AXI_AWPROT),
.S03_AXI_awqos(S03_AXI_AWQOS),
.S03_AXI_awready(S03_AXI_AWREADY),
.S03_AXI_awregion(S03_AXI_AWREGION),
.S03_AXI_awsize(S03_AXI_AWSIZE),
.S03_AXI_awvalid(S03_AXI_AWVALID),
.S03_AXI_bid(S03_AXI_BID),
.S03_AXI_bready(S03_AXI_BREADY),
.S03_AXI_bresp(S03_AXI_BRESP),
.S03_AXI_bvalid(S03_AXI_BVALID),
.S03_AXI_rdata(S03_AXI_RDATA),
.S03_AXI_rid(S03_AXI_RID),
.S03_AXI_rlast(S03_AXI_RLAST),
.S03_AXI_rready(S03_AXI_RREADY),
.S03_AXI_rresp(S03_AXI_RRESP),
.S03_AXI_rvalid(S03_AXI_RVALID),
.S03_AXI_wdata(S03_AXI_WDATA),
.S03_AXI_wlast(S03_AXI_WLAST),
.S03_AXI_wready(S03_AXI_WREADY),
.S03_AXI_wstrb(S03_AXI_WSTRB),
.S03_AXI_wvalid(S03_AXI_WVALID)
);
endmodule