Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,17 @@
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#
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# Copyright 2016 Ettus Research
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_AXI_INTERCON_2X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd \
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$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml \
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$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v
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BD_AXI_INTERCON_2X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \
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axi_intercon_2x64_256_bd.bd.out \
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axi_intercon_2x64_256_bd_ooc.xdc \
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)
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$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(IP_AXI_INTERCON_2X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd
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$(call BUILD_VIVADO_BD,axi_intercon_2x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
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@@ -0,0 +1,715 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:synthFlowMode="None" bd:tool_version="2015.4" bd:top="axi_intercon_2x64_256_bd" bd:version="1.00.a">
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<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>BlockDiagram</spirit:library>
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<spirit:name>axi_intercon_2x64_256_bd</spirit:name>
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<spirit:version>1.00.a</spirit:version>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>isTop</spirit:name>
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<spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>M00_AXI</spirit:name>
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<spirit:master/>
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<spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:value>256</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PROTOCOL</spirit:name>
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<spirit:value>AXI4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FREQ_HZ</spirit:name>
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<spirit:value>200000000</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ADDR_WIDTH</spirit:name>
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<spirit:value>32</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
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<spirit:value>2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
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<spirit:value>2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value>axi_intercon_2x64_128_bd_M00_ACLK</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXI</spirit:name>
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<spirit:slave/>
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<spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:value>64</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PROTOCOL</spirit:name>
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<spirit:value>AXI4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FREQ_HZ</spirit:name>
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<spirit:value>350000000</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ID_WIDTH</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ADDR_WIDTH</spirit:name>
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<spirit:value>32</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>AWUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ARUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>WUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>RUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>BUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>READ_WRITE_MODE</spirit:name>
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<spirit:value>READ_WRITE</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_BURST</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_LOCK</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_PROT</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_CACHE</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_QOS</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_REGION</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_WSTRB</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_BRESP</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_RRESP</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
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<spirit:value>2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
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<spirit:value>2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>MAX_BURST_LENGTH</spirit:name>
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<spirit:value>256</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PHASE</spirit:name>
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<spirit:value>0.000</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S01_AXI</spirit:name>
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<spirit:slave/>
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<spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:value>64</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PROTOCOL</spirit:name>
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<spirit:value>AXI4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FREQ_HZ</spirit:name>
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<spirit:value>350000000</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ID_WIDTH</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ADDR_WIDTH</spirit:name>
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<spirit:value>32</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>AWUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ARUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>WUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>RUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>BUSER_WIDTH</spirit:name>
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<spirit:value>0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>READ_WRITE_MODE</spirit:name>
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<spirit:value>READ_WRITE</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_BURST</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_LOCK</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_PROT</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_CACHE</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_QOS</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_REGION</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_WSTRB</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_BRESP</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>HAS_RRESP</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
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<spirit:value>1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
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<spirit:value>2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
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<spirit:value>2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>MAX_BURST_LENGTH</spirit:name>
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<spirit:value>256</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PHASE</spirit:name>
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<spirit:value>0.000</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>CLK.M00_AXI_ACLK</spirit:name>
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<spirit:displayName>Clk</spirit:displayName>
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<spirit:description>Clock</spirit:description>
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<spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>M00_AXI_ACLK</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value>axi_intercon_2x64_128_bd_M00_ACLK</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value>M00_AXI_ARESETN</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>RST.M00_AXI_ARESETN</spirit:name>
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<spirit:displayName>Reset</spirit:displayName>
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<spirit:description>Reset</spirit:description>
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<spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>M00_AXI_ARESETN</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters/>
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</spirit:busInterface>
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<spirit:busInterface>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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||||
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|
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||||
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|
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|
||||
<spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_width_conv"/>
|
||||
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_rs_256"/>
|
||||
</spirit:interconnection>
|
||||
</spirit:interconnections>
|
||||
<spirit:adHocConnections>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>M00_AXI_ACLK_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="M00_AXI_ACLK"/>
|
||||
<spirit:internalPortReference spirit:componentRef="xbar" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="m00_rs" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_rs_256" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_rs_256" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="m_axi_aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="m_axi_aclk"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>M00_AXI_ARESETN_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="M00_AXI_ARESETN"/>
|
||||
<spirit:internalPortReference spirit:componentRef="xbar" spirit:portRef="aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="m00_rs" spirit:portRef="aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_rs_256" spirit:portRef="aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_rs_256" spirit:portRef="aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="m_axi_aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="m_axi_aresetn"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>S00_AXI_ACLK_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="S00_AXI_ACLK"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_rs" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="s_axi_aclk"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>S00_AXI_ARESETN_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="S00_AXI_ARESETN"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_rs" spirit:portRef="aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="s_axi_aresetn"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>S01_AXI_ACLK_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="S01_AXI_ACLK"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_rs" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="s_axi_aclk"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>S01_AXI_ARESETN_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="S01_AXI_ARESETN"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_rs" spirit:portRef="aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="s_axi_aresetn"/>
|
||||
</spirit:adHocConnection>
|
||||
</spirit:adHocConnections>
|
||||
<spirit:hierConnections>
|
||||
<spirit:hierConnection spirit:interfaceRef="M00_AXI/m00_rs_M_AXI">
|
||||
<spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="m00_rs"/>
|
||||
</spirit:hierConnection>
|
||||
<spirit:hierConnection spirit:interfaceRef="S00_AXI/S00_AXI_1">
|
||||
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_rs"/>
|
||||
</spirit:hierConnection>
|
||||
<spirit:hierConnection spirit:interfaceRef="S01_AXI/S01_AXI_1">
|
||||
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_rs"/>
|
||||
</spirit:hierConnection>
|
||||
</spirit:hierConnections>
|
||||
</spirit:design>
|
||||
|
||||
</bd:repository>
|
||||
@@ -0,0 +1,89 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="33">
|
||||
<CompositeFile CompositeFileTopName="axi_intercon_2x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s00_cc_0/axi_intercon_2x64_256_bd_s00_cc_0.xci" Type="IP">
|
||||
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_m00_rs_0/axi_intercon_2x64_256_bd_m00_rs_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_rs"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s00_rs_0/axi_intercon_2x64_256_bd_s00_rs_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_rs"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s00_width_conv_0/axi_intercon_2x64_256_bd_s00_width_conv_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_width_conv"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s01_rs_0/axi_intercon_2x64_256_bd_s01_rs_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_rs"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s01_width_conv_0/axi_intercon_2x64_256_bd_s01_width_conv_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_width_conv"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_xbar_0/axi_intercon_2x64_256_bd_xbar_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="xbar"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s01_rs_256_0/axi_intercon_2x64_256_bd_s01_rs_256_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_rs_256"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s00_rs_256_0/axi_intercon_2x64_256_bd_s00_rs_256_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_rs_256"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/axi_intercon_2x64_256_bd_s01_cc_0/axi_intercon_2x64_256_bd_s01_cc_0.xci" Type="IP">
|
||||
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
@@ -0,0 +1,500 @@
|
||||
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module axi_intercon_2x64_256_bd_wrapper
|
||||
(M00_AXI_ACLK,
|
||||
M00_AXI_ARESETN,
|
||||
M00_AXI_ARADDR,
|
||||
M00_AXI_ARBURST,
|
||||
M00_AXI_ARCACHE,
|
||||
M00_AXI_ARID,
|
||||
M00_AXI_ARLEN,
|
||||
M00_AXI_ARLOCK,
|
||||
M00_AXI_ARPROT,
|
||||
M00_AXI_ARQOS,
|
||||
M00_AXI_ARREADY,
|
||||
M00_AXI_ARREGION,
|
||||
M00_AXI_ARSIZE,
|
||||
M00_AXI_ARVALID,
|
||||
M00_AXI_AWADDR,
|
||||
M00_AXI_AWBURST,
|
||||
M00_AXI_AWCACHE,
|
||||
M00_AXI_AWID,
|
||||
M00_AXI_AWLEN,
|
||||
M00_AXI_AWLOCK,
|
||||
M00_AXI_AWPROT,
|
||||
M00_AXI_AWQOS,
|
||||
M00_AXI_AWREADY,
|
||||
M00_AXI_AWREGION,
|
||||
M00_AXI_AWSIZE,
|
||||
M00_AXI_AWVALID,
|
||||
M00_AXI_BID,
|
||||
M00_AXI_BREADY,
|
||||
M00_AXI_BRESP,
|
||||
M00_AXI_BVALID,
|
||||
M00_AXI_RDATA,
|
||||
M00_AXI_RID,
|
||||
M00_AXI_RLAST,
|
||||
M00_AXI_RREADY,
|
||||
M00_AXI_RRESP,
|
||||
M00_AXI_RVALID,
|
||||
M00_AXI_WDATA,
|
||||
M00_AXI_WLAST,
|
||||
M00_AXI_WREADY,
|
||||
M00_AXI_WSTRB,
|
||||
M00_AXI_WVALID,
|
||||
S00_AXI_ACLK,
|
||||
S00_AXI_ARESETN,
|
||||
S00_AXI_ARADDR,
|
||||
S00_AXI_ARBURST,
|
||||
S00_AXI_ARCACHE,
|
||||
S00_AXI_ARID,
|
||||
S00_AXI_ARLEN,
|
||||
S00_AXI_ARLOCK,
|
||||
S00_AXI_ARPROT,
|
||||
S00_AXI_ARQOS,
|
||||
S00_AXI_ARREADY,
|
||||
S00_AXI_ARREGION,
|
||||
S00_AXI_ARSIZE,
|
||||
S00_AXI_ARVALID,
|
||||
S00_AXI_AWADDR,
|
||||
S00_AXI_AWBURST,
|
||||
S00_AXI_AWCACHE,
|
||||
S00_AXI_AWID,
|
||||
S00_AXI_AWLEN,
|
||||
S00_AXI_AWLOCK,
|
||||
S00_AXI_AWPROT,
|
||||
S00_AXI_AWQOS,
|
||||
S00_AXI_AWREADY,
|
||||
S00_AXI_AWREGION,
|
||||
S00_AXI_AWSIZE,
|
||||
S00_AXI_AWVALID,
|
||||
S00_AXI_BID,
|
||||
S00_AXI_BREADY,
|
||||
S00_AXI_BRESP,
|
||||
S00_AXI_BVALID,
|
||||
S00_AXI_RDATA,
|
||||
S00_AXI_RID,
|
||||
S00_AXI_RLAST,
|
||||
S00_AXI_RREADY,
|
||||
S00_AXI_RRESP,
|
||||
S00_AXI_RVALID,
|
||||
S00_AXI_WDATA,
|
||||
S00_AXI_WLAST,
|
||||
S00_AXI_WREADY,
|
||||
S00_AXI_WSTRB,
|
||||
S00_AXI_WVALID,
|
||||
S01_AXI_ACLK,
|
||||
S01_AXI_ARESETN,
|
||||
S01_AXI_ARADDR,
|
||||
S01_AXI_ARBURST,
|
||||
S01_AXI_ARCACHE,
|
||||
S01_AXI_ARID,
|
||||
S01_AXI_ARLEN,
|
||||
S01_AXI_ARLOCK,
|
||||
S01_AXI_ARPROT,
|
||||
S01_AXI_ARQOS,
|
||||
S01_AXI_ARREADY,
|
||||
S01_AXI_ARREGION,
|
||||
S01_AXI_ARSIZE,
|
||||
S01_AXI_ARVALID,
|
||||
S01_AXI_AWADDR,
|
||||
S01_AXI_AWBURST,
|
||||
S01_AXI_AWCACHE,
|
||||
S01_AXI_AWID,
|
||||
S01_AXI_AWLEN,
|
||||
S01_AXI_AWLOCK,
|
||||
S01_AXI_AWPROT,
|
||||
S01_AXI_AWQOS,
|
||||
S01_AXI_AWREADY,
|
||||
S01_AXI_AWREGION,
|
||||
S01_AXI_AWSIZE,
|
||||
S01_AXI_AWVALID,
|
||||
S01_AXI_BID,
|
||||
S01_AXI_BREADY,
|
||||
S01_AXI_BRESP,
|
||||
S01_AXI_BVALID,
|
||||
S01_AXI_RDATA,
|
||||
S01_AXI_RID,
|
||||
S01_AXI_RLAST,
|
||||
S01_AXI_RREADY,
|
||||
S01_AXI_RRESP,
|
||||
S01_AXI_RVALID,
|
||||
S01_AXI_WDATA,
|
||||
S01_AXI_WLAST,
|
||||
S01_AXI_WREADY,
|
||||
S01_AXI_WSTRB,
|
||||
S01_AXI_WVALID);
|
||||
input M00_AXI_ACLK;
|
||||
input M00_AXI_ARESETN;
|
||||
output [31:0]M00_AXI_ARADDR;
|
||||
output [1:0]M00_AXI_ARBURST;
|
||||
output [3:0]M00_AXI_ARCACHE;
|
||||
output [0:0]M00_AXI_ARID;
|
||||
output [7:0]M00_AXI_ARLEN;
|
||||
output [0:0]M00_AXI_ARLOCK;
|
||||
output [2:0]M00_AXI_ARPROT;
|
||||
output [3:0]M00_AXI_ARQOS;
|
||||
input M00_AXI_ARREADY;
|
||||
output [3:0]M00_AXI_ARREGION;
|
||||
output [2:0]M00_AXI_ARSIZE;
|
||||
output M00_AXI_ARVALID;
|
||||
output [31:0]M00_AXI_AWADDR;
|
||||
output [1:0]M00_AXI_AWBURST;
|
||||
output [3:0]M00_AXI_AWCACHE;
|
||||
output [0:0]M00_AXI_AWID;
|
||||
output [7:0]M00_AXI_AWLEN;
|
||||
output [0:0]M00_AXI_AWLOCK;
|
||||
output [2:0]M00_AXI_AWPROT;
|
||||
output [3:0]M00_AXI_AWQOS;
|
||||
input M00_AXI_AWREADY;
|
||||
output [3:0]M00_AXI_AWREGION;
|
||||
output [2:0]M00_AXI_AWSIZE;
|
||||
output M00_AXI_AWVALID;
|
||||
input [0:0]M00_AXI_BID;
|
||||
output M00_AXI_BREADY;
|
||||
input [1:0]M00_AXI_BRESP;
|
||||
input M00_AXI_BVALID;
|
||||
input [255:0]M00_AXI_RDATA;
|
||||
input [0:0]M00_AXI_RID;
|
||||
input M00_AXI_RLAST;
|
||||
output M00_AXI_RREADY;
|
||||
input [1:0]M00_AXI_RRESP;
|
||||
input M00_AXI_RVALID;
|
||||
output [255:0]M00_AXI_WDATA;
|
||||
output M00_AXI_WLAST;
|
||||
input M00_AXI_WREADY;
|
||||
output [31:0]M00_AXI_WSTRB;
|
||||
output M00_AXI_WVALID;
|
||||
input S00_AXI_ACLK;
|
||||
input S00_AXI_ARESETN;
|
||||
input [31:0]S00_AXI_ARADDR;
|
||||
input [1:0]S00_AXI_ARBURST;
|
||||
input [3:0]S00_AXI_ARCACHE;
|
||||
input [0:0]S00_AXI_ARID;
|
||||
input [7:0]S00_AXI_ARLEN;
|
||||
input [0:0]S00_AXI_ARLOCK;
|
||||
input [2:0]S00_AXI_ARPROT;
|
||||
input [3:0]S00_AXI_ARQOS;
|
||||
output S00_AXI_ARREADY;
|
||||
input [3:0]S00_AXI_ARREGION;
|
||||
input [2:0]S00_AXI_ARSIZE;
|
||||
input S00_AXI_ARVALID;
|
||||
input [31:0]S00_AXI_AWADDR;
|
||||
input [1:0]S00_AXI_AWBURST;
|
||||
input [3:0]S00_AXI_AWCACHE;
|
||||
input [0:0]S00_AXI_AWID;
|
||||
input [7:0]S00_AXI_AWLEN;
|
||||
input [0:0]S00_AXI_AWLOCK;
|
||||
input [2:0]S00_AXI_AWPROT;
|
||||
input [3:0]S00_AXI_AWQOS;
|
||||
output S00_AXI_AWREADY;
|
||||
input [3:0]S00_AXI_AWREGION;
|
||||
input [2:0]S00_AXI_AWSIZE;
|
||||
input S00_AXI_AWVALID;
|
||||
output [0:0]S00_AXI_BID;
|
||||
input S00_AXI_BREADY;
|
||||
output [1:0]S00_AXI_BRESP;
|
||||
output S00_AXI_BVALID;
|
||||
output [63:0]S00_AXI_RDATA;
|
||||
output [0:0]S00_AXI_RID;
|
||||
output S00_AXI_RLAST;
|
||||
input S00_AXI_RREADY;
|
||||
output [1:0]S00_AXI_RRESP;
|
||||
output S00_AXI_RVALID;
|
||||
input [63:0]S00_AXI_WDATA;
|
||||
input S00_AXI_WLAST;
|
||||
output S00_AXI_WREADY;
|
||||
input [7:0]S00_AXI_WSTRB;
|
||||
input S00_AXI_WVALID;
|
||||
input S01_AXI_ACLK;
|
||||
input S01_AXI_ARESETN;
|
||||
input [31:0]S01_AXI_ARADDR;
|
||||
input [1:0]S01_AXI_ARBURST;
|
||||
input [3:0]S01_AXI_ARCACHE;
|
||||
input [0:0]S01_AXI_ARID;
|
||||
input [7:0]S01_AXI_ARLEN;
|
||||
input [0:0]S01_AXI_ARLOCK;
|
||||
input [2:0]S01_AXI_ARPROT;
|
||||
input [3:0]S01_AXI_ARQOS;
|
||||
output S01_AXI_ARREADY;
|
||||
input [3:0]S01_AXI_ARREGION;
|
||||
input [2:0]S01_AXI_ARSIZE;
|
||||
input S01_AXI_ARVALID;
|
||||
input [31:0]S01_AXI_AWADDR;
|
||||
input [1:0]S01_AXI_AWBURST;
|
||||
input [3:0]S01_AXI_AWCACHE;
|
||||
input [0:0]S01_AXI_AWID;
|
||||
input [7:0]S01_AXI_AWLEN;
|
||||
input [0:0]S01_AXI_AWLOCK;
|
||||
input [2:0]S01_AXI_AWPROT;
|
||||
input [3:0]S01_AXI_AWQOS;
|
||||
output S01_AXI_AWREADY;
|
||||
input [3:0]S01_AXI_AWREGION;
|
||||
input [2:0]S01_AXI_AWSIZE;
|
||||
input S01_AXI_AWVALID;
|
||||
output [0:0]S01_AXI_BID;
|
||||
input S01_AXI_BREADY;
|
||||
output [1:0]S01_AXI_BRESP;
|
||||
output S01_AXI_BVALID;
|
||||
output [63:0]S01_AXI_RDATA;
|
||||
output [0:0]S01_AXI_RID;
|
||||
output S01_AXI_RLAST;
|
||||
input S01_AXI_RREADY;
|
||||
output [1:0]S01_AXI_RRESP;
|
||||
output S01_AXI_RVALID;
|
||||
input [63:0]S01_AXI_WDATA;
|
||||
input S01_AXI_WLAST;
|
||||
output S01_AXI_WREADY;
|
||||
input [7:0]S01_AXI_WSTRB;
|
||||
input S01_AXI_WVALID;
|
||||
|
||||
wire M00_AXI_ACLK;
|
||||
wire M00_AXI_ARESETN;
|
||||
wire [31:0]M00_AXI_ARADDR;
|
||||
wire [1:0]M00_AXI_ARBURST;
|
||||
wire [3:0]M00_AXI_ARCACHE;
|
||||
wire [0:0]M00_AXI_ARID;
|
||||
wire [7:0]M00_AXI_ARLEN;
|
||||
wire [0:0]M00_AXI_ARLOCK;
|
||||
wire [2:0]M00_AXI_ARPROT;
|
||||
wire [3:0]M00_AXI_ARQOS;
|
||||
wire M00_AXI_ARREADY;
|
||||
wire [3:0]M00_AXI_ARREGION;
|
||||
wire [2:0]M00_AXI_ARSIZE;
|
||||
wire M00_AXI_ARVALID;
|
||||
wire [31:0]M00_AXI_AWADDR;
|
||||
wire [1:0]M00_AXI_AWBURST;
|
||||
wire [3:0]M00_AXI_AWCACHE;
|
||||
wire [0:0]M00_AXI_AWID;
|
||||
wire [7:0]M00_AXI_AWLEN;
|
||||
wire [0:0]M00_AXI_AWLOCK;
|
||||
wire [2:0]M00_AXI_AWPROT;
|
||||
wire [3:0]M00_AXI_AWQOS;
|
||||
wire M00_AXI_AWREADY;
|
||||
wire [3:0]M00_AXI_AWREGION;
|
||||
wire [2:0]M00_AXI_AWSIZE;
|
||||
wire M00_AXI_AWVALID;
|
||||
wire [0:0]M00_AXI_BID;
|
||||
wire M00_AXI_BREADY;
|
||||
wire [1:0]M00_AXI_BRESP;
|
||||
wire M00_AXI_BVALID;
|
||||
wire [255:0]M00_AXI_RDATA;
|
||||
wire [0:0]M00_AXI_RID;
|
||||
wire M00_AXI_RLAST;
|
||||
wire M00_AXI_RREADY;
|
||||
wire [1:0]M00_AXI_RRESP;
|
||||
wire M00_AXI_RVALID;
|
||||
wire [255:0]M00_AXI_WDATA;
|
||||
wire M00_AXI_WLAST;
|
||||
wire M00_AXI_WREADY;
|
||||
wire [31:0]M00_AXI_WSTRB;
|
||||
wire M00_AXI_WVALID;
|
||||
wire S00_AXI_ACLK;
|
||||
wire S00_AXI_ARESETN;
|
||||
wire [31:0]S00_AXI_ARADDR;
|
||||
wire [1:0]S00_AXI_ARBURST;
|
||||
wire [3:0]S00_AXI_ARCACHE;
|
||||
wire [0:0]S00_AXI_ARID;
|
||||
wire [7:0]S00_AXI_ARLEN;
|
||||
wire [0:0]S00_AXI_ARLOCK;
|
||||
wire [2:0]S00_AXI_ARPROT;
|
||||
wire [3:0]S00_AXI_ARQOS;
|
||||
wire S00_AXI_ARREADY;
|
||||
wire [3:0]S00_AXI_ARREGION;
|
||||
wire [2:0]S00_AXI_ARSIZE;
|
||||
wire S00_AXI_ARVALID;
|
||||
wire [31:0]S00_AXI_AWADDR;
|
||||
wire [1:0]S00_AXI_AWBURST;
|
||||
wire [3:0]S00_AXI_AWCACHE;
|
||||
wire [0:0]S00_AXI_AWID;
|
||||
wire [7:0]S00_AXI_AWLEN;
|
||||
wire [0:0]S00_AXI_AWLOCK;
|
||||
wire [2:0]S00_AXI_AWPROT;
|
||||
wire [3:0]S00_AXI_AWQOS;
|
||||
wire S00_AXI_AWREADY;
|
||||
wire [3:0]S00_AXI_AWREGION;
|
||||
wire [2:0]S00_AXI_AWSIZE;
|
||||
wire S00_AXI_AWVALID;
|
||||
wire [0:0]S00_AXI_BID;
|
||||
wire S00_AXI_BREADY;
|
||||
wire [1:0]S00_AXI_BRESP;
|
||||
wire S00_AXI_BVALID;
|
||||
wire [63:0]S00_AXI_RDATA;
|
||||
wire [0:0]S00_AXI_RID;
|
||||
wire S00_AXI_RLAST;
|
||||
wire S00_AXI_RREADY;
|
||||
wire [1:0]S00_AXI_RRESP;
|
||||
wire S00_AXI_RVALID;
|
||||
wire [63:0]S00_AXI_WDATA;
|
||||
wire S00_AXI_WLAST;
|
||||
wire S00_AXI_WREADY;
|
||||
wire [7:0]S00_AXI_WSTRB;
|
||||
wire S00_AXI_WVALID;
|
||||
wire S01_AXI_ACLK;
|
||||
wire S01_AXI_ARESETN;
|
||||
wire [31:0]S01_AXI_ARADDR;
|
||||
wire [1:0]S01_AXI_ARBURST;
|
||||
wire [3:0]S01_AXI_ARCACHE;
|
||||
wire [0:0]S01_AXI_ARID;
|
||||
wire [7:0]S01_AXI_ARLEN;
|
||||
wire [0:0]S01_AXI_ARLOCK;
|
||||
wire [2:0]S01_AXI_ARPROT;
|
||||
wire [3:0]S01_AXI_ARQOS;
|
||||
wire S01_AXI_ARREADY;
|
||||
wire [3:0]S01_AXI_ARREGION;
|
||||
wire [2:0]S01_AXI_ARSIZE;
|
||||
wire S01_AXI_ARVALID;
|
||||
wire [31:0]S01_AXI_AWADDR;
|
||||
wire [1:0]S01_AXI_AWBURST;
|
||||
wire [3:0]S01_AXI_AWCACHE;
|
||||
wire [0:0]S01_AXI_AWID;
|
||||
wire [7:0]S01_AXI_AWLEN;
|
||||
wire [0:0]S01_AXI_AWLOCK;
|
||||
wire [2:0]S01_AXI_AWPROT;
|
||||
wire [3:0]S01_AXI_AWQOS;
|
||||
wire S01_AXI_AWREADY;
|
||||
wire [3:0]S01_AXI_AWREGION;
|
||||
wire [2:0]S01_AXI_AWSIZE;
|
||||
wire S01_AXI_AWVALID;
|
||||
wire [0:0]S01_AXI_BID;
|
||||
wire S01_AXI_BREADY;
|
||||
wire [1:0]S01_AXI_BRESP;
|
||||
wire S01_AXI_BVALID;
|
||||
wire [63:0]S01_AXI_RDATA;
|
||||
wire [0:0]S01_AXI_RID;
|
||||
wire S01_AXI_RLAST;
|
||||
wire S01_AXI_RREADY;
|
||||
wire [1:0]S01_AXI_RRESP;
|
||||
wire S01_AXI_RVALID;
|
||||
wire [63:0]S01_AXI_WDATA;
|
||||
wire S01_AXI_WLAST;
|
||||
wire S01_AXI_WREADY;
|
||||
wire [7:0]S01_AXI_WSTRB;
|
||||
wire S01_AXI_WVALID;
|
||||
|
||||
axi_intercon_2x64_256_bd axi_intercon_2x64_256_bd_i (
|
||||
.M00_AXI_ACLK(M00_AXI_ACLK),
|
||||
.M00_AXI_ARESETN(M00_AXI_ARESETN),
|
||||
.M00_AXI_araddr(M00_AXI_ARADDR),
|
||||
.M00_AXI_arburst(M00_AXI_ARBURST),
|
||||
.M00_AXI_arcache(M00_AXI_ARCACHE),
|
||||
.M00_AXI_arid(M00_AXI_ARID),
|
||||
.M00_AXI_arlen(M00_AXI_ARLEN),
|
||||
.M00_AXI_arlock(M00_AXI_ARLOCK),
|
||||
.M00_AXI_arprot(M00_AXI_ARPROT),
|
||||
.M00_AXI_arqos(M00_AXI_ARQOS),
|
||||
.M00_AXI_arready(M00_AXI_ARREADY),
|
||||
.M00_AXI_arregion(M00_AXI_ARREGION),
|
||||
.M00_AXI_arsize(M00_AXI_ARSIZE),
|
||||
.M00_AXI_arvalid(M00_AXI_ARVALID),
|
||||
.M00_AXI_awaddr(M00_AXI_AWADDR),
|
||||
.M00_AXI_awburst(M00_AXI_AWBURST),
|
||||
.M00_AXI_awcache(M00_AXI_AWCACHE),
|
||||
.M00_AXI_awid(M00_AXI_AWID),
|
||||
.M00_AXI_awlen(M00_AXI_AWLEN),
|
||||
.M00_AXI_awlock(M00_AXI_AWLOCK),
|
||||
.M00_AXI_awprot(M00_AXI_AWPROT),
|
||||
.M00_AXI_awqos(M00_AXI_AWQOS),
|
||||
.M00_AXI_awready(M00_AXI_AWREADY),
|
||||
.M00_AXI_awregion(M00_AXI_AWREGION),
|
||||
.M00_AXI_awsize(M00_AXI_AWSIZE),
|
||||
.M00_AXI_awvalid(M00_AXI_AWVALID),
|
||||
.M00_AXI_bid(M00_AXI_BID),
|
||||
.M00_AXI_bready(M00_AXI_BREADY),
|
||||
.M00_AXI_bresp(M00_AXI_BRESP),
|
||||
.M00_AXI_bvalid(M00_AXI_BVALID),
|
||||
.M00_AXI_rdata(M00_AXI_RDATA),
|
||||
.M00_AXI_rid(M00_AXI_RID),
|
||||
.M00_AXI_rlast(M00_AXI_RLAST),
|
||||
.M00_AXI_rready(M00_AXI_RREADY),
|
||||
.M00_AXI_rresp(M00_AXI_RRESP),
|
||||
.M00_AXI_rvalid(M00_AXI_RVALID),
|
||||
.M00_AXI_wdata(M00_AXI_WDATA),
|
||||
.M00_AXI_wlast(M00_AXI_WLAST),
|
||||
.M00_AXI_wready(M00_AXI_WREADY),
|
||||
.M00_AXI_wstrb(M00_AXI_WSTRB),
|
||||
.M00_AXI_wvalid(M00_AXI_WVALID),
|
||||
.S00_AXI_ACLK(S00_AXI_ACLK),
|
||||
.S00_AXI_ARESETN(S00_AXI_ARESETN),
|
||||
.S00_AXI_araddr(S00_AXI_ARADDR),
|
||||
.S00_AXI_arburst(S00_AXI_ARBURST),
|
||||
.S00_AXI_arcache(S00_AXI_ARCACHE),
|
||||
.S00_AXI_arid(S00_AXI_ARID),
|
||||
.S00_AXI_arlen(S00_AXI_ARLEN),
|
||||
.S00_AXI_arlock(S00_AXI_ARLOCK),
|
||||
.S00_AXI_arprot(S00_AXI_ARPROT),
|
||||
.S00_AXI_arqos(S00_AXI_ARQOS),
|
||||
.S00_AXI_arready(S00_AXI_ARREADY),
|
||||
.S00_AXI_arregion(S00_AXI_ARREGION),
|
||||
.S00_AXI_arsize(S00_AXI_ARSIZE),
|
||||
.S00_AXI_arvalid(S00_AXI_ARVALID),
|
||||
.S00_AXI_awaddr(S00_AXI_AWADDR),
|
||||
.S00_AXI_awburst(S00_AXI_AWBURST),
|
||||
.S00_AXI_awcache(S00_AXI_AWCACHE),
|
||||
.S00_AXI_awid(S00_AXI_AWID),
|
||||
.S00_AXI_awlen(S00_AXI_AWLEN),
|
||||
.S00_AXI_awlock(S00_AXI_AWLOCK),
|
||||
.S00_AXI_awprot(S00_AXI_AWPROT),
|
||||
.S00_AXI_awqos(S00_AXI_AWQOS),
|
||||
.S00_AXI_awready(S00_AXI_AWREADY),
|
||||
.S00_AXI_awregion(S00_AXI_AWREGION),
|
||||
.S00_AXI_awsize(S00_AXI_AWSIZE),
|
||||
.S00_AXI_awvalid(S00_AXI_AWVALID),
|
||||
.S00_AXI_bid(S00_AXI_BID),
|
||||
.S00_AXI_bready(S00_AXI_BREADY),
|
||||
.S00_AXI_bresp(S00_AXI_BRESP),
|
||||
.S00_AXI_bvalid(S00_AXI_BVALID),
|
||||
.S00_AXI_rdata(S00_AXI_RDATA),
|
||||
.S00_AXI_rid(S00_AXI_RID),
|
||||
.S00_AXI_rlast(S00_AXI_RLAST),
|
||||
.S00_AXI_rready(S00_AXI_RREADY),
|
||||
.S00_AXI_rresp(S00_AXI_RRESP),
|
||||
.S00_AXI_rvalid(S00_AXI_RVALID),
|
||||
.S00_AXI_wdata(S00_AXI_WDATA),
|
||||
.S00_AXI_wlast(S00_AXI_WLAST),
|
||||
.S00_AXI_wready(S00_AXI_WREADY),
|
||||
.S00_AXI_wstrb(S00_AXI_WSTRB),
|
||||
.S00_AXI_wvalid(S00_AXI_WVALID),
|
||||
.S01_AXI_ACLK(S01_AXI_ACLK),
|
||||
.S01_AXI_ARESETN(S01_AXI_ARESETN),
|
||||
.S01_AXI_araddr(S01_AXI_ARADDR),
|
||||
.S01_AXI_arburst(S01_AXI_ARBURST),
|
||||
.S01_AXI_arcache(S01_AXI_ARCACHE),
|
||||
.S01_AXI_arid(S01_AXI_ARID),
|
||||
.S01_AXI_arlen(S01_AXI_ARLEN),
|
||||
.S01_AXI_arlock(S01_AXI_ARLOCK),
|
||||
.S01_AXI_arprot(S01_AXI_ARPROT),
|
||||
.S01_AXI_arqos(S01_AXI_ARQOS),
|
||||
.S01_AXI_arready(S01_AXI_ARREADY),
|
||||
.S01_AXI_arregion(S01_AXI_ARREGION),
|
||||
.S01_AXI_arsize(S01_AXI_ARSIZE),
|
||||
.S01_AXI_arvalid(S01_AXI_ARVALID),
|
||||
.S01_AXI_awaddr(S01_AXI_AWADDR),
|
||||
.S01_AXI_awburst(S01_AXI_AWBURST),
|
||||
.S01_AXI_awcache(S01_AXI_AWCACHE),
|
||||
.S01_AXI_awid(S01_AXI_AWID),
|
||||
.S01_AXI_awlen(S01_AXI_AWLEN),
|
||||
.S01_AXI_awlock(S01_AXI_AWLOCK),
|
||||
.S01_AXI_awprot(S01_AXI_AWPROT),
|
||||
.S01_AXI_awqos(S01_AXI_AWQOS),
|
||||
.S01_AXI_awready(S01_AXI_AWREADY),
|
||||
.S01_AXI_awregion(S01_AXI_AWREGION),
|
||||
.S01_AXI_awsize(S01_AXI_AWSIZE),
|
||||
.S01_AXI_awvalid(S01_AXI_AWVALID),
|
||||
.S01_AXI_bid(S01_AXI_BID),
|
||||
.S01_AXI_bready(S01_AXI_BREADY),
|
||||
.S01_AXI_bresp(S01_AXI_BRESP),
|
||||
.S01_AXI_bvalid(S01_AXI_BVALID),
|
||||
.S01_AXI_rdata(S01_AXI_RDATA),
|
||||
.S01_AXI_rid(S01_AXI_RID),
|
||||
.S01_AXI_rlast(S01_AXI_RLAST),
|
||||
.S01_AXI_rready(S01_AXI_RREADY),
|
||||
.S01_AXI_rresp(S01_AXI_RRESP),
|
||||
.S01_AXI_rvalid(S01_AXI_RVALID),
|
||||
.S01_AXI_wdata(S01_AXI_WDATA),
|
||||
.S01_AXI_wlast(S01_AXI_WLAST),
|
||||
.S01_AXI_wready(S01_AXI_WREADY),
|
||||
.S01_AXI_wstrb(S01_AXI_WSTRB),
|
||||
.S01_AXI_wvalid(S01_AXI_WVALID));
|
||||
endmodule
|
||||
Reference in New Issue
Block a user