Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,22 @@
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#
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# Copyright 2018 Ettus Research, a National Instruments Company
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#
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.PHONY: all clean
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SRCS=TopCpld.qpf TopCpld.qsf Timing.sdc PkgMgCpld.vhd PkgSetup.vhd TopCpld.vhd
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all: output_files/TopCpld.svf
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cpld-magnesium-revc.svf: output_files/TopCpld.pof
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quartus_cpf --convert --frequency 10.0MHz --voltage 3.3 --operation p $? $@
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output_files/TopCpld.pof: $(SRCS)
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quartus_map TopCpld
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quartus_fit TopCpld
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quartus_asm TopCpld
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quartus_sta TopCpld
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clean:
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rm -rf db incremental_db output_files simulation cpld-magnesium-revc.svf
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@@ -0,0 +1,424 @@
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-------------------------------------------------------------------------------
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--
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-- File: PkgMgCpld.vhd
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-- Author: Autogenerated by XmlParse
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-- Original Project: --
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-- Date: --
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--
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-------------------------------------------------------------------------------
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-- Copyright 2016-2017 Ettus Research, A National Instruments Company
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-- SPDX-License-Identifier: GPL-3.0
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-------------------------------------------------------------------------------
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--
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-- Purpose:
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-- The constants in this file are autogenerated by XmlParse and should
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-- be used by testbench code to access specific register fields.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package PkgMgCpld is
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--===============================================================================
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-- A numerically ordered list of registers and their VHDL source files
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--===============================================================================
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-- SignatureReg : 0x0 (TopCpld.vhd)
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-- MinorRevReg : 0x1 (TopCpld.vhd)
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-- MajorRevReg : 0x2 (TopCpld.vhd)
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-- BuildCodeLSB : 0x3 (TopCpld.vhd)
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-- BuildCodeMSB : 0x4 (TopCpld.vhd)
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-- Scratch : 0x5 (TopCpld.vhd)
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-- CpldControl : 0x10 (TopCpld.vhd)
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-- LmkControl : 0x11 (TopCpld.vhd)
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-- LoStatus : 0x12 (TopCpld.vhd)
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-- MykonosControl : 0x13 (TopCpld.vhd)
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-- PlScratch : 0x40 (TopCpld.vhd)
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-- PlCpldControl : 0x41 (TopCpld.vhd)
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-- TxCh1_Idle : 0x50 (TopCpld.vhd)
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-- RxCh1_0_Idle : 0x51 (TopCpld.vhd)
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-- RxCh1_1_Idle : 0x52 (TopCpld.vhd)
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-- TxCh1_TxOn : 0x53 (TopCpld.vhd)
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-- RxCh1_0_RxOn : 0x54 (TopCpld.vhd)
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-- RxCh1_1_RxOn : 0x55 (TopCpld.vhd)
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-- TxCh2_Idle : 0x60 (TopCpld.vhd)
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-- RxCh2_0_Idle : 0x61 (TopCpld.vhd)
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-- RxCh2_1_Idle : 0x62 (TopCpld.vhd)
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-- TxCh2_TxOn : 0x63 (TopCpld.vhd)
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-- RxCh2_0_RxOn : 0x64 (TopCpld.vhd)
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-- RxCh2_1_RxOn : 0x65 (TopCpld.vhd)
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--===============================================================================
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-- RegTypes
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--===============================================================================
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--===============================================================================
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-- Register Group PsSpi_CpldRegisters
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--===============================================================================
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-- SignatureReg Register (from TopCpld.vhd)
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constant kSignatureReg : integer := 16#0#; -- Register Offset
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constant kSignatureRegSize: integer := 16; -- register width in bits
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constant kSignatureRegMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kProductSignatureSize : integer := 16; --SignatureReg:ProductSignature
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constant kProductSignatureMsb : integer := 15; --SignatureReg:ProductSignature
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constant kProductSignature : integer := 0; --SignatureReg:ProductSignature
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-- MinorRevReg Register (from TopCpld.vhd)
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constant kMinorRevReg : integer := 16#1#; -- Register Offset
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constant kMinorRevRegSize: integer := 16; -- register width in bits
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constant kMinorRevRegMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kCpldMinorRevisionSize : integer := 16; --MinorRevReg:CpldMinorRevision
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constant kCpldMinorRevisionMsb : integer := 15; --MinorRevReg:CpldMinorRevision
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constant kCpldMinorRevision : integer := 0; --MinorRevReg:CpldMinorRevision
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-- MajorRevReg Register (from TopCpld.vhd)
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constant kMajorRevReg : integer := 16#2#; -- Register Offset
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constant kMajorRevRegSize: integer := 16; -- register width in bits
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constant kMajorRevRegMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kCpldMajorRevisionSize : integer := 16; --MajorRevReg:CpldMajorRevision
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constant kCpldMajorRevisionMsb : integer := 15; --MajorRevReg:CpldMajorRevision
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constant kCpldMajorRevision : integer := 0; --MajorRevReg:CpldMajorRevision
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-- BuildCodeLSB Register (from TopCpld.vhd)
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constant kBuildCodeLSB : integer := 16#3#; -- Register Offset
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constant kBuildCodeLSBSize: integer := 16; -- register width in bits
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constant kBuildCodeLSBMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kBuildCodeHHSize : integer := 8; --BuildCodeLSB:BuildCodeHH
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constant kBuildCodeHHMsb : integer := 7; --BuildCodeLSB:BuildCodeHH
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constant kBuildCodeHH : integer := 0; --BuildCodeLSB:BuildCodeHH
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constant kBuildCodeDDSize : integer := 8; --BuildCodeLSB:BuildCodeDD
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constant kBuildCodeDDMsb : integer := 15; --BuildCodeLSB:BuildCodeDD
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constant kBuildCodeDD : integer := 8; --BuildCodeLSB:BuildCodeDD
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-- BuildCodeMSB Register (from TopCpld.vhd)
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constant kBuildCodeMSB : integer := 16#4#; -- Register Offset
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constant kBuildCodeMSBSize: integer := 16; -- register width in bits
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constant kBuildCodeMSBMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kBuildCodeMMSize : integer := 8; --BuildCodeMSB:BuildCodeMM
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constant kBuildCodeMMMsb : integer := 7; --BuildCodeMSB:BuildCodeMM
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constant kBuildCodeMM : integer := 0; --BuildCodeMSB:BuildCodeMM
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constant kBuildCodeYYSize : integer := 8; --BuildCodeMSB:BuildCodeYY
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constant kBuildCodeYYMsb : integer := 15; --BuildCodeMSB:BuildCodeYY
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constant kBuildCodeYY : integer := 8; --BuildCodeMSB:BuildCodeYY
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-- Scratch Register (from TopCpld.vhd)
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constant kScratch : integer := 16#5#; -- Register Offset
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constant kScratchSize: integer := 16; -- register width in bits
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constant kScratchMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kScratchValSize : integer := 16; --Scratch:ScratchVal
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constant kScratchValMsb : integer := 15; --Scratch:ScratchVal
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constant kScratchVal : integer := 0; --Scratch:ScratchVal
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-- CpldControl Register (from TopCpld.vhd)
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constant kCpldControl : integer := 16#10#; -- Register Offset
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constant kCpldControlSize: integer := 16; -- register width in bits
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constant kCpldControlMask : std_logic_vector(15 downto 0) := X"0001";
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constant kCpldResetSize : integer := 1; --CpldControl:CpldReset
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constant kCpldResetMsb : integer := 0; --CpldControl:CpldReset
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constant kCpldReset : integer := 0; --CpldControl:CpldReset
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-- LmkControl Register (from TopCpld.vhd)
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constant kLmkControl : integer := 16#11#; -- Register Offset
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constant kLmkControlSize: integer := 16; -- register width in bits
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constant kLmkControlMask : std_logic_vector(15 downto 0) := X"0010";
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constant kVcxoControlSize : integer := 1; --LmkControl:VcxoControl
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constant kVcxoControlMsb : integer := 4; --LmkControl:VcxoControl
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constant kVcxoControl : integer := 4; --LmkControl:VcxoControl
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-- LoStatus Register (from TopCpld.vhd)
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constant kLoStatus : integer := 16#12#; -- Register Offset
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constant kLoStatusSize: integer := 16; -- register width in bits
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constant kLoStatusMask : std_logic_vector(15 downto 0) := X"0011";
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constant kRxLoLockDetectSize : integer := 1; --LoStatus:RxLoLockDetect
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constant kRxLoLockDetectMsb : integer := 0; --LoStatus:RxLoLockDetect
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constant kRxLoLockDetect : integer := 0; --LoStatus:RxLoLockDetect
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constant kTxLoLockDetectSize : integer := 1; --LoStatus:TxLoLockDetect
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constant kTxLoLockDetectMsb : integer := 4; --LoStatus:TxLoLockDetect
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constant kTxLoLockDetect : integer := 4; --LoStatus:TxLoLockDetect
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-- MykonosControl Register (from TopCpld.vhd)
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constant kMykonosControl : integer := 16#13#; -- Register Offset
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constant kMykonosControlSize: integer := 16; -- register width in bits
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constant kMykonosControlMask : std_logic_vector(15 downto 0) := X"0001";
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constant kMykonosResetSize : integer := 1; --MykonosControl:MykonosReset
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constant kMykonosResetMsb : integer := 0; --MykonosControl:MykonosReset
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constant kMykonosReset : integer := 0; --MykonosControl:MykonosReset
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--===============================================================================
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-- Register Group PlSpi_FrontEndControl
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--===============================================================================
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-- Enumerated type Rx1Switch1
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constant kRx1Switch1Size : integer := 4;
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constant kTxRxInput : integer := 0; -- Rx1Switch1:TxRxInput
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constant kRxLoCalInput : integer := 1; -- Rx1Switch1:RxLoCalInput
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constant kTrxSwitchOutput : integer := 2; -- Rx1Switch1:TrxSwitchOutput
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constant kRx2Input : integer := 3; -- Rx1Switch1:Rx2Input
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-- Enumerated type Rx1Switch2
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constant kRx1Switch2Size : integer := 4;
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constant kShutdownSw2 : integer := 0; -- Rx1Switch2:ShutdownSw2
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constant kLowerFilterBankToSwitch3 : integer := 1; -- Rx1Switch2:LowerFilterBankToSwitch3
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constant kBypassPathToSwitch6 : integer := 2; -- Rx1Switch2:BypassPathToSwitch6
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constant kUpperFilterBankToSwitch4 : integer := 3; -- Rx1Switch2:UpperFilterBankToSwitch4
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-- Enumerated type Rx1Switch3
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constant kRx1Switch3Size : integer := 7;
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constant kFilter2100x2850MHz : integer := 0; -- Rx1Switch3:Filter2100x2850MHz
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constant kFilter0490LpMHz : integer := 1; -- Rx1Switch3:Filter0490LpMHz
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constant kFilter1600x2250MHz : integer := 2; -- Rx1Switch3:Filter1600x2250MHz
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constant kFilter0440x0530MHz : integer := 4; -- Rx1Switch3:Filter0440x0530MHz
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constant kFilter0650x1000MHz : integer := 5; -- Rx1Switch3:Filter0650x1000MHz
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constant kFilter1100x1575MHz : integer := 6; -- Rx1Switch3:Filter1100x1575MHz
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constant kShutdownSw3 : integer := 7; -- Rx1Switch3:ShutdownSw3
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-- Enumerated type Rx1Switch4
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constant kRx1Switch4Size : integer := 3;
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constant kFilter2100x2850MHzFrom : integer := 1; -- Rx1Switch4:Filter2100x2850MHzFrom
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constant kFilter1600x2250MHzFrom : integer := 2; -- Rx1Switch4:Filter1600x2250MHzFrom
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constant kFilter2700HpMHz : integer := 4; -- Rx1Switch4:Filter2700HpMHz
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-- Enumerated type Rx1Switch5
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constant kRx1Switch5Size : integer := 4;
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constant kFilter0440x0530MHzFrom : integer := 1; -- Rx1Switch5:Filter0440x0530MHzFrom
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constant kFilter1100x1575MHzFrom : integer := 2; -- Rx1Switch5:Filter1100x1575MHzFrom
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constant kFilter0490LpMHzFrom : integer := 4; -- Rx1Switch5:Filter0490LpMHzFrom
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constant kFilter0650x1000MHzFrom : integer := 8; -- Rx1Switch5:Filter0650x1000MHzFrom
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-- Enumerated type Rx1Switch6
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constant kRx1Switch6Size : integer := 3;
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constant kLowerFilterBankFromSwitch5 : integer := 1; -- Rx1Switch6:LowerFilterBankFromSwitch5
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constant kUpperFilterBankFromSwitch4 : integer := 2; -- Rx1Switch6:UpperFilterBankFromSwitch4
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constant kBypassPathFromSwitch2 : integer := 4; -- Rx1Switch6:BypassPathFromSwitch2
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-- Enumerated type TrxSwitch
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constant kTrxSwitchSize : integer := 4;
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constant kFromLowerFilterBankTxSw1 : integer := 0; -- TrxSwitch:FromLowerFilterBankTxSw1
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constant kFromTxUpperFilterBankLp6400MHz : integer := 1; -- TrxSwitch:FromTxUpperFilterBankLp6400MHz
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constant kRxChannelPath : integer := 2; -- TrxSwitch:RxChannelPath
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constant kBypassPathToTxSw3 : integer := 3; -- TrxSwitch:BypassPathToTxSw3
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-- Enumerated type TxSwitch1
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constant kTxSwitch1Size : integer := 4;
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constant kShutdownTxSw1 : integer := 0; -- TxSwitch1:ShutdownTxSw1
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constant kFromTxFilterLp1700MHz : integer := 1; -- TxSwitch1:FromTxFilterLp1700MHz
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constant kFromTxFilterLp3400MHz : integer := 2; -- TxSwitch1:FromTxFilterLp3400MHz
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constant kFromTxFilterLp0800MHz : integer := 3; -- TxSwitch1:FromTxFilterLp0800MHz
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-- Enumerated type TxSwitch2
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constant kTxSwitch2Size : integer := 4;
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constant kToTxFilterLp3400MHz : integer := 1; -- TxSwitch2:ToTxFilterLp3400MHz
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constant kToTxFilterLp1700MHz : integer := 2; -- TxSwitch2:ToTxFilterLp1700MHz
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constant kToTxFilterLp0800MHz : integer := 4; -- TxSwitch2:ToTxFilterLp0800MHz
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constant kToTxFilterLp6400MHz : integer := 8; -- TxSwitch2:ToTxFilterLp6400MHz
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-- Enumerated type TxSwitch3
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constant kTxSwitch3Size : integer := 2;
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constant kToTxFilterBanks : integer := 0; -- TxSwitch3:ToTxFilterBanks
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constant kBypassPathToTrxSw : integer := 1; -- TxSwitch3:BypassPathToTrxSw
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-- PlScratch Register (from TopCpld.vhd)
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constant kPlScratch : integer := 16#40#; -- Register Offset
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constant kPlScratchSize: integer := 16; -- register width in bits
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constant kPlScratchMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kPlScratchValSize : integer := 16; --PlScratch:PlScratchVal
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constant kPlScratchValMsb : integer := 15; --PlScratch:PlScratchVal
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constant kPlScratchVal : integer := 0; --PlScratch:PlScratchVal
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-- PlCpldControl Register (from TopCpld.vhd)
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constant kPlCpldControl : integer := 16#41#; -- Register Offset
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constant kPlCpldControlSize: integer := 16; -- register width in bits
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constant kPlCpldControlMask : std_logic_vector(15 downto 0) := X"0001";
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constant kPlCpldResetSize : integer := 1; --PlCpldControl:PlCpldReset
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constant kPlCpldResetMsb : integer := 0; --PlCpldControl:PlCpldReset
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constant kPlCpldReset : integer := 0; --PlCpldControl:PlCpldReset
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-- TxCh1_Idle Register (from TopCpld.vhd)
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constant kTxCh1_Idle : integer := 16#50#; -- Register Offset
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constant kTxCh1_IdleSize: integer := 16; -- register width in bits
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constant kTxCh1_IdleMask : std_logic_vector(15 downto 0) := X"7fff";
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constant kCh1TxSw1Size : integer := 2; --TxCh1_Idle:Ch1TxSw1
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constant kCh1TxSw1Msb : integer := 1; --TxCh1_Idle:Ch1TxSw1
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constant kCh1TxSw1 : integer := 0; --TxCh1_Idle:Ch1TxSw1
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constant kCh1TxSw2Size : integer := 4; --TxCh1_Idle:Ch1TxSw2
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constant kCh1TxSw2Msb : integer := 5; --TxCh1_Idle:Ch1TxSw2
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constant kCh1TxSw2 : integer := 2; --TxCh1_Idle:Ch1TxSw2
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constant kCh1TxSw3Size : integer := 1; --TxCh1_Idle:Ch1TxSw3
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||||
constant kCh1TxSw3Msb : integer := 6; --TxCh1_Idle:Ch1TxSw3
|
||||
constant kCh1TxSw3 : integer := 6; --TxCh1_Idle:Ch1TxSw3
|
||||
constant kCh1TxLowbandMixerPathSelectSize : integer := 1; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect
|
||||
constant kCh1TxLowbandMixerPathSelectMsb : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect
|
||||
constant kCh1TxLowbandMixerPathSelect : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect
|
||||
constant kCh1TxMixerEnSize : integer := 1; --TxCh1_Idle:Ch1TxMixerEn
|
||||
constant kCh1TxMixerEnMsb : integer := 8; --TxCh1_Idle:Ch1TxMixerEn
|
||||
constant kCh1TxMixerEn : integer := 8; --TxCh1_Idle:Ch1TxMixerEn
|
||||
constant kCh1TxAmpEnSize : integer := 1; --TxCh1_Idle:Ch1TxAmpEn
|
||||
constant kCh1TxAmpEnMsb : integer := 9; --TxCh1_Idle:Ch1TxAmpEn
|
||||
constant kCh1TxAmpEn : integer := 9; --TxCh1_Idle:Ch1TxAmpEn
|
||||
constant kCh1TxPaEnSize : integer := 1; --TxCh1_Idle:Ch1TxPaEn
|
||||
constant kCh1TxPaEnMsb : integer := 10; --TxCh1_Idle:Ch1TxPaEn
|
||||
constant kCh1TxPaEn : integer := 10; --TxCh1_Idle:Ch1TxPaEn
|
||||
constant kCh1SwTrxSize : integer := 2; --TxCh1_Idle:Ch1SwTrx
|
||||
constant kCh1SwTrxMsb : integer := 12; --TxCh1_Idle:Ch1SwTrx
|
||||
constant kCh1SwTrx : integer := 11; --TxCh1_Idle:Ch1SwTrx
|
||||
constant kCh1TxLedSize : integer := 1; --TxCh1_Idle:Ch1TxLed
|
||||
constant kCh1TxLedMsb : integer := 13; --TxCh1_Idle:Ch1TxLed
|
||||
constant kCh1TxLed : integer := 13; --TxCh1_Idle:Ch1TxLed
|
||||
constant kCh1MykEnTxSize : integer := 1; --TxCh1_Idle:Ch1MykEnTx
|
||||
constant kCh1MykEnTxMsb : integer := 14; --TxCh1_Idle:Ch1MykEnTx
|
||||
constant kCh1MykEnTx : integer := 14; --TxCh1_Idle:Ch1MykEnTx
|
||||
|
||||
-- RxCh1_0_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh1_0_Idle : integer := 16#51#; -- Register Offset
|
||||
constant kRxCh1_0_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_0_IdleMask : std_logic_vector(15 downto 0) := X"3fff";
|
||||
constant kCh1RxSw1Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw1
|
||||
constant kCh1RxSw1Msb : integer := 1; --RxCh1_0_Idle:Ch1RxSw1
|
||||
constant kCh1RxSw1 : integer := 0; --RxCh1_0_Idle:Ch1RxSw1
|
||||
constant kCh1RxSw2Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw2
|
||||
constant kCh1RxSw2Msb : integer := 3; --RxCh1_0_Idle:Ch1RxSw2
|
||||
constant kCh1RxSw2 : integer := 2; --RxCh1_0_Idle:Ch1RxSw2
|
||||
constant kCh1RxSw3Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw3
|
||||
constant kCh1RxSw3Msb : integer := 6; --RxCh1_0_Idle:Ch1RxSw3
|
||||
constant kCh1RxSw3 : integer := 4; --RxCh1_0_Idle:Ch1RxSw3
|
||||
constant kCh1RxSw4Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw4
|
||||
constant kCh1RxSw4Msb : integer := 9; --RxCh1_0_Idle:Ch1RxSw4
|
||||
constant kCh1RxSw4 : integer := 7; --RxCh1_0_Idle:Ch1RxSw4
|
||||
constant kCh1RxSw5Size : integer := 4; --RxCh1_0_Idle:Ch1RxSw5
|
||||
constant kCh1RxSw5Msb : integer := 13; --RxCh1_0_Idle:Ch1RxSw5
|
||||
constant kCh1RxSw5 : integer := 10; --RxCh1_0_Idle:Ch1RxSw5
|
||||
|
||||
-- RxCh1_1_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh1_1_Idle : integer := 16#52#; -- Register Offset
|
||||
constant kRxCh1_1_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_1_IdleMask : std_logic_vector(15 downto 0) := X"07ff";
|
||||
constant kCh1RxSw6Size : integer := 3; --RxCh1_1_Idle:Ch1RxSw6
|
||||
constant kCh1RxSw6Msb : integer := 2; --RxCh1_1_Idle:Ch1RxSw6
|
||||
constant kCh1RxSw6 : integer := 0; --RxCh1_1_Idle:Ch1RxSw6
|
||||
constant kCh1RxLowbandMixerPathSelectSize : integer := 1; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect
|
||||
constant kCh1RxLowbandMixerPathSelectMsb : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect
|
||||
constant kCh1RxLowbandMixerPathSelect : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect
|
||||
constant kCh1RxMixerEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxMixerEn
|
||||
constant kCh1RxMixerEnMsb : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn
|
||||
constant kCh1RxMixerEn : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn
|
||||
constant kCh1RxAmpEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxAmpEn
|
||||
constant kCh1RxAmpEnMsb : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn
|
||||
constant kCh1RxAmpEn : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn
|
||||
constant kCh1RxLna1EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna1En
|
||||
constant kCh1RxLna1EnMsb : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En
|
||||
constant kCh1RxLna1En : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En
|
||||
constant kCh1RxLna2EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna2En
|
||||
constant kCh1RxLna2EnMsb : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En
|
||||
constant kCh1RxLna2En : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En
|
||||
constant kCh1Rx2LedSize : integer := 1; --RxCh1_1_Idle:Ch1Rx2Led
|
||||
constant kCh1Rx2LedMsb : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led
|
||||
constant kCh1Rx2Led : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led
|
||||
constant kCh1RxLedSize : integer := 1; --RxCh1_1_Idle:Ch1RxLed
|
||||
constant kCh1RxLedMsb : integer := 9; --RxCh1_1_Idle:Ch1RxLed
|
||||
constant kCh1RxLed : integer := 9; --RxCh1_1_Idle:Ch1RxLed
|
||||
constant kCh1MykEnRxSize : integer := 1; --RxCh1_1_Idle:Ch1MykEnRx
|
||||
constant kCh1MykEnRxMsb : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx
|
||||
constant kCh1MykEnRx : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx
|
||||
|
||||
-- TxCh1_TxOn Register (from TopCpld.vhd)
|
||||
constant kTxCh1_TxOn : integer := 16#53#; -- Register Offset
|
||||
constant kTxCh1_TxOnSize: integer := 16; -- register width in bits
|
||||
constant kTxCh1_TxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh1_0_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh1_0_RxOn : integer := 16#54#; -- Register Offset
|
||||
constant kRxCh1_0_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh1_1_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh1_1_RxOn : integer := 16#55#; -- Register Offset
|
||||
constant kRxCh1_1_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- TxCh2_Idle Register (from TopCpld.vhd)
|
||||
constant kTxCh2_Idle : integer := 16#60#; -- Register Offset
|
||||
constant kTxCh2_IdleSize: integer := 16; -- register width in bits
|
||||
constant kTxCh2_IdleMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_0_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh2_0_Idle : integer := 16#61#; -- Register Offset
|
||||
constant kRxCh2_0_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_0_IdleMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_1_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh2_1_Idle : integer := 16#62#; -- Register Offset
|
||||
constant kRxCh2_1_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_1_IdleMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- TxCh2_TxOn Register (from TopCpld.vhd)
|
||||
constant kTxCh2_TxOn : integer := 16#63#; -- Register Offset
|
||||
constant kTxCh2_TxOnSize: integer := 16; -- register width in bits
|
||||
constant kTxCh2_TxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_0_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh2_0_RxOn : integer := 16#64#; -- Register Offset
|
||||
constant kRxCh2_0_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_1_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh2_1_RxOn : integer := 16#65#; -- Register Offset
|
||||
constant kRxCh2_1_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
end package;
|
||||
|
||||
package body PkgMgCpld is
|
||||
|
||||
-- function kSignatureRegRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMinorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMajorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kBuildCodeLSBRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kBuildCodeMSBRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kScratchRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kLmkControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kLoStatusRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMykonosControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kPlScratchRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kPlCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh1_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh2_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh2_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,259 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: PkgSetup.vhd
|
||||
-- Author: Daniel Jepson
|
||||
-- Original Project: N310
|
||||
-- Date: 22 September 2017
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2016-2017 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: GPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Default values for front end config and CPLD constants.
|
||||
--
|
||||
-- Contains the revision constants that must be bumped when the CPLD is updated.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgMgCpld.all;
|
||||
|
||||
package PkgSetup is
|
||||
|
||||
|
||||
constant kRdWtWidth : integer := 1;
|
||||
constant kAddrWidth : integer := 7;
|
||||
constant kDataWidth : integer := 16;
|
||||
constant kTotalWidth : integer := kRdWtWidth + kAddrWidth + kDataWidth;
|
||||
|
||||
subtype InterfaceData_t is std_logic_vector(kDataWidth-1 downto 0);
|
||||
|
||||
constant kSignature : InterfaceData_t := x"CAFE";
|
||||
|
||||
|
||||
-- UPDATE THESE REVISIONS when making changes to the CPLD -----------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
constant kMinorRev : InterfaceData_t := std_logic_vector(to_unsigned(0,kDataWidth));
|
||||
constant kMajorRev : InterfaceData_t := std_logic_vector(to_unsigned(5,kDataWidth));
|
||||
-- Currently just the timestamp of the build time/date: yymmddhh
|
||||
constant kBuildCode : std_logic_vector(31 downto 0) := X"18010408";
|
||||
|
||||
|
||||
function kTxChDefault return InterfaceData_t;
|
||||
function kTxChDefaultRun return InterfaceData_t;
|
||||
function kRxChDefault0 return InterfaceData_t;
|
||||
function kRxChDefault1 return InterfaceData_t;
|
||||
function kRxChDefault0Run return InterfaceData_t;
|
||||
function kRxChDefault1Run return InterfaceData_t;
|
||||
|
||||
function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Tx2TrxMod (kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
|
||||
function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
package body PkgSetup is
|
||||
|
||||
function kTxChDefault return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize));
|
||||
RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kShutdownTxSw1, kCh1TxSw1Size));
|
||||
RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size));
|
||||
RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size));
|
||||
RetVal(kCh1TxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1TxMixerEn) := '0';
|
||||
RetVal(kCh1TxAmpEn) := '0';
|
||||
RetVal(kCh1TxPaEn) := '0';
|
||||
RetVal(kCh1TxLed) := '0';
|
||||
RetVal(kCh1MykEnTx) := '1';
|
||||
return RetVal;
|
||||
end kTxChDefault;
|
||||
|
||||
function kTxChDefaultRun return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize));
|
||||
RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kFromTxFilterLp3400MHz, kCh1TxSw1Size));
|
||||
RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size));
|
||||
RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size));
|
||||
RetVal(kCh1TxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1TxMixerEn) := '0';
|
||||
RetVal(kCh1TxAmpEn) := '1';
|
||||
RetVal(kCh1TxPaEn) := '1';
|
||||
RetVal(kCh1TxLed) := '1';
|
||||
RetVal(kCh1MykEnTx) := '1';
|
||||
return RetVal;
|
||||
end kTxChDefaultRun;
|
||||
|
||||
|
||||
|
||||
|
||||
function kRxChDefault0 return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size));
|
||||
RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kShutdownSw2, kCh1RxSw2Size));
|
||||
RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kShutdownSw3, kCh1RxSw3Size));
|
||||
RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size));
|
||||
RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size));
|
||||
return RetVal;
|
||||
end kRxChDefault0;
|
||||
|
||||
function kRxChDefault1 return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size));
|
||||
RetVal(kCh1RxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1RxMixerEn) := '0';
|
||||
RetVal(kCh1RxAmpEn) := '0';
|
||||
RetVal(kCh1RxLna1En) := '0';
|
||||
RetVal(kCh1RxLna2En) := '0';
|
||||
RetVal(kCh1Rx2Led) := '0';
|
||||
RetVal(kCh1RxLed) := '0';
|
||||
RetVal(kCh1MykEnRx) := '1';
|
||||
return RetVal;
|
||||
end kRxChDefault1;
|
||||
|
||||
function kRxChDefault0Run return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size));
|
||||
RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kLowerFilterBankToSwitch3, kCh1RxSw2Size));
|
||||
RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kFilter2100x2850MHz, kCh1RxSw3Size));
|
||||
RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size));
|
||||
RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size));
|
||||
return RetVal;
|
||||
end kRxChDefault0Run;
|
||||
|
||||
function kRxChDefault1Run return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size));
|
||||
RetVal(kCh1RxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1RxMixerEn) := '0';
|
||||
RetVal(kCh1RxAmpEn) := '1';
|
||||
RetVal(kCh1RxLna1En) := '1';
|
||||
RetVal(kCh1RxLna2En) := '1';
|
||||
RetVal(kCh1Rx2Led) := '1'; -- turn on a LED for grins
|
||||
RetVal(kCh1RxLed) := '0';
|
||||
RetVal(kCh1MykEnRx) := '1';
|
||||
return RetVal;
|
||||
end kRxChDefault1Run;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 2);
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3);
|
||||
return RetVal;
|
||||
end Tx2Switch2Mod;
|
||||
|
||||
function Tx2TrxMod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
if kCh1Val = "00" then RetVal := "00";
|
||||
elsif kCh1Val = "01" then RetVal := "10";
|
||||
elsif kCh1Val = "10" then RetVal := "01";
|
||||
elsif kCh1Val = "11" then RetVal := "11";
|
||||
else RetVal := "00"; end if;
|
||||
return RetVal;
|
||||
end Tx2TrxMod;
|
||||
|
||||
|
||||
|
||||
function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is binary, so we need to mux.
|
||||
if kCh1Val = "00" then RetVal := "01";
|
||||
elsif kCh1Val = "01" then RetVal := "00";
|
||||
elsif kCh1Val = "10" then RetVal := "11";
|
||||
elsif kCh1Val = "11" then RetVal := "10";
|
||||
else RetVal := "00"; end if;
|
||||
return RetVal;
|
||||
end Rx2Switch1Mod;
|
||||
|
||||
function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is binary, so we need to mux.
|
||||
if kCh1Val = "00" then RetVal := "00";
|
||||
elsif kCh1Val = "01" then RetVal := "11";
|
||||
elsif kCh1Val = "10" then RetVal := "10";
|
||||
elsif kCh1Val = "11" then RetVal := "01";
|
||||
else RetVal := "00"; end if;
|
||||
return RetVal;
|
||||
end Rx2Switch2Mod;
|
||||
|
||||
function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is binary, so we need to mux.
|
||||
if kCh1Val = "000" then RetVal := "100";
|
||||
elsif kCh1Val = "001" then RetVal := "101";
|
||||
elsif kCh1Val = "010" then RetVal := "110";
|
||||
elsif kCh1Val = "011" then RetVal := "011";
|
||||
elsif kCh1Val = "100" then RetVal := "001";
|
||||
elsif kCh1Val = "101" then RetVal := "000";
|
||||
elsif kCh1Val = "110" then RetVal := "010";
|
||||
elsif kCh1Val = "111" then RetVal := "111";
|
||||
else RetVal := "000"; end if;
|
||||
return RetVal;
|
||||
end Rx2Switch3Mod;
|
||||
|
||||
function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2);
|
||||
return RetVal;
|
||||
end Rx2Switch4Mod;
|
||||
|
||||
function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 2);
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3);
|
||||
return RetVal;
|
||||
end Rx2Switch5Mod;
|
||||
|
||||
function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2);
|
||||
return RetVal;
|
||||
end Rx2Switch6Mod;
|
||||
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,160 @@
|
||||
#
|
||||
# Copyright 2017 Ettus Research, A National Instruments Company
|
||||
# SPDX-License-Identifier: LGPL-3.0
|
||||
#
|
||||
|
||||
# All the magic numbers come from the "/n3xx/dboards/mg/doc/mg_timing.xlsx" timing
|
||||
# analysis spreadsheet. Analysis should be re-performed every time a board rev occurs
|
||||
# that affects the CPLD interfaces.
|
||||
|
||||
## PS Slave Constraints #################################################################
|
||||
# - PsClk Rate
|
||||
# - PsClk to SDI
|
||||
# - PsClk to LE (sync and async paths)
|
||||
# - PsClk to SDO
|
||||
|
||||
# Maximum 4 MHz clock rate! This is heavily limited by the read data turnaround time...
|
||||
# and could be up to 20 MHz if only performing writes.
|
||||
create_clock -name PsClk -period 250 [get_ports {PsSpiSck}]
|
||||
|
||||
# SDI is both registered in the CPLD and used as a direct passthrough. First constrain
|
||||
# the input delay on the local paths inside the CPLD. Passthrough constraints
|
||||
# are handled elsewhere.
|
||||
|
||||
set PsSdiInputDelayMax 22.303
|
||||
set PsSdiInputDelayMin -19.019
|
||||
|
||||
# SDI is driven from the PS on the falling edge of the Clk. Worst-case data-clock skew
|
||||
# is around +/-20ns due to FPGA routing delays and board buffering. Complete timing
|
||||
# analysis is performed and recorded elsewhere.
|
||||
set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiSdi] -clock_fall
|
||||
set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiSdi] -clock_fall
|
||||
|
||||
# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and
|
||||
# synchronously to latch data. First, constrain the overall input delay for sync use.
|
||||
# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives
|
||||
# but we still constrain it identically to the SDI in case something goes amiss.
|
||||
set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiLe] -clock_fall
|
||||
set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiLe] -clock_fall
|
||||
# Then set a false path only on the async reset flops.
|
||||
set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*]
|
||||
set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*]
|
||||
|
||||
# Constrain MISO as snugly as possible through the CPLD without making the tools work
|
||||
# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns.
|
||||
# Math for Max = T_clk/2 - 60 = 250/2 - 60 = 65 ns.
|
||||
set PsSdoOutputDelayMax 60
|
||||
set PsSdoOutputDelayMin -10
|
||||
|
||||
set_output_delay -clock PsClk -max $PsSdoOutputDelayMax [get_ports sPsSpiSdo]
|
||||
set_output_delay -clock PsClk -min $PsSdoOutputDelayMin [get_ports sPsSpiSdo]
|
||||
|
||||
|
||||
|
||||
## PL Slave Constraints #################################################################
|
||||
# - PlClk Rate
|
||||
# - PlClk to SDI
|
||||
# - PlClk to LE (sync and async paths)
|
||||
# - PlClk to SDO
|
||||
|
||||
# Maximum 5 MHz clock rate!
|
||||
create_clock -name PlClk -period 200 [get_ports {PlSpiSck}]
|
||||
|
||||
# SDI is both registered in the CPLD and used as a direct passthrough. First constrain
|
||||
# the input delay on the local paths inside the CPLD. Passthrough constraints
|
||||
# are handled elsewhere.
|
||||
|
||||
set PlSdiInputDelayMax 10.445
|
||||
set PlSdiInputDelayMin -10.378
|
||||
|
||||
# SDI is driven from the FPGA on the falling edge of the Clk. Worst-case data-clock skew
|
||||
# is around +/-10ns. Complete timing analysis is performed and recorded elsewhere.
|
||||
set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiSdi] -clock_fall
|
||||
set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiSdi] -clock_fall
|
||||
|
||||
# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and
|
||||
# synchronously to latch data. First, constrain the overall input delay for sync use.
|
||||
# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives
|
||||
# but we still constrain it identically to the SDI in case something goes amiss.
|
||||
set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiLe] -clock_fall
|
||||
set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiLe] -clock_fall
|
||||
# Then set a false path only on the async reset flops.
|
||||
set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}]
|
||||
set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}]
|
||||
|
||||
# Constrain MISO as snugly as possible through the CPLD without making the tools work
|
||||
# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns.
|
||||
# Math for Max = T_clk/2 - 35 = 200/2 - 35 = 65 ns.
|
||||
set PlSdoOutputDelayMax 35
|
||||
set PlSdoOutputDelayMin -10
|
||||
|
||||
set_output_delay -clock PlClk -max $PlSdoOutputDelayMax [get_ports lPlSpiSdo]
|
||||
set_output_delay -clock PlClk -min $PlSdoOutputDelayMin [get_ports lPlSpiSdo]
|
||||
|
||||
|
||||
|
||||
## Passthrough Constraints ##############################################################
|
||||
# - LMK SYNC
|
||||
# - PlClk/PsClk passthrough
|
||||
# - SDI passthrough for both
|
||||
# - SDO return mux passthrough for both
|
||||
# - Cs_n passthrough for both
|
||||
|
||||
# LMK Sync Passthrough: constrain min and max delays for output
|
||||
set_max_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 17
|
||||
set_min_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 2
|
||||
|
||||
# SPI Passthroughs: constrain min and max delays for outputs and inputs.
|
||||
# Since the SDI ports have input delays pre-defined above, we have to remove those from
|
||||
# the delay analysis here by adding the input delay to the constraint.
|
||||
# Similarly, for the SDO pins add the output delay to the constraint.
|
||||
set SpiMaxDelay 25
|
||||
set SpiMinDelay 5
|
||||
|
||||
# PS
|
||||
set_max_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMax + $SpiMaxDelay]
|
||||
set_min_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMin + $SpiMinDelay]
|
||||
set_max_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMinDelay
|
||||
set_max_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMinDelay
|
||||
set_max_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMaxDelay + $PsSdoOutputDelayMax]
|
||||
set_min_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMinDelay + $PsSdoOutputDelayMin]
|
||||
|
||||
# PL
|
||||
set_max_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMax + $SpiMaxDelay]
|
||||
set_min_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMin + $SpiMinDelay]
|
||||
set_max_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMinDelay
|
||||
set_max_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMinDelay
|
||||
set_max_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMaxDelay + $PlSdoOutputDelayMax]
|
||||
set_min_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMinDelay + $PlSdoOutputDelayMin]
|
||||
|
||||
|
||||
|
||||
## Async Inputs #########################################################################
|
||||
# aLmkStatus2 aRxLoLockDetect aTxLoLockDetect
|
||||
set_false_path -from [get_ports {aRxLoLockDetect}]
|
||||
set_false_path -from [get_ports {aTxLoLockDetect}]
|
||||
|
||||
|
||||
|
||||
## Async Outputs ########################################################################
|
||||
# aMkReset_n aVcxoCtrl
|
||||
set_false_path -to [get_ports {aMkReset_n}]
|
||||
set_false_path -to [get_ports {aVcxoCtrl}]
|
||||
|
||||
|
||||
|
||||
## Sync Front End Outputs ###############################################################
|
||||
# All we need to do here is constrain for maximum path delay from the aAtr(Rx|Tx)(1|2)
|
||||
# control bits toggling to the outputs for aCh1* and aCh2* toggling. Just in case the
|
||||
# user attempts to write the ATR while it's in use, we also constrain from the flops
|
||||
# to the pins... which covers all paths... so just to -to option is needed.
|
||||
set_max_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 40
|
||||
set_min_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 5
|
||||
|
||||
# We don't care about the LED timing whatsoever. Let's not have them clogging up our
|
||||
# precious timing paths.
|
||||
set_false_path -to [get_ports {aCh*Led*}]
|
||||
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
|
||||
# Date created = 14:51:27 February 24, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "16.1"
|
||||
DATE = "14:51:27 February 24, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "TopCpld"
|
||||
@@ -0,0 +1,313 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
|
||||
# Date created = 14:51:27 February 24, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# TopCpld_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX V"
|
||||
set_global_assignment -name DEVICE 5M570ZF256I5
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:51:27 FEBRUARY 24, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name SDC_FILE Timing.sdc
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name GENERATE_SVF_FILE ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
|
||||
|
||||
set_location_assignment PIN_C3 -to aCh2RxSw4[0]
|
||||
set_location_assignment PIN_C2 -to aCh2TxPaEn
|
||||
set_location_assignment PIN_D3 -to aCh2RxSw6[0]
|
||||
set_location_assignment PIN_D1 -to aCh2RxSw4[1]
|
||||
set_location_assignment PIN_D2 -to aCh2TxSw3
|
||||
set_location_assignment PIN_E1 -to aCh2RxSw4[2]
|
||||
set_location_assignment PIN_E4 -to aCh2RxSw7[1]
|
||||
set_location_assignment PIN_F2 -to aCh2RxSw6[1]
|
||||
set_location_assignment PIN_E3 -to aCh2RxSw7[0]
|
||||
set_location_assignment PIN_F1 -to aCh2RxSw5[0]
|
||||
set_location_assignment PIN_E2 -to aCh2RxSw5[1]
|
||||
set_location_assignment PIN_G2 -to aCh2RxSw5[3]
|
||||
set_location_assignment PIN_F3 -to aCh2TxSw4[0]
|
||||
set_location_assignment PIN_G1 -to aCh2RxSw6[2]
|
||||
set_location_assignment PIN_G3 -to aCh2TxSw4[1]
|
||||
set_location_assignment PIN_H2 -to aCh2TxAmpEn
|
||||
set_location_assignment PIN_H1 -to aCh2RxSw5[2]
|
||||
set_location_assignment PIN_J1 -to aCh2TxMixerEn
|
||||
set_location_assignment PIN_H5 -to aLoSpiSync
|
||||
set_location_assignment PIN_J2 -to aCh2RxMixerEn
|
||||
#set_location_assignment PIN_L3 -to aLmkSpiSdio
|
||||
set_location_assignment PIN_K1 -to aCh2TxSw5[1]
|
||||
set_location_assignment PIN_K2 -to aCh2TxSw5[0]
|
||||
set_location_assignment PIN_M2 -to aLmkSpiSdio
|
||||
set_location_assignment PIN_L1 -to aCh2RxSw8[0]
|
||||
set_location_assignment PIN_M3 -to lPlSpiSdi
|
||||
set_location_assignment PIN_L2 -to aCh2RxSw8[1]
|
||||
set_location_assignment PIN_M1 -to aCh2RxAmpEn
|
||||
set_location_assignment PIN_N2 -to aLmkSpiSck
|
||||
set_location_assignment PIN_N1 -to aLmkSpiCs_n
|
||||
set_location_assignment PIN_N3 -to PlSpiSck
|
||||
# set_location_assignment PIN_P2 -to lPlSpiLe
|
||||
set_location_assignment PIN_R3 -to aMkReset_n
|
||||
set_location_assignment PIN_R1 -to lPlSpiLe
|
||||
set_location_assignment PIN_T2 -to aLmkSync
|
||||
set_location_assignment PIN_R4 -to aVcxoCtrl
|
||||
set_location_assignment PIN_T4 -to aDacDin
|
||||
set_location_assignment PIN_T5 -to aDacSync_n
|
||||
set_location_assignment PIN_R6 -to aPlSpiAddr[2]
|
||||
set_location_assignment PIN_R5 -to aDacSck
|
||||
set_location_assignment PIN_T6 -to aPlSpiAddr[1]
|
||||
set_location_assignment PIN_R7 -to aLmkClkinSel[0]
|
||||
set_location_assignment PIN_T7 -to lPlSpiSdo
|
||||
set_location_assignment PIN_P8 -to sPsSpiLe
|
||||
set_location_assignment PIN_R8 -to aPsSpiAddr[1]
|
||||
set_location_assignment PIN_P9 -to aPlSpiAddr[0]
|
||||
set_location_assignment PIN_T8 -to PsSpiSck
|
||||
set_location_assignment PIN_T9 -to aPsSpiAddr[0]
|
||||
set_location_assignment PIN_R9 -to sPsSpiSdi
|
||||
set_location_assignment PIN_P10 -to aAtrRx1
|
||||
set_location_assignment PIN_T10 -to sPsSpiSdo
|
||||
set_location_assignment PIN_P11 -to aAtrTx2
|
||||
set_location_assignment PIN_R10 -to aRxLoLockDetect
|
||||
set_location_assignment PIN_R12 -to aRxLoSck
|
||||
set_location_assignment PIN_T11 -to aTxLoLockDetect
|
||||
set_location_assignment PIN_P12 -to aAtrRx2
|
||||
set_location_assignment PIN_R11 -to aRxLoDin
|
||||
set_location_assignment PIN_T12 -to aRxLoCs_n
|
||||
set_location_assignment PIN_R13 -to aTxLoDin
|
||||
set_location_assignment PIN_T13 -to aRxLoMuxOut
|
||||
set_location_assignment PIN_P13 -to aAtrTx1
|
||||
set_location_assignment PIN_T15 -to aTxLoSck
|
||||
set_location_assignment PIN_R14 -to aTxLoCs_n
|
||||
set_location_assignment PIN_R16 -to aTxLoMuxOut
|
||||
set_location_assignment PIN_P14 -to aMkTx1En
|
||||
set_location_assignment PIN_N15 -to aMkRx2En
|
||||
set_location_assignment PIN_P15 -to aMkRx1En
|
||||
set_location_assignment PIN_N16 -to aMkTx2En
|
||||
set_location_assignment PIN_K15 -to aCh1TxSw5[1]
|
||||
set_location_assignment PIN_L14 -to aCh1RxMixerEn
|
||||
set_location_assignment PIN_K16 -to aCh1TxMixerEn
|
||||
set_location_assignment PIN_K14 -to aCh1RxSw8[0]
|
||||
set_location_assignment PIN_J15 -to aCh1TxAmpEn
|
||||
set_location_assignment PIN_J14 -to aCh1RxSw8[1]
|
||||
set_location_assignment PIN_J16 -to aCh1TxSw5[0]
|
||||
set_location_assignment PIN_H14 -to aCh1RxAmpEn
|
||||
set_location_assignment PIN_H16 -to aCh1TxSw4[0]
|
||||
set_location_assignment PIN_G14 -to aCh1TxSw4[1]
|
||||
set_location_assignment PIN_H15 -to aCh1RxSw5[1]
|
||||
set_location_assignment PIN_F14 -to aCh1RxSw7[1]
|
||||
set_location_assignment PIN_G16 -to aCh1RxSw5[0]
|
||||
set_location_assignment PIN_G15 -to aCh1RxSw4[0]
|
||||
set_location_assignment PIN_E14 -to aCh1RxSw6[1]
|
||||
set_location_assignment PIN_F16 -to aCh1RxSw2[1]
|
||||
set_location_assignment PIN_E13 -to aCh1RxSw7[0]
|
||||
set_location_assignment PIN_F15 -to aCh1RxSw2[0]
|
||||
set_location_assignment PIN_D14 -to aCh1RxSw6[2]
|
||||
set_location_assignment PIN_E16 -to aCh1RxSw6[0]
|
||||
set_location_assignment PIN_E15 -to aCh1TxSw3
|
||||
set_location_assignment PIN_C15 -to aCh1RxSw5[2]
|
||||
set_location_assignment PIN_D16 -to aCh1TxPaEn
|
||||
set_location_assignment PIN_C14 -to aCh1RxSw4[1]
|
||||
set_location_assignment PIN_D15 -to aCh1RxSw5[3]
|
||||
set_location_assignment PIN_B14 -to aCh1TxSw2[3]
|
||||
set_location_assignment PIN_B16 -to aCh1RxLna2En
|
||||
set_location_assignment PIN_C13 -to aCh1RxSw4[2]
|
||||
set_location_assignment PIN_A15 -to aCh1TxSw2[2]
|
||||
set_location_assignment PIN_B13 -to aCh1TxSw2[1]
|
||||
set_location_assignment PIN_A13 -to aCh1TxSw2[0]
|
||||
set_location_assignment PIN_C12 -to aCh1RxSw1[0]
|
||||
set_location_assignment PIN_B12 -to aCh1TxSw1[0]
|
||||
set_location_assignment PIN_D12 -to aCh1RxSw1[1]
|
||||
set_location_assignment PIN_A12 -to aCh1TxSw1[1]
|
||||
set_location_assignment PIN_C11 -to aCh1LedTx
|
||||
set_location_assignment PIN_B11 -to aCh1RxLna1En
|
||||
set_location_assignment PIN_D11 -to aCh2RxSw1[1]
|
||||
set_location_assignment PIN_A11 -to aCh1RxSw3[2]
|
||||
set_location_assignment PIN_C10 -to aCh1LedRx
|
||||
set_location_assignment PIN_B10 -to aCh1RxSw3[1]
|
||||
set_location_assignment PIN_C9 -to aCh1LedRx2
|
||||
set_location_assignment PIN_A10 -to aCh1RxSw3[0]
|
||||
set_location_assignment PIN_C8 -to aCh2LedRx2
|
||||
set_location_assignment PIN_B9 -to aCh1SwTrx[1]
|
||||
set_location_assignment PIN_A9 -to aCh1SwTrx[0]
|
||||
set_location_assignment PIN_A8 -to aCh2SwTrx[0]
|
||||
set_location_assignment PIN_C7 -to aCh2RxSw3[0]
|
||||
set_location_assignment PIN_B8 -to aCh2SwTrx[1]
|
||||
set_location_assignment PIN_C6 -to aCh2LedRx
|
||||
set_location_assignment PIN_A7 -to aCh2RxSw3[1]
|
||||
set_location_assignment PIN_B5 -to aCh2TxSw1[0]
|
||||
set_location_assignment PIN_C5 -to aCh2RxSw1[0]
|
||||
set_location_assignment PIN_A6 -to aCh2TxSw1[1]
|
||||
set_location_assignment PIN_D5 -to aCh2LedTx
|
||||
set_location_assignment PIN_B6 -to aCh2RxSw3[2]
|
||||
set_location_assignment PIN_B4 -to aCh2RxLna2En
|
||||
set_location_assignment PIN_A5 -to aCh2RxLna1En
|
||||
set_location_assignment PIN_C4 -to aCh2RxSw2[0]
|
||||
set_location_assignment PIN_A4 -to aCh2TxSw2[1]
|
||||
set_location_assignment PIN_D4 -to aCh2RxSw2[1]
|
||||
set_location_assignment PIN_A2 -to aCh2TxSw2[3]
|
||||
set_location_assignment PIN_B3 -to aCh2TxSw2[0]
|
||||
set_location_assignment PIN_B1 -to aCh2TxSw2[2]
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
|
||||
set_global_assignment -name GENERATE_JAM_FILE ON
|
||||
set_global_assignment -name GENERATE_JBC_FILE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxPaEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSdio
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiCs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkReset_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSync
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aVcxoCtrl
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacDin
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSync_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to lPlSpiSdo
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sPsSpiSdo
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoDin
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoCs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoDin
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoCs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxPaEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedTx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedTx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[2]
|
||||
set_global_assignment -name SEED 11
|
||||
set_global_assignment -name VHDL_FILE PkgMgCpld.vhd
|
||||
set_global_assignment -name VHDL_FILE PkgSetup.vhd
|
||||
set_global_assignment -name VHDL_FILE TopCpld.vhd
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY TopCpld
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user