Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,34 @@
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#
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# Copyright 2017 Ettus Research LLC
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#
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##################################################
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# DB IFC Sources
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##################################################
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MAGNESIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/db_ifc/, \
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DbCore.vhd \
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DaughterboardRegs.vhd \
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ClockingRegs.vhd \
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PkgMgPersonality.vhd \
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PkgDaughterboardRegMap.vhd \
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PkgClockingRegMap.vhd \
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PkgJesdConfig.vhd \
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RadioClocking.vhd \
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Jesd204bXcvrCore.edf \
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))
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MAGNESIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \
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n3xx.v \
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))
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MAGNESIUM_DB_TIMING_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \
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db_timing.xdc \
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))
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MAGNESIUM_DB0_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \
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db0_pins.xdc \
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))
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MAGNESIUM_DB1_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \
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db1_pins.xdc \
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))
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@@ -0,0 +1,22 @@
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#
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# Copyright 2018 Ettus Research, a National Instruments Company
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#
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.PHONY: all clean
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SRCS=TopCpld.qpf TopCpld.qsf Timing.sdc PkgMgCpld.vhd PkgSetup.vhd TopCpld.vhd
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all: output_files/TopCpld.svf
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cpld-magnesium-revc.svf: output_files/TopCpld.pof
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quartus_cpf --convert --frequency 10.0MHz --voltage 3.3 --operation p $? $@
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output_files/TopCpld.pof: $(SRCS)
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quartus_map TopCpld
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quartus_fit TopCpld
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quartus_asm TopCpld
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quartus_sta TopCpld
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clean:
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rm -rf db incremental_db output_files simulation cpld-magnesium-revc.svf
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@@ -0,0 +1,424 @@
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-------------------------------------------------------------------------------
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--
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-- File: PkgMgCpld.vhd
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-- Author: Autogenerated by XmlParse
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-- Original Project: --
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-- Date: --
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--
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-------------------------------------------------------------------------------
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-- Copyright 2016-2017 Ettus Research, A National Instruments Company
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-- SPDX-License-Identifier: GPL-3.0
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-------------------------------------------------------------------------------
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--
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-- Purpose:
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-- The constants in this file are autogenerated by XmlParse and should
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-- be used by testbench code to access specific register fields.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package PkgMgCpld is
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--===============================================================================
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-- A numerically ordered list of registers and their VHDL source files
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--===============================================================================
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-- SignatureReg : 0x0 (TopCpld.vhd)
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-- MinorRevReg : 0x1 (TopCpld.vhd)
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-- MajorRevReg : 0x2 (TopCpld.vhd)
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-- BuildCodeLSB : 0x3 (TopCpld.vhd)
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-- BuildCodeMSB : 0x4 (TopCpld.vhd)
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-- Scratch : 0x5 (TopCpld.vhd)
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-- CpldControl : 0x10 (TopCpld.vhd)
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-- LmkControl : 0x11 (TopCpld.vhd)
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-- LoStatus : 0x12 (TopCpld.vhd)
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-- MykonosControl : 0x13 (TopCpld.vhd)
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-- PlScratch : 0x40 (TopCpld.vhd)
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-- PlCpldControl : 0x41 (TopCpld.vhd)
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-- TxCh1_Idle : 0x50 (TopCpld.vhd)
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-- RxCh1_0_Idle : 0x51 (TopCpld.vhd)
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-- RxCh1_1_Idle : 0x52 (TopCpld.vhd)
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-- TxCh1_TxOn : 0x53 (TopCpld.vhd)
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-- RxCh1_0_RxOn : 0x54 (TopCpld.vhd)
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-- RxCh1_1_RxOn : 0x55 (TopCpld.vhd)
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-- TxCh2_Idle : 0x60 (TopCpld.vhd)
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-- RxCh2_0_Idle : 0x61 (TopCpld.vhd)
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-- RxCh2_1_Idle : 0x62 (TopCpld.vhd)
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-- TxCh2_TxOn : 0x63 (TopCpld.vhd)
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-- RxCh2_0_RxOn : 0x64 (TopCpld.vhd)
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-- RxCh2_1_RxOn : 0x65 (TopCpld.vhd)
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--===============================================================================
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-- RegTypes
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--===============================================================================
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--===============================================================================
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-- Register Group PsSpi_CpldRegisters
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--===============================================================================
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-- SignatureReg Register (from TopCpld.vhd)
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constant kSignatureReg : integer := 16#0#; -- Register Offset
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constant kSignatureRegSize: integer := 16; -- register width in bits
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constant kSignatureRegMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kProductSignatureSize : integer := 16; --SignatureReg:ProductSignature
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constant kProductSignatureMsb : integer := 15; --SignatureReg:ProductSignature
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constant kProductSignature : integer := 0; --SignatureReg:ProductSignature
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-- MinorRevReg Register (from TopCpld.vhd)
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constant kMinorRevReg : integer := 16#1#; -- Register Offset
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constant kMinorRevRegSize: integer := 16; -- register width in bits
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constant kMinorRevRegMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kCpldMinorRevisionSize : integer := 16; --MinorRevReg:CpldMinorRevision
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constant kCpldMinorRevisionMsb : integer := 15; --MinorRevReg:CpldMinorRevision
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constant kCpldMinorRevision : integer := 0; --MinorRevReg:CpldMinorRevision
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-- MajorRevReg Register (from TopCpld.vhd)
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constant kMajorRevReg : integer := 16#2#; -- Register Offset
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constant kMajorRevRegSize: integer := 16; -- register width in bits
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constant kMajorRevRegMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kCpldMajorRevisionSize : integer := 16; --MajorRevReg:CpldMajorRevision
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constant kCpldMajorRevisionMsb : integer := 15; --MajorRevReg:CpldMajorRevision
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constant kCpldMajorRevision : integer := 0; --MajorRevReg:CpldMajorRevision
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-- BuildCodeLSB Register (from TopCpld.vhd)
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constant kBuildCodeLSB : integer := 16#3#; -- Register Offset
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constant kBuildCodeLSBSize: integer := 16; -- register width in bits
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constant kBuildCodeLSBMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kBuildCodeHHSize : integer := 8; --BuildCodeLSB:BuildCodeHH
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constant kBuildCodeHHMsb : integer := 7; --BuildCodeLSB:BuildCodeHH
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constant kBuildCodeHH : integer := 0; --BuildCodeLSB:BuildCodeHH
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constant kBuildCodeDDSize : integer := 8; --BuildCodeLSB:BuildCodeDD
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constant kBuildCodeDDMsb : integer := 15; --BuildCodeLSB:BuildCodeDD
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constant kBuildCodeDD : integer := 8; --BuildCodeLSB:BuildCodeDD
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-- BuildCodeMSB Register (from TopCpld.vhd)
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constant kBuildCodeMSB : integer := 16#4#; -- Register Offset
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constant kBuildCodeMSBSize: integer := 16; -- register width in bits
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constant kBuildCodeMSBMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kBuildCodeMMSize : integer := 8; --BuildCodeMSB:BuildCodeMM
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constant kBuildCodeMMMsb : integer := 7; --BuildCodeMSB:BuildCodeMM
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constant kBuildCodeMM : integer := 0; --BuildCodeMSB:BuildCodeMM
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constant kBuildCodeYYSize : integer := 8; --BuildCodeMSB:BuildCodeYY
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constant kBuildCodeYYMsb : integer := 15; --BuildCodeMSB:BuildCodeYY
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constant kBuildCodeYY : integer := 8; --BuildCodeMSB:BuildCodeYY
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-- Scratch Register (from TopCpld.vhd)
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constant kScratch : integer := 16#5#; -- Register Offset
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constant kScratchSize: integer := 16; -- register width in bits
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constant kScratchMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kScratchValSize : integer := 16; --Scratch:ScratchVal
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constant kScratchValMsb : integer := 15; --Scratch:ScratchVal
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constant kScratchVal : integer := 0; --Scratch:ScratchVal
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-- CpldControl Register (from TopCpld.vhd)
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constant kCpldControl : integer := 16#10#; -- Register Offset
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constant kCpldControlSize: integer := 16; -- register width in bits
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constant kCpldControlMask : std_logic_vector(15 downto 0) := X"0001";
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constant kCpldResetSize : integer := 1; --CpldControl:CpldReset
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constant kCpldResetMsb : integer := 0; --CpldControl:CpldReset
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constant kCpldReset : integer := 0; --CpldControl:CpldReset
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-- LmkControl Register (from TopCpld.vhd)
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constant kLmkControl : integer := 16#11#; -- Register Offset
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constant kLmkControlSize: integer := 16; -- register width in bits
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constant kLmkControlMask : std_logic_vector(15 downto 0) := X"0010";
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constant kVcxoControlSize : integer := 1; --LmkControl:VcxoControl
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constant kVcxoControlMsb : integer := 4; --LmkControl:VcxoControl
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constant kVcxoControl : integer := 4; --LmkControl:VcxoControl
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-- LoStatus Register (from TopCpld.vhd)
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constant kLoStatus : integer := 16#12#; -- Register Offset
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constant kLoStatusSize: integer := 16; -- register width in bits
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constant kLoStatusMask : std_logic_vector(15 downto 0) := X"0011";
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constant kRxLoLockDetectSize : integer := 1; --LoStatus:RxLoLockDetect
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constant kRxLoLockDetectMsb : integer := 0; --LoStatus:RxLoLockDetect
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constant kRxLoLockDetect : integer := 0; --LoStatus:RxLoLockDetect
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constant kTxLoLockDetectSize : integer := 1; --LoStatus:TxLoLockDetect
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constant kTxLoLockDetectMsb : integer := 4; --LoStatus:TxLoLockDetect
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constant kTxLoLockDetect : integer := 4; --LoStatus:TxLoLockDetect
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-- MykonosControl Register (from TopCpld.vhd)
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constant kMykonosControl : integer := 16#13#; -- Register Offset
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constant kMykonosControlSize: integer := 16; -- register width in bits
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constant kMykonosControlMask : std_logic_vector(15 downto 0) := X"0001";
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constant kMykonosResetSize : integer := 1; --MykonosControl:MykonosReset
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constant kMykonosResetMsb : integer := 0; --MykonosControl:MykonosReset
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constant kMykonosReset : integer := 0; --MykonosControl:MykonosReset
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--===============================================================================
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-- Register Group PlSpi_FrontEndControl
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--===============================================================================
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-- Enumerated type Rx1Switch1
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constant kRx1Switch1Size : integer := 4;
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constant kTxRxInput : integer := 0; -- Rx1Switch1:TxRxInput
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constant kRxLoCalInput : integer := 1; -- Rx1Switch1:RxLoCalInput
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constant kTrxSwitchOutput : integer := 2; -- Rx1Switch1:TrxSwitchOutput
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constant kRx2Input : integer := 3; -- Rx1Switch1:Rx2Input
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-- Enumerated type Rx1Switch2
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constant kRx1Switch2Size : integer := 4;
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constant kShutdownSw2 : integer := 0; -- Rx1Switch2:ShutdownSw2
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constant kLowerFilterBankToSwitch3 : integer := 1; -- Rx1Switch2:LowerFilterBankToSwitch3
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constant kBypassPathToSwitch6 : integer := 2; -- Rx1Switch2:BypassPathToSwitch6
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constant kUpperFilterBankToSwitch4 : integer := 3; -- Rx1Switch2:UpperFilterBankToSwitch4
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-- Enumerated type Rx1Switch3
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constant kRx1Switch3Size : integer := 7;
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constant kFilter2100x2850MHz : integer := 0; -- Rx1Switch3:Filter2100x2850MHz
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constant kFilter0490LpMHz : integer := 1; -- Rx1Switch3:Filter0490LpMHz
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constant kFilter1600x2250MHz : integer := 2; -- Rx1Switch3:Filter1600x2250MHz
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constant kFilter0440x0530MHz : integer := 4; -- Rx1Switch3:Filter0440x0530MHz
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constant kFilter0650x1000MHz : integer := 5; -- Rx1Switch3:Filter0650x1000MHz
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constant kFilter1100x1575MHz : integer := 6; -- Rx1Switch3:Filter1100x1575MHz
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constant kShutdownSw3 : integer := 7; -- Rx1Switch3:ShutdownSw3
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-- Enumerated type Rx1Switch4
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constant kRx1Switch4Size : integer := 3;
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constant kFilter2100x2850MHzFrom : integer := 1; -- Rx1Switch4:Filter2100x2850MHzFrom
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constant kFilter1600x2250MHzFrom : integer := 2; -- Rx1Switch4:Filter1600x2250MHzFrom
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constant kFilter2700HpMHz : integer := 4; -- Rx1Switch4:Filter2700HpMHz
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-- Enumerated type Rx1Switch5
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constant kRx1Switch5Size : integer := 4;
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constant kFilter0440x0530MHzFrom : integer := 1; -- Rx1Switch5:Filter0440x0530MHzFrom
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constant kFilter1100x1575MHzFrom : integer := 2; -- Rx1Switch5:Filter1100x1575MHzFrom
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constant kFilter0490LpMHzFrom : integer := 4; -- Rx1Switch5:Filter0490LpMHzFrom
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constant kFilter0650x1000MHzFrom : integer := 8; -- Rx1Switch5:Filter0650x1000MHzFrom
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-- Enumerated type Rx1Switch6
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constant kRx1Switch6Size : integer := 3;
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constant kLowerFilterBankFromSwitch5 : integer := 1; -- Rx1Switch6:LowerFilterBankFromSwitch5
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constant kUpperFilterBankFromSwitch4 : integer := 2; -- Rx1Switch6:UpperFilterBankFromSwitch4
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constant kBypassPathFromSwitch2 : integer := 4; -- Rx1Switch6:BypassPathFromSwitch2
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-- Enumerated type TrxSwitch
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constant kTrxSwitchSize : integer := 4;
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constant kFromLowerFilterBankTxSw1 : integer := 0; -- TrxSwitch:FromLowerFilterBankTxSw1
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constant kFromTxUpperFilterBankLp6400MHz : integer := 1; -- TrxSwitch:FromTxUpperFilterBankLp6400MHz
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constant kRxChannelPath : integer := 2; -- TrxSwitch:RxChannelPath
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constant kBypassPathToTxSw3 : integer := 3; -- TrxSwitch:BypassPathToTxSw3
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-- Enumerated type TxSwitch1
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constant kTxSwitch1Size : integer := 4;
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constant kShutdownTxSw1 : integer := 0; -- TxSwitch1:ShutdownTxSw1
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constant kFromTxFilterLp1700MHz : integer := 1; -- TxSwitch1:FromTxFilterLp1700MHz
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constant kFromTxFilterLp3400MHz : integer := 2; -- TxSwitch1:FromTxFilterLp3400MHz
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constant kFromTxFilterLp0800MHz : integer := 3; -- TxSwitch1:FromTxFilterLp0800MHz
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-- Enumerated type TxSwitch2
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constant kTxSwitch2Size : integer := 4;
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constant kToTxFilterLp3400MHz : integer := 1; -- TxSwitch2:ToTxFilterLp3400MHz
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constant kToTxFilterLp1700MHz : integer := 2; -- TxSwitch2:ToTxFilterLp1700MHz
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constant kToTxFilterLp0800MHz : integer := 4; -- TxSwitch2:ToTxFilterLp0800MHz
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constant kToTxFilterLp6400MHz : integer := 8; -- TxSwitch2:ToTxFilterLp6400MHz
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-- Enumerated type TxSwitch3
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constant kTxSwitch3Size : integer := 2;
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constant kToTxFilterBanks : integer := 0; -- TxSwitch3:ToTxFilterBanks
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constant kBypassPathToTrxSw : integer := 1; -- TxSwitch3:BypassPathToTrxSw
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-- PlScratch Register (from TopCpld.vhd)
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constant kPlScratch : integer := 16#40#; -- Register Offset
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constant kPlScratchSize: integer := 16; -- register width in bits
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constant kPlScratchMask : std_logic_vector(15 downto 0) := X"ffff";
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constant kPlScratchValSize : integer := 16; --PlScratch:PlScratchVal
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constant kPlScratchValMsb : integer := 15; --PlScratch:PlScratchVal
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constant kPlScratchVal : integer := 0; --PlScratch:PlScratchVal
|
||||
|
||||
-- PlCpldControl Register (from TopCpld.vhd)
|
||||
constant kPlCpldControl : integer := 16#41#; -- Register Offset
|
||||
constant kPlCpldControlSize: integer := 16; -- register width in bits
|
||||
constant kPlCpldControlMask : std_logic_vector(15 downto 0) := X"0001";
|
||||
constant kPlCpldResetSize : integer := 1; --PlCpldControl:PlCpldReset
|
||||
constant kPlCpldResetMsb : integer := 0; --PlCpldControl:PlCpldReset
|
||||
constant kPlCpldReset : integer := 0; --PlCpldControl:PlCpldReset
|
||||
|
||||
-- TxCh1_Idle Register (from TopCpld.vhd)
|
||||
constant kTxCh1_Idle : integer := 16#50#; -- Register Offset
|
||||
constant kTxCh1_IdleSize: integer := 16; -- register width in bits
|
||||
constant kTxCh1_IdleMask : std_logic_vector(15 downto 0) := X"7fff";
|
||||
constant kCh1TxSw1Size : integer := 2; --TxCh1_Idle:Ch1TxSw1
|
||||
constant kCh1TxSw1Msb : integer := 1; --TxCh1_Idle:Ch1TxSw1
|
||||
constant kCh1TxSw1 : integer := 0; --TxCh1_Idle:Ch1TxSw1
|
||||
constant kCh1TxSw2Size : integer := 4; --TxCh1_Idle:Ch1TxSw2
|
||||
constant kCh1TxSw2Msb : integer := 5; --TxCh1_Idle:Ch1TxSw2
|
||||
constant kCh1TxSw2 : integer := 2; --TxCh1_Idle:Ch1TxSw2
|
||||
constant kCh1TxSw3Size : integer := 1; --TxCh1_Idle:Ch1TxSw3
|
||||
constant kCh1TxSw3Msb : integer := 6; --TxCh1_Idle:Ch1TxSw3
|
||||
constant kCh1TxSw3 : integer := 6; --TxCh1_Idle:Ch1TxSw3
|
||||
constant kCh1TxLowbandMixerPathSelectSize : integer := 1; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect
|
||||
constant kCh1TxLowbandMixerPathSelectMsb : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect
|
||||
constant kCh1TxLowbandMixerPathSelect : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect
|
||||
constant kCh1TxMixerEnSize : integer := 1; --TxCh1_Idle:Ch1TxMixerEn
|
||||
constant kCh1TxMixerEnMsb : integer := 8; --TxCh1_Idle:Ch1TxMixerEn
|
||||
constant kCh1TxMixerEn : integer := 8; --TxCh1_Idle:Ch1TxMixerEn
|
||||
constant kCh1TxAmpEnSize : integer := 1; --TxCh1_Idle:Ch1TxAmpEn
|
||||
constant kCh1TxAmpEnMsb : integer := 9; --TxCh1_Idle:Ch1TxAmpEn
|
||||
constant kCh1TxAmpEn : integer := 9; --TxCh1_Idle:Ch1TxAmpEn
|
||||
constant kCh1TxPaEnSize : integer := 1; --TxCh1_Idle:Ch1TxPaEn
|
||||
constant kCh1TxPaEnMsb : integer := 10; --TxCh1_Idle:Ch1TxPaEn
|
||||
constant kCh1TxPaEn : integer := 10; --TxCh1_Idle:Ch1TxPaEn
|
||||
constant kCh1SwTrxSize : integer := 2; --TxCh1_Idle:Ch1SwTrx
|
||||
constant kCh1SwTrxMsb : integer := 12; --TxCh1_Idle:Ch1SwTrx
|
||||
constant kCh1SwTrx : integer := 11; --TxCh1_Idle:Ch1SwTrx
|
||||
constant kCh1TxLedSize : integer := 1; --TxCh1_Idle:Ch1TxLed
|
||||
constant kCh1TxLedMsb : integer := 13; --TxCh1_Idle:Ch1TxLed
|
||||
constant kCh1TxLed : integer := 13; --TxCh1_Idle:Ch1TxLed
|
||||
constant kCh1MykEnTxSize : integer := 1; --TxCh1_Idle:Ch1MykEnTx
|
||||
constant kCh1MykEnTxMsb : integer := 14; --TxCh1_Idle:Ch1MykEnTx
|
||||
constant kCh1MykEnTx : integer := 14; --TxCh1_Idle:Ch1MykEnTx
|
||||
|
||||
-- RxCh1_0_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh1_0_Idle : integer := 16#51#; -- Register Offset
|
||||
constant kRxCh1_0_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_0_IdleMask : std_logic_vector(15 downto 0) := X"3fff";
|
||||
constant kCh1RxSw1Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw1
|
||||
constant kCh1RxSw1Msb : integer := 1; --RxCh1_0_Idle:Ch1RxSw1
|
||||
constant kCh1RxSw1 : integer := 0; --RxCh1_0_Idle:Ch1RxSw1
|
||||
constant kCh1RxSw2Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw2
|
||||
constant kCh1RxSw2Msb : integer := 3; --RxCh1_0_Idle:Ch1RxSw2
|
||||
constant kCh1RxSw2 : integer := 2; --RxCh1_0_Idle:Ch1RxSw2
|
||||
constant kCh1RxSw3Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw3
|
||||
constant kCh1RxSw3Msb : integer := 6; --RxCh1_0_Idle:Ch1RxSw3
|
||||
constant kCh1RxSw3 : integer := 4; --RxCh1_0_Idle:Ch1RxSw3
|
||||
constant kCh1RxSw4Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw4
|
||||
constant kCh1RxSw4Msb : integer := 9; --RxCh1_0_Idle:Ch1RxSw4
|
||||
constant kCh1RxSw4 : integer := 7; --RxCh1_0_Idle:Ch1RxSw4
|
||||
constant kCh1RxSw5Size : integer := 4; --RxCh1_0_Idle:Ch1RxSw5
|
||||
constant kCh1RxSw5Msb : integer := 13; --RxCh1_0_Idle:Ch1RxSw5
|
||||
constant kCh1RxSw5 : integer := 10; --RxCh1_0_Idle:Ch1RxSw5
|
||||
|
||||
-- RxCh1_1_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh1_1_Idle : integer := 16#52#; -- Register Offset
|
||||
constant kRxCh1_1_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_1_IdleMask : std_logic_vector(15 downto 0) := X"07ff";
|
||||
constant kCh1RxSw6Size : integer := 3; --RxCh1_1_Idle:Ch1RxSw6
|
||||
constant kCh1RxSw6Msb : integer := 2; --RxCh1_1_Idle:Ch1RxSw6
|
||||
constant kCh1RxSw6 : integer := 0; --RxCh1_1_Idle:Ch1RxSw6
|
||||
constant kCh1RxLowbandMixerPathSelectSize : integer := 1; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect
|
||||
constant kCh1RxLowbandMixerPathSelectMsb : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect
|
||||
constant kCh1RxLowbandMixerPathSelect : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect
|
||||
constant kCh1RxMixerEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxMixerEn
|
||||
constant kCh1RxMixerEnMsb : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn
|
||||
constant kCh1RxMixerEn : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn
|
||||
constant kCh1RxAmpEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxAmpEn
|
||||
constant kCh1RxAmpEnMsb : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn
|
||||
constant kCh1RxAmpEn : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn
|
||||
constant kCh1RxLna1EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna1En
|
||||
constant kCh1RxLna1EnMsb : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En
|
||||
constant kCh1RxLna1En : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En
|
||||
constant kCh1RxLna2EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna2En
|
||||
constant kCh1RxLna2EnMsb : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En
|
||||
constant kCh1RxLna2En : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En
|
||||
constant kCh1Rx2LedSize : integer := 1; --RxCh1_1_Idle:Ch1Rx2Led
|
||||
constant kCh1Rx2LedMsb : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led
|
||||
constant kCh1Rx2Led : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led
|
||||
constant kCh1RxLedSize : integer := 1; --RxCh1_1_Idle:Ch1RxLed
|
||||
constant kCh1RxLedMsb : integer := 9; --RxCh1_1_Idle:Ch1RxLed
|
||||
constant kCh1RxLed : integer := 9; --RxCh1_1_Idle:Ch1RxLed
|
||||
constant kCh1MykEnRxSize : integer := 1; --RxCh1_1_Idle:Ch1MykEnRx
|
||||
constant kCh1MykEnRxMsb : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx
|
||||
constant kCh1MykEnRx : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx
|
||||
|
||||
-- TxCh1_TxOn Register (from TopCpld.vhd)
|
||||
constant kTxCh1_TxOn : integer := 16#53#; -- Register Offset
|
||||
constant kTxCh1_TxOnSize: integer := 16; -- register width in bits
|
||||
constant kTxCh1_TxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh1_0_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh1_0_RxOn : integer := 16#54#; -- Register Offset
|
||||
constant kRxCh1_0_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh1_1_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh1_1_RxOn : integer := 16#55#; -- Register Offset
|
||||
constant kRxCh1_1_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh1_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- TxCh2_Idle Register (from TopCpld.vhd)
|
||||
constant kTxCh2_Idle : integer := 16#60#; -- Register Offset
|
||||
constant kTxCh2_IdleSize: integer := 16; -- register width in bits
|
||||
constant kTxCh2_IdleMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_0_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh2_0_Idle : integer := 16#61#; -- Register Offset
|
||||
constant kRxCh2_0_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_0_IdleMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_1_Idle Register (from TopCpld.vhd)
|
||||
constant kRxCh2_1_Idle : integer := 16#62#; -- Register Offset
|
||||
constant kRxCh2_1_IdleSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_1_IdleMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- TxCh2_TxOn Register (from TopCpld.vhd)
|
||||
constant kTxCh2_TxOn : integer := 16#63#; -- Register Offset
|
||||
constant kTxCh2_TxOnSize: integer := 16; -- register width in bits
|
||||
constant kTxCh2_TxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_0_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh2_0_RxOn : integer := 16#64#; -- Register Offset
|
||||
constant kRxCh2_0_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
-- RxCh2_1_RxOn Register (from TopCpld.vhd)
|
||||
constant kRxCh2_1_RxOn : integer := 16#65#; -- Register Offset
|
||||
constant kRxCh2_1_RxOnSize: integer := 16; -- register width in bits
|
||||
constant kRxCh2_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000";
|
||||
|
||||
end package;
|
||||
|
||||
package body PkgMgCpld is
|
||||
|
||||
-- function kSignatureRegRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMinorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMajorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kBuildCodeLSBRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kBuildCodeMSBRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kScratchRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kLmkControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kLoStatusRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMykonosControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kPlScratchRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kPlCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh1_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh1_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh2_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kTxCh2_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRxCh2_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,259 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: PkgSetup.vhd
|
||||
-- Author: Daniel Jepson
|
||||
-- Original Project: N310
|
||||
-- Date: 22 September 2017
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2016-2017 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: GPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Default values for front end config and CPLD constants.
|
||||
--
|
||||
-- Contains the revision constants that must be bumped when the CPLD is updated.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgMgCpld.all;
|
||||
|
||||
package PkgSetup is
|
||||
|
||||
|
||||
constant kRdWtWidth : integer := 1;
|
||||
constant kAddrWidth : integer := 7;
|
||||
constant kDataWidth : integer := 16;
|
||||
constant kTotalWidth : integer := kRdWtWidth + kAddrWidth + kDataWidth;
|
||||
|
||||
subtype InterfaceData_t is std_logic_vector(kDataWidth-1 downto 0);
|
||||
|
||||
constant kSignature : InterfaceData_t := x"CAFE";
|
||||
|
||||
|
||||
-- UPDATE THESE REVISIONS when making changes to the CPLD -----------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
constant kMinorRev : InterfaceData_t := std_logic_vector(to_unsigned(0,kDataWidth));
|
||||
constant kMajorRev : InterfaceData_t := std_logic_vector(to_unsigned(5,kDataWidth));
|
||||
-- Currently just the timestamp of the build time/date: yymmddhh
|
||||
constant kBuildCode : std_logic_vector(31 downto 0) := X"18010408";
|
||||
|
||||
|
||||
function kTxChDefault return InterfaceData_t;
|
||||
function kTxChDefaultRun return InterfaceData_t;
|
||||
function kRxChDefault0 return InterfaceData_t;
|
||||
function kRxChDefault1 return InterfaceData_t;
|
||||
function kRxChDefault0Run return InterfaceData_t;
|
||||
function kRxChDefault1Run return InterfaceData_t;
|
||||
|
||||
function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Tx2TrxMod (kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
|
||||
function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector;
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
package body PkgSetup is
|
||||
|
||||
function kTxChDefault return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize));
|
||||
RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kShutdownTxSw1, kCh1TxSw1Size));
|
||||
RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size));
|
||||
RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size));
|
||||
RetVal(kCh1TxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1TxMixerEn) := '0';
|
||||
RetVal(kCh1TxAmpEn) := '0';
|
||||
RetVal(kCh1TxPaEn) := '0';
|
||||
RetVal(kCh1TxLed) := '0';
|
||||
RetVal(kCh1MykEnTx) := '1';
|
||||
return RetVal;
|
||||
end kTxChDefault;
|
||||
|
||||
function kTxChDefaultRun return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize));
|
||||
RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kFromTxFilterLp3400MHz, kCh1TxSw1Size));
|
||||
RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size));
|
||||
RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size));
|
||||
RetVal(kCh1TxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1TxMixerEn) := '0';
|
||||
RetVal(kCh1TxAmpEn) := '1';
|
||||
RetVal(kCh1TxPaEn) := '1';
|
||||
RetVal(kCh1TxLed) := '1';
|
||||
RetVal(kCh1MykEnTx) := '1';
|
||||
return RetVal;
|
||||
end kTxChDefaultRun;
|
||||
|
||||
|
||||
|
||||
|
||||
function kRxChDefault0 return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size));
|
||||
RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kShutdownSw2, kCh1RxSw2Size));
|
||||
RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kShutdownSw3, kCh1RxSw3Size));
|
||||
RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size));
|
||||
RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size));
|
||||
return RetVal;
|
||||
end kRxChDefault0;
|
||||
|
||||
function kRxChDefault1 return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size));
|
||||
RetVal(kCh1RxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1RxMixerEn) := '0';
|
||||
RetVal(kCh1RxAmpEn) := '0';
|
||||
RetVal(kCh1RxLna1En) := '0';
|
||||
RetVal(kCh1RxLna2En) := '0';
|
||||
RetVal(kCh1Rx2Led) := '0';
|
||||
RetVal(kCh1RxLed) := '0';
|
||||
RetVal(kCh1MykEnRx) := '1';
|
||||
return RetVal;
|
||||
end kRxChDefault1;
|
||||
|
||||
function kRxChDefault0Run return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size));
|
||||
RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kLowerFilterBankToSwitch3, kCh1RxSw2Size));
|
||||
RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kFilter2100x2850MHz, kCh1RxSw3Size));
|
||||
RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size));
|
||||
RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size));
|
||||
return RetVal;
|
||||
end kRxChDefault0Run;
|
||||
|
||||
function kRxChDefault1Run return InterfaceData_t is
|
||||
variable RetVal : InterfaceData_t := (others => '0');
|
||||
begin
|
||||
RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size));
|
||||
RetVal(kCh1RxLowbandMixerPathSelect) := '0';
|
||||
RetVal(kCh1RxMixerEn) := '0';
|
||||
RetVal(kCh1RxAmpEn) := '1';
|
||||
RetVal(kCh1RxLna1En) := '1';
|
||||
RetVal(kCh1RxLna2En) := '1';
|
||||
RetVal(kCh1Rx2Led) := '1'; -- turn on a LED for grins
|
||||
RetVal(kCh1RxLed) := '0';
|
||||
RetVal(kCh1MykEnRx) := '1';
|
||||
return RetVal;
|
||||
end kRxChDefault1Run;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 2);
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3);
|
||||
return RetVal;
|
||||
end Tx2Switch2Mod;
|
||||
|
||||
function Tx2TrxMod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
if kCh1Val = "00" then RetVal := "00";
|
||||
elsif kCh1Val = "01" then RetVal := "10";
|
||||
elsif kCh1Val = "10" then RetVal := "01";
|
||||
elsif kCh1Val = "11" then RetVal := "11";
|
||||
else RetVal := "00"; end if;
|
||||
return RetVal;
|
||||
end Tx2TrxMod;
|
||||
|
||||
|
||||
|
||||
function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is binary, so we need to mux.
|
||||
if kCh1Val = "00" then RetVal := "01";
|
||||
elsif kCh1Val = "01" then RetVal := "00";
|
||||
elsif kCh1Val = "10" then RetVal := "11";
|
||||
elsif kCh1Val = "11" then RetVal := "10";
|
||||
else RetVal := "00"; end if;
|
||||
return RetVal;
|
||||
end Rx2Switch1Mod;
|
||||
|
||||
function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is binary, so we need to mux.
|
||||
if kCh1Val = "00" then RetVal := "00";
|
||||
elsif kCh1Val = "01" then RetVal := "11";
|
||||
elsif kCh1Val = "10" then RetVal := "10";
|
||||
elsif kCh1Val = "11" then RetVal := "01";
|
||||
else RetVal := "00"; end if;
|
||||
return RetVal;
|
||||
end Rx2Switch2Mod;
|
||||
|
||||
function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is binary, so we need to mux.
|
||||
if kCh1Val = "000" then RetVal := "100";
|
||||
elsif kCh1Val = "001" then RetVal := "101";
|
||||
elsif kCh1Val = "010" then RetVal := "110";
|
||||
elsif kCh1Val = "011" then RetVal := "011";
|
||||
elsif kCh1Val = "100" then RetVal := "001";
|
||||
elsif kCh1Val = "101" then RetVal := "000";
|
||||
elsif kCh1Val = "110" then RetVal := "010";
|
||||
elsif kCh1Val = "111" then RetVal := "111";
|
||||
else RetVal := "000"; end if;
|
||||
return RetVal;
|
||||
end Rx2Switch3Mod;
|
||||
|
||||
function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2);
|
||||
return RetVal;
|
||||
end Rx2Switch4Mod;
|
||||
|
||||
function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 2);
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3);
|
||||
return RetVal;
|
||||
end Rx2Switch5Mod;
|
||||
|
||||
function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector is
|
||||
variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0');
|
||||
begin
|
||||
-- Encoding for this switch is one-hot, so we just flip around the bits here.
|
||||
RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0);
|
||||
RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1);
|
||||
RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2);
|
||||
return RetVal;
|
||||
end Rx2Switch6Mod;
|
||||
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,160 @@
|
||||
#
|
||||
# Copyright 2017 Ettus Research, A National Instruments Company
|
||||
# SPDX-License-Identifier: LGPL-3.0
|
||||
#
|
||||
|
||||
# All the magic numbers come from the "/n3xx/dboards/mg/doc/mg_timing.xlsx" timing
|
||||
# analysis spreadsheet. Analysis should be re-performed every time a board rev occurs
|
||||
# that affects the CPLD interfaces.
|
||||
|
||||
## PS Slave Constraints #################################################################
|
||||
# - PsClk Rate
|
||||
# - PsClk to SDI
|
||||
# - PsClk to LE (sync and async paths)
|
||||
# - PsClk to SDO
|
||||
|
||||
# Maximum 4 MHz clock rate! This is heavily limited by the read data turnaround time...
|
||||
# and could be up to 20 MHz if only performing writes.
|
||||
create_clock -name PsClk -period 250 [get_ports {PsSpiSck}]
|
||||
|
||||
# SDI is both registered in the CPLD and used as a direct passthrough. First constrain
|
||||
# the input delay on the local paths inside the CPLD. Passthrough constraints
|
||||
# are handled elsewhere.
|
||||
|
||||
set PsSdiInputDelayMax 22.303
|
||||
set PsSdiInputDelayMin -19.019
|
||||
|
||||
# SDI is driven from the PS on the falling edge of the Clk. Worst-case data-clock skew
|
||||
# is around +/-20ns due to FPGA routing delays and board buffering. Complete timing
|
||||
# analysis is performed and recorded elsewhere.
|
||||
set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiSdi] -clock_fall
|
||||
set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiSdi] -clock_fall
|
||||
|
||||
# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and
|
||||
# synchronously to latch data. First, constrain the overall input delay for sync use.
|
||||
# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives
|
||||
# but we still constrain it identically to the SDI in case something goes amiss.
|
||||
set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiLe] -clock_fall
|
||||
set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiLe] -clock_fall
|
||||
# Then set a false path only on the async reset flops.
|
||||
set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*]
|
||||
set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*]
|
||||
|
||||
# Constrain MISO as snugly as possible through the CPLD without making the tools work
|
||||
# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns.
|
||||
# Math for Max = T_clk/2 - 60 = 250/2 - 60 = 65 ns.
|
||||
set PsSdoOutputDelayMax 60
|
||||
set PsSdoOutputDelayMin -10
|
||||
|
||||
set_output_delay -clock PsClk -max $PsSdoOutputDelayMax [get_ports sPsSpiSdo]
|
||||
set_output_delay -clock PsClk -min $PsSdoOutputDelayMin [get_ports sPsSpiSdo]
|
||||
|
||||
|
||||
|
||||
## PL Slave Constraints #################################################################
|
||||
# - PlClk Rate
|
||||
# - PlClk to SDI
|
||||
# - PlClk to LE (sync and async paths)
|
||||
# - PlClk to SDO
|
||||
|
||||
# Maximum 5 MHz clock rate!
|
||||
create_clock -name PlClk -period 200 [get_ports {PlSpiSck}]
|
||||
|
||||
# SDI is both registered in the CPLD and used as a direct passthrough. First constrain
|
||||
# the input delay on the local paths inside the CPLD. Passthrough constraints
|
||||
# are handled elsewhere.
|
||||
|
||||
set PlSdiInputDelayMax 10.445
|
||||
set PlSdiInputDelayMin -10.378
|
||||
|
||||
# SDI is driven from the FPGA on the falling edge of the Clk. Worst-case data-clock skew
|
||||
# is around +/-10ns. Complete timing analysis is performed and recorded elsewhere.
|
||||
set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiSdi] -clock_fall
|
||||
set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiSdi] -clock_fall
|
||||
|
||||
# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and
|
||||
# synchronously to latch data. First, constrain the overall input delay for sync use.
|
||||
# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives
|
||||
# but we still constrain it identically to the SDI in case something goes amiss.
|
||||
set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiLe] -clock_fall
|
||||
set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiLe] -clock_fall
|
||||
# Then set a false path only on the async reset flops.
|
||||
set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}]
|
||||
set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}]
|
||||
|
||||
# Constrain MISO as snugly as possible through the CPLD without making the tools work
|
||||
# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns.
|
||||
# Math for Max = T_clk/2 - 35 = 200/2 - 35 = 65 ns.
|
||||
set PlSdoOutputDelayMax 35
|
||||
set PlSdoOutputDelayMin -10
|
||||
|
||||
set_output_delay -clock PlClk -max $PlSdoOutputDelayMax [get_ports lPlSpiSdo]
|
||||
set_output_delay -clock PlClk -min $PlSdoOutputDelayMin [get_ports lPlSpiSdo]
|
||||
|
||||
|
||||
|
||||
## Passthrough Constraints ##############################################################
|
||||
# - LMK SYNC
|
||||
# - PlClk/PsClk passthrough
|
||||
# - SDI passthrough for both
|
||||
# - SDO return mux passthrough for both
|
||||
# - Cs_n passthrough for both
|
||||
|
||||
# LMK Sync Passthrough: constrain min and max delays for output
|
||||
set_max_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 17
|
||||
set_min_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 2
|
||||
|
||||
# SPI Passthroughs: constrain min and max delays for outputs and inputs.
|
||||
# Since the SDI ports have input delays pre-defined above, we have to remove those from
|
||||
# the delay analysis here by adding the input delay to the constraint.
|
||||
# Similarly, for the SDO pins add the output delay to the constraint.
|
||||
set SpiMaxDelay 25
|
||||
set SpiMinDelay 5
|
||||
|
||||
# PS
|
||||
set_max_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMax + $SpiMaxDelay]
|
||||
set_min_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMin + $SpiMinDelay]
|
||||
set_max_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMinDelay
|
||||
set_max_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMinDelay
|
||||
set_max_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMaxDelay + $PsSdoOutputDelayMax]
|
||||
set_min_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMinDelay + $PsSdoOutputDelayMin]
|
||||
|
||||
# PL
|
||||
set_max_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMax + $SpiMaxDelay]
|
||||
set_min_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMin + $SpiMinDelay]
|
||||
set_max_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMinDelay
|
||||
set_max_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMaxDelay
|
||||
set_min_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMinDelay
|
||||
set_max_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMaxDelay + $PlSdoOutputDelayMax]
|
||||
set_min_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMinDelay + $PlSdoOutputDelayMin]
|
||||
|
||||
|
||||
|
||||
## Async Inputs #########################################################################
|
||||
# aLmkStatus2 aRxLoLockDetect aTxLoLockDetect
|
||||
set_false_path -from [get_ports {aRxLoLockDetect}]
|
||||
set_false_path -from [get_ports {aTxLoLockDetect}]
|
||||
|
||||
|
||||
|
||||
## Async Outputs ########################################################################
|
||||
# aMkReset_n aVcxoCtrl
|
||||
set_false_path -to [get_ports {aMkReset_n}]
|
||||
set_false_path -to [get_ports {aVcxoCtrl}]
|
||||
|
||||
|
||||
|
||||
## Sync Front End Outputs ###############################################################
|
||||
# All we need to do here is constrain for maximum path delay from the aAtr(Rx|Tx)(1|2)
|
||||
# control bits toggling to the outputs for aCh1* and aCh2* toggling. Just in case the
|
||||
# user attempts to write the ATR while it's in use, we also constrain from the flops
|
||||
# to the pins... which covers all paths... so just to -to option is needed.
|
||||
set_max_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 40
|
||||
set_min_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 5
|
||||
|
||||
# We don't care about the LED timing whatsoever. Let's not have them clogging up our
|
||||
# precious timing paths.
|
||||
set_false_path -to [get_ports {aCh*Led*}]
|
||||
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
|
||||
# Date created = 14:51:27 February 24, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "16.1"
|
||||
DATE = "14:51:27 February 24, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "TopCpld"
|
||||
@@ -0,0 +1,313 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
|
||||
# Date created = 14:51:27 February 24, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# TopCpld_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX V"
|
||||
set_global_assignment -name DEVICE 5M570ZF256I5
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:51:27 FEBRUARY 24, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name SDC_FILE Timing.sdc
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name GENERATE_SVF_FILE ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
|
||||
|
||||
set_location_assignment PIN_C3 -to aCh2RxSw4[0]
|
||||
set_location_assignment PIN_C2 -to aCh2TxPaEn
|
||||
set_location_assignment PIN_D3 -to aCh2RxSw6[0]
|
||||
set_location_assignment PIN_D1 -to aCh2RxSw4[1]
|
||||
set_location_assignment PIN_D2 -to aCh2TxSw3
|
||||
set_location_assignment PIN_E1 -to aCh2RxSw4[2]
|
||||
set_location_assignment PIN_E4 -to aCh2RxSw7[1]
|
||||
set_location_assignment PIN_F2 -to aCh2RxSw6[1]
|
||||
set_location_assignment PIN_E3 -to aCh2RxSw7[0]
|
||||
set_location_assignment PIN_F1 -to aCh2RxSw5[0]
|
||||
set_location_assignment PIN_E2 -to aCh2RxSw5[1]
|
||||
set_location_assignment PIN_G2 -to aCh2RxSw5[3]
|
||||
set_location_assignment PIN_F3 -to aCh2TxSw4[0]
|
||||
set_location_assignment PIN_G1 -to aCh2RxSw6[2]
|
||||
set_location_assignment PIN_G3 -to aCh2TxSw4[1]
|
||||
set_location_assignment PIN_H2 -to aCh2TxAmpEn
|
||||
set_location_assignment PIN_H1 -to aCh2RxSw5[2]
|
||||
set_location_assignment PIN_J1 -to aCh2TxMixerEn
|
||||
set_location_assignment PIN_H5 -to aLoSpiSync
|
||||
set_location_assignment PIN_J2 -to aCh2RxMixerEn
|
||||
#set_location_assignment PIN_L3 -to aLmkSpiSdio
|
||||
set_location_assignment PIN_K1 -to aCh2TxSw5[1]
|
||||
set_location_assignment PIN_K2 -to aCh2TxSw5[0]
|
||||
set_location_assignment PIN_M2 -to aLmkSpiSdio
|
||||
set_location_assignment PIN_L1 -to aCh2RxSw8[0]
|
||||
set_location_assignment PIN_M3 -to lPlSpiSdi
|
||||
set_location_assignment PIN_L2 -to aCh2RxSw8[1]
|
||||
set_location_assignment PIN_M1 -to aCh2RxAmpEn
|
||||
set_location_assignment PIN_N2 -to aLmkSpiSck
|
||||
set_location_assignment PIN_N1 -to aLmkSpiCs_n
|
||||
set_location_assignment PIN_N3 -to PlSpiSck
|
||||
# set_location_assignment PIN_P2 -to lPlSpiLe
|
||||
set_location_assignment PIN_R3 -to aMkReset_n
|
||||
set_location_assignment PIN_R1 -to lPlSpiLe
|
||||
set_location_assignment PIN_T2 -to aLmkSync
|
||||
set_location_assignment PIN_R4 -to aVcxoCtrl
|
||||
set_location_assignment PIN_T4 -to aDacDin
|
||||
set_location_assignment PIN_T5 -to aDacSync_n
|
||||
set_location_assignment PIN_R6 -to aPlSpiAddr[2]
|
||||
set_location_assignment PIN_R5 -to aDacSck
|
||||
set_location_assignment PIN_T6 -to aPlSpiAddr[1]
|
||||
set_location_assignment PIN_R7 -to aLmkClkinSel[0]
|
||||
set_location_assignment PIN_T7 -to lPlSpiSdo
|
||||
set_location_assignment PIN_P8 -to sPsSpiLe
|
||||
set_location_assignment PIN_R8 -to aPsSpiAddr[1]
|
||||
set_location_assignment PIN_P9 -to aPlSpiAddr[0]
|
||||
set_location_assignment PIN_T8 -to PsSpiSck
|
||||
set_location_assignment PIN_T9 -to aPsSpiAddr[0]
|
||||
set_location_assignment PIN_R9 -to sPsSpiSdi
|
||||
set_location_assignment PIN_P10 -to aAtrRx1
|
||||
set_location_assignment PIN_T10 -to sPsSpiSdo
|
||||
set_location_assignment PIN_P11 -to aAtrTx2
|
||||
set_location_assignment PIN_R10 -to aRxLoLockDetect
|
||||
set_location_assignment PIN_R12 -to aRxLoSck
|
||||
set_location_assignment PIN_T11 -to aTxLoLockDetect
|
||||
set_location_assignment PIN_P12 -to aAtrRx2
|
||||
set_location_assignment PIN_R11 -to aRxLoDin
|
||||
set_location_assignment PIN_T12 -to aRxLoCs_n
|
||||
set_location_assignment PIN_R13 -to aTxLoDin
|
||||
set_location_assignment PIN_T13 -to aRxLoMuxOut
|
||||
set_location_assignment PIN_P13 -to aAtrTx1
|
||||
set_location_assignment PIN_T15 -to aTxLoSck
|
||||
set_location_assignment PIN_R14 -to aTxLoCs_n
|
||||
set_location_assignment PIN_R16 -to aTxLoMuxOut
|
||||
set_location_assignment PIN_P14 -to aMkTx1En
|
||||
set_location_assignment PIN_N15 -to aMkRx2En
|
||||
set_location_assignment PIN_P15 -to aMkRx1En
|
||||
set_location_assignment PIN_N16 -to aMkTx2En
|
||||
set_location_assignment PIN_K15 -to aCh1TxSw5[1]
|
||||
set_location_assignment PIN_L14 -to aCh1RxMixerEn
|
||||
set_location_assignment PIN_K16 -to aCh1TxMixerEn
|
||||
set_location_assignment PIN_K14 -to aCh1RxSw8[0]
|
||||
set_location_assignment PIN_J15 -to aCh1TxAmpEn
|
||||
set_location_assignment PIN_J14 -to aCh1RxSw8[1]
|
||||
set_location_assignment PIN_J16 -to aCh1TxSw5[0]
|
||||
set_location_assignment PIN_H14 -to aCh1RxAmpEn
|
||||
set_location_assignment PIN_H16 -to aCh1TxSw4[0]
|
||||
set_location_assignment PIN_G14 -to aCh1TxSw4[1]
|
||||
set_location_assignment PIN_H15 -to aCh1RxSw5[1]
|
||||
set_location_assignment PIN_F14 -to aCh1RxSw7[1]
|
||||
set_location_assignment PIN_G16 -to aCh1RxSw5[0]
|
||||
set_location_assignment PIN_G15 -to aCh1RxSw4[0]
|
||||
set_location_assignment PIN_E14 -to aCh1RxSw6[1]
|
||||
set_location_assignment PIN_F16 -to aCh1RxSw2[1]
|
||||
set_location_assignment PIN_E13 -to aCh1RxSw7[0]
|
||||
set_location_assignment PIN_F15 -to aCh1RxSw2[0]
|
||||
set_location_assignment PIN_D14 -to aCh1RxSw6[2]
|
||||
set_location_assignment PIN_E16 -to aCh1RxSw6[0]
|
||||
set_location_assignment PIN_E15 -to aCh1TxSw3
|
||||
set_location_assignment PIN_C15 -to aCh1RxSw5[2]
|
||||
set_location_assignment PIN_D16 -to aCh1TxPaEn
|
||||
set_location_assignment PIN_C14 -to aCh1RxSw4[1]
|
||||
set_location_assignment PIN_D15 -to aCh1RxSw5[3]
|
||||
set_location_assignment PIN_B14 -to aCh1TxSw2[3]
|
||||
set_location_assignment PIN_B16 -to aCh1RxLna2En
|
||||
set_location_assignment PIN_C13 -to aCh1RxSw4[2]
|
||||
set_location_assignment PIN_A15 -to aCh1TxSw2[2]
|
||||
set_location_assignment PIN_B13 -to aCh1TxSw2[1]
|
||||
set_location_assignment PIN_A13 -to aCh1TxSw2[0]
|
||||
set_location_assignment PIN_C12 -to aCh1RxSw1[0]
|
||||
set_location_assignment PIN_B12 -to aCh1TxSw1[0]
|
||||
set_location_assignment PIN_D12 -to aCh1RxSw1[1]
|
||||
set_location_assignment PIN_A12 -to aCh1TxSw1[1]
|
||||
set_location_assignment PIN_C11 -to aCh1LedTx
|
||||
set_location_assignment PIN_B11 -to aCh1RxLna1En
|
||||
set_location_assignment PIN_D11 -to aCh2RxSw1[1]
|
||||
set_location_assignment PIN_A11 -to aCh1RxSw3[2]
|
||||
set_location_assignment PIN_C10 -to aCh1LedRx
|
||||
set_location_assignment PIN_B10 -to aCh1RxSw3[1]
|
||||
set_location_assignment PIN_C9 -to aCh1LedRx2
|
||||
set_location_assignment PIN_A10 -to aCh1RxSw3[0]
|
||||
set_location_assignment PIN_C8 -to aCh2LedRx2
|
||||
set_location_assignment PIN_B9 -to aCh1SwTrx[1]
|
||||
set_location_assignment PIN_A9 -to aCh1SwTrx[0]
|
||||
set_location_assignment PIN_A8 -to aCh2SwTrx[0]
|
||||
set_location_assignment PIN_C7 -to aCh2RxSw3[0]
|
||||
set_location_assignment PIN_B8 -to aCh2SwTrx[1]
|
||||
set_location_assignment PIN_C6 -to aCh2LedRx
|
||||
set_location_assignment PIN_A7 -to aCh2RxSw3[1]
|
||||
set_location_assignment PIN_B5 -to aCh2TxSw1[0]
|
||||
set_location_assignment PIN_C5 -to aCh2RxSw1[0]
|
||||
set_location_assignment PIN_A6 -to aCh2TxSw1[1]
|
||||
set_location_assignment PIN_D5 -to aCh2LedTx
|
||||
set_location_assignment PIN_B6 -to aCh2RxSw3[2]
|
||||
set_location_assignment PIN_B4 -to aCh2RxLna2En
|
||||
set_location_assignment PIN_A5 -to aCh2RxLna1En
|
||||
set_location_assignment PIN_C4 -to aCh2RxSw2[0]
|
||||
set_location_assignment PIN_A4 -to aCh2TxSw2[1]
|
||||
set_location_assignment PIN_D4 -to aCh2RxSw2[1]
|
||||
set_location_assignment PIN_A2 -to aCh2TxSw2[3]
|
||||
set_location_assignment PIN_B3 -to aCh2TxSw2[0]
|
||||
set_location_assignment PIN_B1 -to aCh2TxSw2[2]
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
|
||||
set_global_assignment -name GENERATE_JAM_FILE ON
|
||||
set_global_assignment -name GENERATE_JBC_FILE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxPaEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSdio
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiCs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkReset_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSync
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aVcxoCtrl
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacDin
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSync_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to lPlSpiSdo
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sPsSpiSdo
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoDin
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoCs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoDin
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoSck
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoCs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxMixerEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxAmpEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxPaEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedTx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedTx
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna2En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna1En
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[2]
|
||||
set_global_assignment -name SEED 11
|
||||
set_global_assignment -name VHDL_FILE PkgMgCpld.vhd
|
||||
set_global_assignment -name VHDL_FILE PkgSetup.vhd
|
||||
set_global_assignment -name VHDL_FILE TopCpld.vhd
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY TopCpld
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,156 @@
|
||||
#
|
||||
# Copyright 2017 Ettus Research, A National Instruments Company
|
||||
# SPDX-License-Identifier: LGPL-3.0
|
||||
#
|
||||
# Daughterboard Pin Definitions for the N310.
|
||||
#
|
||||
|
||||
## TDC : ################################################################################
|
||||
## Bank 10, 2.5V (DB A)
|
||||
#########################################################################################
|
||||
|
||||
set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}]
|
||||
set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}]
|
||||
set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}]
|
||||
set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}]
|
||||
set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}]
|
||||
|
||||
## USRP IO A : ##########################################################################
|
||||
## Banks 10/33
|
||||
#########################################################################################
|
||||
|
||||
## HP GPIO, Bank 33, 1.8V
|
||||
|
||||
set_property PACKAGE_PIN G1 [get_ports {DBA_CPLD_PS_SPI_LE}]
|
||||
set_property PACKAGE_PIN H2 [get_ports {DBA_CPLD_PS_SPI_SCLK}]
|
||||
set_property PACKAGE_PIN D1 [get_ports {DBA_CH1_TX_DSA_DATA[5]}]
|
||||
# set_property PACKAGE_PIN E1 [get_ports {nc}]
|
||||
set_property PACKAGE_PIN H1 [get_ports {DBA_CPLD_PS_SPI_ADDR[0]}]
|
||||
set_property PACKAGE_PIN J1 [get_ports {DBA_CPLD_PS_SPI_ADDR[1]}]
|
||||
set_property PACKAGE_PIN A5 [get_ports {DBA_CH1_TX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN A4 [get_ports {DBA_CH1_TX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN F5 [get_ports {DBA_CPLD_PS_SPI_SDO}]
|
||||
set_property PACKAGE_PIN E5 [get_ports {DBA_CPLD_PS_SPI_SDI}]
|
||||
set_property PACKAGE_PIN E3 [get_ports {DBA_CH1_RX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN E2 [get_ports {DBA_CH1_RX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN A3 [get_ports {DBA_CH1_TX_DSA_DATA[2]}]
|
||||
set_property PACKAGE_PIN A2 [get_ports {DBA_CH1_TX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN K1 [get_ports {DBA_ATR_RX_1}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {DBA_ATR_TX_2}]
|
||||
set_property PACKAGE_PIN C4 [get_ports {DBA_CH1_TX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN C3 [get_ports {DBA_CH1_RX_DSA_DATA[5]}]
|
||||
set_property PACKAGE_PIN F4 [get_ports {DBA_ATR_TX_1}]
|
||||
set_property PACKAGE_PIN F3 [get_ports {DBA_ATR_RX_2}]
|
||||
# set_property PACKAGE_PIN B1 [get_ports {nc}]
|
||||
set_property PACKAGE_PIN B2 [get_ports {DBA_CH1_RX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN C1 [get_ports {DBA_CH1_RX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN C2 [get_ports {DBA_CH1_RX_DSA_DATA[2]}]
|
||||
|
||||
## HR GPIO, Bank 10, 2.5V
|
||||
|
||||
set_property PACKAGE_PIN AG12 [get_ports {DBA_MYK_SYNC_IN_n}]
|
||||
set_property PACKAGE_PIN AH12 [get_ports {DBA_CPLD_PL_SPI_ADDR[0]}]
|
||||
set_property PACKAGE_PIN AJ13 [get_ports {DBA_MYK_SPI_SDO}]
|
||||
set_property PACKAGE_PIN AJ14 [get_ports {DBA_MYK_SPI_SDIO}]
|
||||
set_property PACKAGE_PIN AG15 [get_ports {DBA_CPLD_PL_SPI_ADDR[1]}]
|
||||
set_property PACKAGE_PIN AF15 [get_ports {DBA_CH2_TX_DSA_DATA[5]}]
|
||||
set_property PACKAGE_PIN AH13 [get_ports {DBA_CPLD_JTAG_TDI}]
|
||||
set_property PACKAGE_PIN AH14 [get_ports {DBA_CPLD_JTAG_TDO}]
|
||||
set_property PACKAGE_PIN AK15 [get_ports {DBA_MYK_GPIO_1}]
|
||||
set_property PACKAGE_PIN AJ15 [get_ports {DBA_MYK_GPIO_4}]
|
||||
set_property PACKAGE_PIN AH16 [get_ports {DBA_CH2_TX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN AH17 [get_ports {DBA_CH2_TX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN AE12 [get_ports {DBA_MYK_SYNC_OUT_n}]
|
||||
set_property PACKAGE_PIN AF12 [get_ports {DBA_CPLD_PL_SPI_SDO}]
|
||||
set_property PACKAGE_PIN AK12 [get_ports {DBA_MYK_GPIO_13}]
|
||||
set_property PACKAGE_PIN AK13 [get_ports {DBA_MYK_GPIO_0}]
|
||||
set_property PACKAGE_PIN AK16 [get_ports {DBA_MYK_INTRQ}]
|
||||
set_property PACKAGE_PIN AJ16 [get_ports {DBA_CH2_TX_DSA_DATA[2]}]
|
||||
set_property PACKAGE_PIN AH18 [get_ports {DBA_CH2_TX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN AJ18 [get_ports {DBA_CH2_TX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN AF14 [get_ports {DBA_FPGA_CLK_P}]
|
||||
set_property PACKAGE_PIN AG14 [get_ports {DBA_FPGA_CLK_N}]
|
||||
set_property PACKAGE_PIN AG17 [get_ports {DBA_FPGA_SYSREF_P}]
|
||||
set_property PACKAGE_PIN AG16 [get_ports {DBA_FPGA_SYSREF_N}]
|
||||
set_property PACKAGE_PIN AD15 [get_ports {DBA_CH2_RX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN AD16 [get_ports {DBA_CH2_RX_DSA_DATA[5]}]
|
||||
set_property PACKAGE_PIN AE13 [get_ports {DBA_CPLD_JTAG_TMS}]
|
||||
set_property PACKAGE_PIN AF13 [get_ports {DBA_CPLD_JTAG_TCK}]
|
||||
set_property PACKAGE_PIN AE15 [get_ports {DBA_MYK_GPIO_15}]
|
||||
set_property PACKAGE_PIN AE16 [get_ports {DBA_MYK_SPI_CS_n}]
|
||||
set_property PACKAGE_PIN AF17 [get_ports {DBA_CH2_RX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN AF18 [get_ports {DBA_CH2_RX_DSA_DATA[2]}]
|
||||
set_property PACKAGE_PIN AC16 [get_ports {DBA_CPLD_PL_SPI_LE}]
|
||||
set_property PACKAGE_PIN AC17 [get_ports {DBA_CPLD_PL_SPI_SDI}]
|
||||
set_property PACKAGE_PIN AD13 [get_ports {DBA_MYK_GPIO_12}]
|
||||
set_property PACKAGE_PIN AD14 [get_ports {DBA_MYK_GPIO_14}]
|
||||
set_property PACKAGE_PIN AE17 [get_ports {DBA_MYK_SPI_SCLK}]
|
||||
set_property PACKAGE_PIN AE18 [get_ports {DBA_MYK_GPIO_3}]
|
||||
set_property PACKAGE_PIN AB12 [get_ports {DBA_CH2_RX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN AC12 [get_ports {DBA_CH2_RX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN AC13 [get_ports {DBA_CPLD_PL_SPI_ADDR[2]}]
|
||||
set_property PACKAGE_PIN AC14 [get_ports {DBA_CPLD_PL_SPI_SCLK}]
|
||||
|
||||
# set_property PACKAGE_PIN AB25 [get_ports {DBA_SWITCHER_CLOCK}]
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports {DBA_SWITCHER_CLOCK}]
|
||||
# set_property DRIVE 4 [get_ports {DBA_SWITCHER_CLOCK}]
|
||||
# set_property SLEW SLOW [get_ports {DBA_SWITCHER_CLOCK}]
|
||||
|
||||
# During SI measurements with default drive strength, many of the FPGA-driven lines to
|
||||
# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs
|
||||
# we are decreasing the drive strength to the minimum value (4mA) and explicitly
|
||||
# declaring the (default) slew rate as SLOW.
|
||||
|
||||
set UsrpIoAHpPinsSe [get_ports {DBA_CPLD_PS_* \
|
||||
DBA_CH1_* \
|
||||
DBA_ATR*}]
|
||||
set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe
|
||||
set_property DRIVE 4 $UsrpIoAHpPinsSe
|
||||
set_property SLEW SLOW $UsrpIoAHpPinsSe
|
||||
|
||||
set UsrpIoAHrPinsSe [get_ports {DBA_MYK_SPI_* \
|
||||
DBA_MYK_INTRQ \
|
||||
DBA_MYK_SYNC* \
|
||||
DBA_MYK_GPIO* \
|
||||
DBA_CPLD_PL_* \
|
||||
DBA_CPLD_JTAG_* \
|
||||
DBA_CH2*}]
|
||||
set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSe
|
||||
set_property DRIVE 4 $UsrpIoAHrPinsSe
|
||||
set_property SLEW SLOW $UsrpIoAHrPinsSe
|
||||
|
||||
set UsrpIoAHrPinsDiff [get_ports {DBA_FPGA_CLK_* \
|
||||
DBA_FPGA_SYSREF_*}]
|
||||
set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff
|
||||
set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff
|
||||
|
||||
# Do not allow the DSA lines to float... give them a weak pull if undriven.
|
||||
set_property PULLUP TRUE [get_ports {DBA_CH*_*X_DSA_DATA[*]}]
|
||||
|
||||
|
||||
### MGTs, Bank 112
|
||||
|
||||
set_property PACKAGE_PIN N8 [get_ports {USRPIO_A_MGTCLK_P}]
|
||||
set_property PACKAGE_PIN N7 [get_ports {USRPIO_A_MGTCLK_N}]
|
||||
|
||||
# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado
|
||||
# places the transceivers in the correct places. The mixup in lanes is accounted for
|
||||
# in the Mykonos lane crossbar settings.
|
||||
set_property PACKAGE_PIN V6 [get_ports {USRPIO_A_RX_P[0]}]
|
||||
set_property PACKAGE_PIN V5 [get_ports {USRPIO_A_RX_N[0]}]
|
||||
set_property PACKAGE_PIN U4 [get_ports {USRPIO_A_RX_P[1]}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {USRPIO_A_RX_N[1]}]
|
||||
set_property PACKAGE_PIN T6 [get_ports {USRPIO_A_RX_P[2]}]
|
||||
set_property PACKAGE_PIN T5 [get_ports {USRPIO_A_RX_N[2]}]
|
||||
set_property PACKAGE_PIN P6 [get_ports {USRPIO_A_RX_P[3]}]
|
||||
set_property PACKAGE_PIN P5 [get_ports {USRPIO_A_RX_N[3]}]
|
||||
|
||||
set_property PACKAGE_PIN T2 [get_ports {USRPIO_A_TX_P[0]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {USRPIO_A_TX_N[0]}]
|
||||
set_property PACKAGE_PIN R4 [get_ports {USRPIO_A_TX_P[1]}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {USRPIO_A_TX_N[1]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {USRPIO_A_TX_P[2]}]
|
||||
set_property PACKAGE_PIN P1 [get_ports {USRPIO_A_TX_N[2]}]
|
||||
set_property PACKAGE_PIN N4 [get_ports {USRPIO_A_TX_P[3]}]
|
||||
set_property PACKAGE_PIN N3 [get_ports {USRPIO_A_TX_N[3]}]
|
||||
@@ -0,0 +1,156 @@
|
||||
#
|
||||
# Copyright 2017 Ettus Research, A National Instruments Company
|
||||
# SPDX-License-Identifier: LGPL-3.0
|
||||
#
|
||||
# Daughterboard Pin Definitions for the N310.
|
||||
#
|
||||
|
||||
## TDC : ################################################################################
|
||||
## Bank 11, 2.5V (DB B)
|
||||
#########################################################################################
|
||||
|
||||
set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}]
|
||||
set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}]
|
||||
set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}]
|
||||
set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}]
|
||||
set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}]
|
||||
|
||||
### USRP IO B : #########################################################################
|
||||
## Bank 11/33
|
||||
#########################################################################################
|
||||
|
||||
## HP GPIO, Bank 33, 1.8V
|
||||
|
||||
set_property PACKAGE_PIN J4 [get_ports {DBB_CPLD_PS_SPI_LE}]
|
||||
set_property PACKAGE_PIN J3 [get_ports {DBB_CPLD_PS_SPI_SCLK}]
|
||||
set_property PACKAGE_PIN D4 [get_ports {DBB_CH1_TX_DSA_DATA[5]}]
|
||||
# set_property PACKAGE_PIN D3 [get_ports {nc}]
|
||||
set_property PACKAGE_PIN K2 [get_ports {DBB_CPLD_PS_SPI_ADDR[0]}]
|
||||
set_property PACKAGE_PIN K3 [get_ports {DBB_CPLD_PS_SPI_ADDR[1]}]
|
||||
set_property PACKAGE_PIN B5 [get_ports {DBB_CH1_TX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN B4 [get_ports {DBB_CH1_TX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN G5 [get_ports {DBB_CPLD_PS_SPI_SDO}]
|
||||
set_property PACKAGE_PIN G4 [get_ports {DBB_CPLD_PS_SPI_SDI}]
|
||||
set_property PACKAGE_PIN J5 [get_ports {DBB_CH1_RX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN K5 [get_ports {DBB_CH1_RX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN D5 [get_ports {DBB_CH1_TX_DSA_DATA[2]}]
|
||||
set_property PACKAGE_PIN E6 [get_ports {DBB_CH1_TX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN L3 [get_ports {DBB_ATR_RX_1}]
|
||||
set_property PACKAGE_PIN L2 [get_ports {DBB_ATR_TX_2}]
|
||||
set_property PACKAGE_PIN G6 [get_ports {DBB_CH1_TX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN H6 [get_ports {DBB_CH1_RX_DSA_DATA[5]}]
|
||||
set_property PACKAGE_PIN H4 [get_ports {DBB_ATR_TX_1}]
|
||||
set_property PACKAGE_PIN H3 [get_ports {DBB_ATR_RX_2}]
|
||||
# set_property PACKAGE_PIN F2 [get_ports {nc}]
|
||||
set_property PACKAGE_PIN G2 [get_ports {DBB_CH1_RX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN J6 [get_ports {DBB_CH1_RX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN K6 [get_ports {DBB_CH1_RX_DSA_DATA[2]}]
|
||||
|
||||
## HR GPIO, Bank 10, 2.5V
|
||||
|
||||
set_property PACKAGE_PIN AK17 [get_ports {DBB_MYK_SYNC_IN_n}]
|
||||
set_property PACKAGE_PIN AK18 [get_ports {DBB_CPLD_PL_SPI_ADDR[0]}]
|
||||
set_property PACKAGE_PIN AK21 [get_ports {DBB_MYK_SPI_SDO}]
|
||||
set_property PACKAGE_PIN AJ21 [get_ports {DBB_MYK_SPI_SDIO}]
|
||||
set_property PACKAGE_PIN AF19 [get_ports {DBB_CPLD_PL_SPI_ADDR[1]}]
|
||||
set_property PACKAGE_PIN AG19 [get_ports {DBB_CH2_TX_DSA_DATA[5]}]
|
||||
set_property PACKAGE_PIN AH19 [get_ports {DBB_CPLD_JTAG_TDI}]
|
||||
set_property PACKAGE_PIN AJ19 [get_ports {DBB_CPLD_JTAG_TDO}]
|
||||
set_property PACKAGE_PIN AK22 [get_ports {DBB_MYK_GPIO_1}]
|
||||
set_property PACKAGE_PIN AK23 [get_ports {DBB_MYK_GPIO_4}]
|
||||
set_property PACKAGE_PIN AF20 [get_ports {DBB_CH2_TX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN AG20 [get_ports {DBB_CH2_TX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN AF23 [get_ports {DBB_MYK_SYNC_OUT_n}]
|
||||
set_property PACKAGE_PIN AF24 [get_ports {DBB_CPLD_PL_SPI_SDO}]
|
||||
set_property PACKAGE_PIN AK20 [get_ports {DBB_MYK_GPIO_13}]
|
||||
set_property PACKAGE_PIN AJ20 [get_ports {DBB_MYK_GPIO_0}]
|
||||
set_property PACKAGE_PIN AJ23 [get_ports {DBB_MYK_INTRQ}]
|
||||
set_property PACKAGE_PIN AJ24 [get_ports {DBB_CH2_TX_DSA_DATA[2]}]
|
||||
set_property PACKAGE_PIN AG24 [get_ports {DBB_CH2_TX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN AG25 [get_ports {DBB_CH2_TX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN AG21 [get_ports {DBB_FPGA_CLK_P}]
|
||||
set_property PACKAGE_PIN AH21 [get_ports {DBB_FPGA_CLK_N}]
|
||||
set_property PACKAGE_PIN AE22 [get_ports {DBB_FPGA_SYSREF_P}]
|
||||
set_property PACKAGE_PIN AF22 [get_ports {DBB_FPGA_SYSREF_N}]
|
||||
set_property PACKAGE_PIN AJ25 [get_ports {DBB_CH2_RX_DSA_DATA[3]}]
|
||||
set_property PACKAGE_PIN AK25 [get_ports {DBB_CH2_RX_DSA_DATA[5]}]
|
||||
set_property PACKAGE_PIN AB21 [get_ports {DBB_CPLD_JTAG_TMS}]
|
||||
set_property PACKAGE_PIN AB22 [get_ports {DBB_CPLD_JTAG_TCK}]
|
||||
set_property PACKAGE_PIN AD23 [get_ports {DBB_MYK_GPIO_15}]
|
||||
set_property PACKAGE_PIN AE23 [get_ports {DBB_MYK_SPI_CS_n}]
|
||||
set_property PACKAGE_PIN AB24 [get_ports {DBB_CH2_RX_DSA_DATA[1]}]
|
||||
set_property PACKAGE_PIN AA24 [get_ports {DBB_CH2_RX_DSA_DATA[2]}]
|
||||
set_property PACKAGE_PIN AG22 [get_ports {DBB_CPLD_PL_SPI_LE}]
|
||||
set_property PACKAGE_PIN AH22 [get_ports {DBB_CPLD_PL_SPI_SDI}]
|
||||
set_property PACKAGE_PIN AD21 [get_ports {DBB_MYK_GPIO_12}]
|
||||
set_property PACKAGE_PIN AE21 [get_ports {DBB_MYK_GPIO_14}]
|
||||
set_property PACKAGE_PIN AC22 [get_ports {DBB_MYK_SPI_SCLK}]
|
||||
set_property PACKAGE_PIN AC23 [get_ports {DBB_MYK_GPIO_3}]
|
||||
set_property PACKAGE_PIN AC24 [get_ports {DBB_CH2_RX_DSA_DATA[0]}]
|
||||
set_property PACKAGE_PIN AD24 [get_ports {DBB_CH2_RX_DSA_DATA[4]}]
|
||||
set_property PACKAGE_PIN AH23 [get_ports {DBB_CPLD_PL_SPI_ADDR[2]}]
|
||||
set_property PACKAGE_PIN AH24 [get_ports {DBB_CPLD_PL_SPI_SCLK}]
|
||||
|
||||
# set_property PACKAGE_PIN AA25 [get_ports DBB_SWITCHER_CLOCK]
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports DBB_SWITCHER_CLOCK]
|
||||
# set_property DRIVE 4 [get_ports DBB_SWITCHER_CLOCK]
|
||||
# set_property SLEW SLOW [get_ports DBB_SWITCHER_CLOCK]
|
||||
|
||||
# During SI measurements with default drive strength, many of the FPGA-driven lines to
|
||||
# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs
|
||||
# we are decreasing the drive strength to the minimum value (4mA) and explicitly
|
||||
# declaring the (default) slew rate as SLOW.
|
||||
|
||||
set UsrpIoBHpPinsSe [get_ports {DBB_CPLD_PS_* \
|
||||
DBB_CH1_* \
|
||||
DBB_ATR*}]
|
||||
set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe
|
||||
set_property DRIVE 4 $UsrpIoBHpPinsSe
|
||||
set_property SLEW SLOW $UsrpIoBHpPinsSe
|
||||
|
||||
set UsrpIoBHrPinsSe [get_ports {DBB_MYK_SPI_* \
|
||||
DBB_MYK_INTRQ \
|
||||
DBB_MYK_SYNC* \
|
||||
DBB_MYK_GPIO* \
|
||||
DBB_CPLD_PL_* \
|
||||
DBB_CPLD_JTAG_* \
|
||||
DBB_CH2*}]
|
||||
set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSe
|
||||
set_property DRIVE 4 $UsrpIoBHrPinsSe
|
||||
set_property SLEW SLOW $UsrpIoBHrPinsSe
|
||||
|
||||
set UsrpIoBHrPinsDiff [get_ports {DBB_FPGA_CLK_* \
|
||||
DBB_FPGA_SYSREF_*}]
|
||||
set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff
|
||||
set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff
|
||||
|
||||
# Do not allow the DSA lines to float... give them a weak pull if undriven.
|
||||
set_property PULLUP TRUE [get_ports {DBB_CH*_*X_DSA_DATA[*]}]
|
||||
|
||||
|
||||
### MGTs, Bank 112
|
||||
|
||||
set_property PACKAGE_PIN W8 [get_ports {USRPIO_B_MGTCLK_P}]
|
||||
set_property PACKAGE_PIN W7 [get_ports {USRPIO_B_MGTCLK_N}]
|
||||
|
||||
# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado
|
||||
# places the transceivers in the correct places. The mixup in lanes is accounted for
|
||||
# in the Mykonos lane crossbar settings.
|
||||
set_property PACKAGE_PIN AC4 [get_ports {USRPIO_B_RX_P[0]}]
|
||||
set_property PACKAGE_PIN AC3 [get_ports {USRPIO_B_RX_N[0]}]
|
||||
set_property PACKAGE_PIN AB6 [get_ports {USRPIO_B_RX_P[1]}]
|
||||
set_property PACKAGE_PIN AB5 [get_ports {USRPIO_B_RX_N[1]}]
|
||||
set_property PACKAGE_PIN Y6 [get_ports {USRPIO_B_RX_P[2]}]
|
||||
set_property PACKAGE_PIN Y5 [get_ports {USRPIO_B_RX_N[2]}]
|
||||
set_property PACKAGE_PIN AA4 [get_ports {USRPIO_B_RX_P[3]}]
|
||||
set_property PACKAGE_PIN AA3 [get_ports {USRPIO_B_RX_N[3]}]
|
||||
|
||||
set_property PACKAGE_PIN AB2 [get_ports {USRPIO_B_TX_P[0]}]
|
||||
set_property PACKAGE_PIN AB1 [get_ports {USRPIO_B_TX_N[0]}]
|
||||
set_property PACKAGE_PIN Y2 [get_ports {USRPIO_B_TX_P[1]}]
|
||||
set_property PACKAGE_PIN Y1 [get_ports {USRPIO_B_TX_N[1]}]
|
||||
set_property PACKAGE_PIN W4 [get_ports {USRPIO_B_TX_P[2]}]
|
||||
set_property PACKAGE_PIN W3 [get_ports {USRPIO_B_TX_N[2]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {USRPIO_B_TX_P[3]}]
|
||||
set_property PACKAGE_PIN V1 [get_ports {USRPIO_B_TX_N[3]}]
|
||||
@@ -0,0 +1,345 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: ClockingRegs.vhd
|
||||
-- Author: Daniel Jepson
|
||||
-- Original Project: N310
|
||||
-- Date: 17 March 2016
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2016-2018 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Register access to the control/status bits and interfaces for the
|
||||
-- RadioClocking module.
|
||||
--
|
||||
-- XML register definition is included below the module.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library work;
|
||||
use work.PkgClockingRegMap.all;
|
||||
use work.PkgRegs.all;
|
||||
|
||||
|
||||
entity ClockingRegs is
|
||||
port(
|
||||
-- Async reset. Can be tied low if desired.
|
||||
aReset : in boolean;
|
||||
-- Sync reset... used in the same places as the async one.
|
||||
bReset : in boolean;
|
||||
-- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited
|
||||
-- to 200 MHz!
|
||||
BusClk : in std_logic;
|
||||
|
||||
bRegPortOut : out RegPortOut_t;
|
||||
bRegPortIn : in RegPortIn_t;
|
||||
|
||||
-- Phase shift interface to the RadioClkMmcm.
|
||||
-- There is a reset crossing here between the MMCM reset and aReset. The outgoing
|
||||
-- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only
|
||||
-- signal and (b) this interface should only be used when the MMCM is not in reset
|
||||
-- (SW waits for the MMCM to be out of reset and locked before using this interface).
|
||||
-- The only input signal, pPsDone, is double-synced in this file before being used.
|
||||
-- This is OK (even though it is a strobe signal) because there is only a reset
|
||||
-- crossing and not a clock domain crossing.
|
||||
pPsInc : out std_logic;
|
||||
pPsEn : out std_logic;
|
||||
pPsDone : in std_logic;
|
||||
|
||||
-- PsClk is driven directly by BusClk, so p = b in the logic below!
|
||||
PsClk : out std_logic;
|
||||
|
||||
-- Sync reset strobes from the register bus to the RadioClkMmcm.
|
||||
bRadioClkMmcmReset : out std_logic;
|
||||
-- Status of RadioClk MMCM lock to register bus.
|
||||
aRadioClksValid : in std_logic;
|
||||
|
||||
bRadioClk1xEnabled : out std_logic;
|
||||
bRadioClk2xEnabled : out std_logic;
|
||||
bRadioClk3xEnabled : out std_logic;
|
||||
|
||||
bJesdRefClkPresent : in std_logic
|
||||
);
|
||||
end ClockingRegs;
|
||||
|
||||
|
||||
architecture RTL of ClockingRegs is
|
||||
|
||||
--vhook_sigstart
|
||||
--vhook_sigend
|
||||
|
||||
signal bRadioClkMmcmResetInt : std_logic := '1';
|
||||
|
||||
signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero;
|
||||
|
||||
signal bPsDone,
|
||||
bPsEn,
|
||||
bPsInc,
|
||||
pPsDoneDs_ms,
|
||||
pPsDoneDs : std_logic := '0';
|
||||
|
||||
signal bRadioClk1xEnabledInt,
|
||||
bRadioClk2xEnabledInt,
|
||||
bRadioClk3xEnabledInt,
|
||||
bRadioClksValid_ms,
|
||||
bRadioClksValid : std_logic := '0';
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of bRadioClksValid_ms : signal is "true";
|
||||
attribute ASYNC_REG of bRadioClksValid : signal is "true";
|
||||
attribute ASYNC_REG of pPsDoneDs_ms : signal is "true";
|
||||
attribute ASYNC_REG of pPsDoneDs : signal is "true";
|
||||
|
||||
begin
|
||||
|
||||
-- Locals to outputs.
|
||||
PsClk <= BusClk;
|
||||
pPsInc <= bPsInc;
|
||||
pPsEn <= bPsEn;
|
||||
|
||||
bRadioClkMmcmReset <= bRadioClkMmcmResetInt;
|
||||
|
||||
bRadioClk1xEnabled <= bRadioClk1xEnabledInt;
|
||||
bRadioClk2xEnabled <= bRadioClk2xEnabledInt;
|
||||
bRadioClk3xEnabled <= bRadioClk3xEnabledInt;
|
||||
|
||||
|
||||
-- Write Registers : ------------------------------------------------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
WriteRegisters: process(aReset, BusClk)
|
||||
begin
|
||||
if aReset then
|
||||
bRadioClkMmcmResetInt <= '1';
|
||||
bPsInc <= '0';
|
||||
bPsEn <= '0';
|
||||
bRadioClk1xEnabledInt <= '0';
|
||||
bRadioClk2xEnabledInt <= '0';
|
||||
bRadioClk3xEnabledInt <= '0';
|
||||
elsif rising_edge(BusClk) then
|
||||
|
||||
if bReset then
|
||||
bRadioClkMmcmResetInt <= '1';
|
||||
bPsInc <= '0';
|
||||
bPsEn <= '0';
|
||||
bRadioClk1xEnabledInt <= '0';
|
||||
bRadioClk2xEnabledInt <= '0';
|
||||
bRadioClk3xEnabledInt <= '0';
|
||||
else
|
||||
-- Clear strobe
|
||||
bPsEn <= '0';
|
||||
|
||||
if RegWrite(kPhaseShiftControl, bRegPortIn) then
|
||||
if bRegPortIn.Data(kPsInc) = '1' then
|
||||
bPsInc <= '1';
|
||||
bPsEn <= '1';
|
||||
elsif bRegPortIn.Data(kPsDec) = '1' then
|
||||
bPsInc <= '0';
|
||||
bPsEn <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if RegWrite(kRadioClkMmcm, bRegPortIn) then
|
||||
-- Set/Clear pair
|
||||
if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then
|
||||
bRadioClkMmcmResetInt <= '1';
|
||||
elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then
|
||||
bRadioClkMmcmResetInt <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if RegWrite(kRadioClkEnables, bRegPortIn) then
|
||||
bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled);
|
||||
bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled);
|
||||
bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process WriteRegisters;
|
||||
|
||||
|
||||
DoubleSyncs : process (aReset, BusClk)
|
||||
begin
|
||||
if aReset then
|
||||
bRadioClksValid_ms <= '0';
|
||||
bRadioClksValid <= '0';
|
||||
pPsDoneDs_ms <= '0';
|
||||
pPsDoneDs <= '0';
|
||||
elsif rising_edge(BusClk) then
|
||||
-- No sync reset on double-syncs (however there are default assignments above)!
|
||||
bRadioClksValid_ms <= aRadioClksValid;
|
||||
bRadioClksValid <= bRadioClksValid_ms;
|
||||
pPsDoneDs_ms <= pPsDone;
|
||||
pPsDoneDs <= pPsDoneDs_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Read Registers : -------------------------------------------------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
ReadRegisters: process(aReset, BusClk)
|
||||
begin
|
||||
if aReset then
|
||||
bRegPortOutLcl <= kRegPortOutZero;
|
||||
bPsDone <= '0';
|
||||
elsif rising_edge(BusClk) then
|
||||
|
||||
if bReset then
|
||||
bRegPortOutLcl <= kRegPortOutZero;
|
||||
bPsDone <= '0';
|
||||
else
|
||||
-- Deassert strobes
|
||||
bRegPortOutLcl.Data <= kRegPortDataZero;
|
||||
|
||||
-- All of these transactions only take one clock cycle, so we do not have to
|
||||
-- de-assert the Ready signal (ever).
|
||||
bRegPortOutLcl.Ready <= true;
|
||||
|
||||
-- Process the returned data from the phase shifter in the MMCM. Note that even
|
||||
-- though the prefixes are different (p and b), we drive the PsClk from the BusClk
|
||||
-- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone -
|
||||
-- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW
|
||||
-- that the shift operation is complete.
|
||||
--
|
||||
-- However, if pPsDone asserts at the same time that SW tries to read the register,
|
||||
-- we should accurately report that the operation is indeed complete and then NOT
|
||||
-- store the sticky (since it has already been read by SW). If a read does not come
|
||||
-- through at the same time pPsDone is asserted, then we store the done state as a
|
||||
-- sticky, bPsDone, which is only cleared by a read to this register.
|
||||
if RegRead(kPhaseShiftControl, bRegPortIn) then
|
||||
-- The phase shift is always enabled for the feedback clock in RadioClocking.vhd
|
||||
bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1';
|
||||
bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs;
|
||||
bPsDone <= '0';
|
||||
elsif pPsDoneDs = '1' then
|
||||
bPsDone <= '1';
|
||||
end if;
|
||||
|
||||
if RegRead(kRadioClkMmcm, bRegPortIn) then
|
||||
bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid;
|
||||
end if;
|
||||
|
||||
if RegRead(kRadioClkEnables, bRegPortIn) then
|
||||
bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt;
|
||||
bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt;
|
||||
bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt;
|
||||
end if;
|
||||
|
||||
if RegRead(kMgtRefClkStatus, bRegPortIn) then
|
||||
bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process ReadRegisters;
|
||||
|
||||
-- Local to output
|
||||
bRegPortOut <= bRegPortOutLcl;
|
||||
|
||||
|
||||
end RTL;
|
||||
|
||||
|
||||
--XmlParse xml_on
|
||||
--<regmap name="ClockingRegMap">
|
||||
-- <group name="ClockingRegs">
|
||||
--
|
||||
-- <register name="RadioClkMmcm" size="32" offset="0x20" attributes="Readable|Writable">
|
||||
-- <info>
|
||||
-- </info>
|
||||
-- <bitfield name="RadioClkMmcmLocked" range="4">
|
||||
-- <info>
|
||||
-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid
|
||||
-- when the MMCM reset is de-asserted. Read-only.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="RadioClkMmcmResetClear" range="1" attributes="Strobe">
|
||||
-- <info>
|
||||
-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the
|
||||
-- reset to the MMCM. Default is reset asserted. Write-only.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="RadioClkMmcmResetSet" range="0" attributes="Strobe">
|
||||
-- <info>
|
||||
-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the
|
||||
-- reset to the MMCM. Default is reset asserted. Write-only.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- </register>
|
||||
--
|
||||
-- <register name="PhaseShiftControl" size="32" offset="0x24" attributes="Readable|Writable">
|
||||
-- <info>
|
||||
-- Phase Shift for RadioClkMmcm.
|
||||
-- </info>
|
||||
-- <bitfield name="PsDone" range="28">
|
||||
-- <info>
|
||||
-- This bit should set after a shift operation successfully completes.
|
||||
-- Reading this register will clear this bit. Read-only.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="PsInc" range="0" attributes="Strobe">
|
||||
-- <info>
|
||||
-- Strobe this bit to increment the phase. This bit is self-clearing and will
|
||||
-- always return '0' when read. If PsInc and PsDec are asserted together,
|
||||
-- the phase will increment.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="PsDec" range="4" attributes="Strobe">
|
||||
-- <info>
|
||||
-- Strobe this bit to decrement the phase. This bit is self-clearing and will
|
||||
-- always return '0' when read. If PsInc and PsDec are asserted together,
|
||||
-- the phase will increment.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="PsEnabledForFdbClk" range="16">
|
||||
-- <info>
|
||||
-- Read-only.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- </register>
|
||||
--
|
||||
-- <register name="RadioClkEnables" size="32" offset="0x28" attributes="Readable|Writable">
|
||||
-- <info>
|
||||
-- </info>
|
||||
-- <bitfield name="RadioClk3xEnabled" range="8">
|
||||
-- <info>
|
||||
-- Set to '1' to enable the clock. Default disabled = '0'.
|
||||
-- Do so ONLY after the MMCM is out of reset and locked!
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="RadioClk2xEnabled" range="4">
|
||||
-- <info>
|
||||
-- Set to '1' to enable the clock. Default disabled = '0'.
|
||||
-- Do so ONLY after the MMCM is out of reset and locked!
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="RadioClk1xEnabled" range="0">
|
||||
-- <info>
|
||||
-- Set to '1' to enable the clock. Default disabled = '0'.
|
||||
-- Do so ONLY after the MMCM is out of reset and locked!
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- </register>
|
||||
--
|
||||
-- <register name="MgtRefClkStatus" size="32" offset="0x30" attributes="Readable">
|
||||
-- <info>
|
||||
-- </info>
|
||||
-- <bitfield name="JesdRefClkPresent" range="0">
|
||||
-- <info>
|
||||
-- Live indicator of the MGT Reference Clock toggling and within expected
|
||||
-- frequency limits. If this bit is de-asserted, then the JESD204b core will
|
||||
-- not function correctly!
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- </register>
|
||||
--
|
||||
-- </group>
|
||||
--
|
||||
--</regmap>
|
||||
--XmlParse xml_off
|
||||
@@ -0,0 +1,116 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: DaughterboardRegs.vhd
|
||||
-- Author: Daniel Jepson
|
||||
-- Original Project: N310
|
||||
-- Date: 27 April 2016
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2016-2018 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Register interface to the semi-static control lines for the Mg
|
||||
-- Daughterboard.
|
||||
--
|
||||
-- XML register definition is included below the module.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library work;
|
||||
use work.PkgDaughterboardRegMap.all;
|
||||
use work.PkgRegs.all;
|
||||
|
||||
|
||||
entity DaughterboardRegs is
|
||||
port(
|
||||
-- Async reset. Can be tied low if desired.
|
||||
aReset : in boolean;
|
||||
-- Sync reset... used in the same places as the async one.
|
||||
bReset : in boolean;
|
||||
BusClk : in std_logic;
|
||||
|
||||
bRegPortOut : out RegPortOut_t;
|
||||
bRegPortIn : in RegPortIn_t;
|
||||
|
||||
-- Slot and DB ID values. These should be tied to constants!
|
||||
kDbId : in std_logic_vector(15 downto 0);
|
||||
kSlotId : in std_logic
|
||||
|
||||
);
|
||||
end DaughterboardRegs;
|
||||
|
||||
|
||||
architecture RTL of DaughterboardRegs is
|
||||
|
||||
--vhook_sigstart
|
||||
--vhook_sigend
|
||||
|
||||
signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- Read Registers : -------------------------------------------------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
ReadRegisters: process(aReset, BusClk)
|
||||
begin
|
||||
if aReset then
|
||||
bRegPortOutLcl <= kRegPortOutZero;
|
||||
elsif rising_edge(BusClk) then
|
||||
if bReset then
|
||||
bRegPortOutLcl <= kRegPortOutZero;
|
||||
else
|
||||
-- De-assert strobes
|
||||
bRegPortOutLcl.Data <= kRegPortDataZero;
|
||||
|
||||
-- All of these transactions only take one clock cycle, so we do not have to
|
||||
-- de-assert the Ready signal (ever).
|
||||
bRegPortOutLcl.Ready <= true;
|
||||
|
||||
if RegRead(kDaughterboardId, bRegPortIn) then
|
||||
bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId;
|
||||
bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process ReadRegisters;
|
||||
|
||||
-- Local to output
|
||||
bRegPortOut <= bRegPortOutLcl;
|
||||
|
||||
|
||||
end RTL;
|
||||
|
||||
|
||||
--XmlParse xml_on
|
||||
--<regmap name="DaughterboardRegMap">
|
||||
-- <group name="StaticControl" order="1">
|
||||
--
|
||||
-- <register name="DaughterboardId" size="32" offset="0x30" attributes="Readable">
|
||||
-- <info>
|
||||
-- </info>
|
||||
-- <bitfield name="DbIdVal" range="15..0">
|
||||
-- <info>
|
||||
-- ID for the DB with which this file is designed to communicate. Matches the DB
|
||||
-- EEPROM ID.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- <bitfield name="SlotIdVal" range="16">
|
||||
-- <info>
|
||||
-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB.
|
||||
-- </info>
|
||||
-- </bitfield>
|
||||
-- </register>
|
||||
--
|
||||
-- </group>
|
||||
--
|
||||
--
|
||||
--</regmap>
|
||||
--XmlParse xml_off
|
||||
@@ -0,0 +1,562 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: DbCore.vhd
|
||||
-- Author: Daniel Jepson
|
||||
-- Original Project: N310
|
||||
-- Date: 12 April 2017
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2017-2018 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Wrapper file for Daughterboard Control. This includes the semi-static control
|
||||
-- and status registers, clocking, synchronization, and JESD204B cores.
|
||||
--
|
||||
-- There is no version register for the plain-text files here.
|
||||
-- Version control for the Sync and JESD204B cores is internal to the netlists.
|
||||
--
|
||||
-- The resets for this core are almost entirely local and/or synchronous.
|
||||
-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the
|
||||
-- registers connected to the RegPort, as well as any other stray registers
|
||||
-- connected to the BusClk. All other resets are local to the modules they touch.
|
||||
-- No other reset drives all modules universally.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgMgPersonality.all;
|
||||
use work.PkgRegs.all;
|
||||
use work.PkgJesdConfig.all;
|
||||
|
||||
|
||||
entity DbCore is
|
||||
generic(
|
||||
-- Set to '1' to include the White Rabbit TDC.
|
||||
kInclWhiteRabbitTdc : std_logic := '0'
|
||||
);
|
||||
port(
|
||||
|
||||
-- Resets --
|
||||
-- Synchronous Reset for the BusClk domain (mainly for the RegPort)
|
||||
bBusReset : in std_logic;
|
||||
|
||||
-- Clocks --
|
||||
-- Register Bus Clock (any frequency)
|
||||
BusClk : in std_logic;
|
||||
-- Always-on at 40 MHz
|
||||
Clk40 : in std_logic;
|
||||
-- Super secret crazy awesome measurement clock at weird frequencies.
|
||||
MeasClk : in std_logic;
|
||||
-- FPGA Sample Clock from DB LMK
|
||||
FpgaClk_p : in std_logic;
|
||||
FpgaClk_n : in std_logic;
|
||||
|
||||
-- Sample Clock Sharing. The clocks generated in this module are exported out to the
|
||||
-- top level so they can be shared amongst daughterboards. Therefore they must be
|
||||
-- driven back into the SampleClk*x inputs at a higher level in order for this module
|
||||
-- to work correctly. There are a few isolated cases where SampleClk*xOut is used
|
||||
-- directly in this module, and those are documented below.
|
||||
SampleClk1xOut : out std_logic;
|
||||
SampleClk1x : in std_logic;
|
||||
SampleClk2xOut : out std_logic;
|
||||
SampleClk2x : in std_logic;
|
||||
|
||||
|
||||
-- Register Ports --
|
||||
--
|
||||
-- Only synchronous resets can be used for these ports!
|
||||
bRegPortInFlat : in std_logic_vector(49 downto 0);
|
||||
bRegPortOutFlat : out std_logic_vector(33 downto 0);
|
||||
|
||||
-- Slot ID value. This should be tied to a constant!
|
||||
kSlotId : in std_logic;
|
||||
|
||||
|
||||
-- SYSREF --
|
||||
--
|
||||
-- SYSREF direct from the LMK
|
||||
sSysRefFpgaLvds_p,
|
||||
sSysRefFpgaLvds_n : in std_logic;
|
||||
-- SYNC directly to the LMK
|
||||
aLmkSync : out std_logic;
|
||||
|
||||
|
||||
-- JESD Signals --
|
||||
--
|
||||
-- GTX Sample Clock Reference Input. Direct connect to FPGA pins.
|
||||
JesdRefClk_p,
|
||||
JesdRefClk_n : in std_logic;
|
||||
|
||||
-- ADC JESD PHY Interface. Direct connect to FPGA pins.
|
||||
aAdcRx_p,
|
||||
aAdcRx_n : in std_logic_vector(3 downto 0);
|
||||
aSyncAdcOut_n : out std_logic;
|
||||
|
||||
-- DAC JESD PHY Interface. Direct connect to FPGA pins.
|
||||
aDacTx_p,
|
||||
aDacTx_n : out std_logic_vector(3 downto 0);
|
||||
aSyncDacIn_n : in std_logic;
|
||||
|
||||
|
||||
-- Data Pipes to/from the DACs/ADCs --
|
||||
--
|
||||
-- - Data is presented as one sample per cycle.
|
||||
-- - sAdcDataValid asserts when ADC data is valid.
|
||||
-- - sDacReadyForInput asserts when DAC data is ready to be received.
|
||||
--
|
||||
-- Reset Crossings:
|
||||
-- The ADC data and valid outputs are synchronously cleared before the asynchronous
|
||||
-- reset is asserted--preventing any reset crossing issues here between the RX
|
||||
-- (internal to the core) reset and the no-reset domain of RFNoC.
|
||||
--
|
||||
-- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted
|
||||
-- in reset. If they are not zeros, then it is still OK because data is ignored until
|
||||
-- RFI is asserted. DAC RFI is double-synchronized to protect against the reset
|
||||
-- crossing. This is safe to do because it simply delays the output of RFI by two
|
||||
-- cycles on the assertion edge, and as long as reset is held for more than two
|
||||
-- cycles, the de-assertion edge of RFI should come long before the TX module is
|
||||
-- taken out of reset.
|
||||
sAdcDataValid : out std_logic;
|
||||
sAdcDataSamples0I : out std_logic_vector(15 downto 0);
|
||||
sAdcDataSamples0Q : out std_logic_vector(15 downto 0);
|
||||
sAdcDataSamples1I : out std_logic_vector(15 downto 0);
|
||||
sAdcDataSamples1Q : out std_logic_vector(15 downto 0);
|
||||
sDacReadyForInput : out std_logic;
|
||||
sDacDataSamples0I : in std_logic_vector(15 downto 0);
|
||||
sDacDataSamples0Q : in std_logic_vector(15 downto 0);
|
||||
sDacDataSamples1I : in std_logic_vector(15 downto 0);
|
||||
sDacDataSamples1Q : in std_logic_vector(15 downto 0);
|
||||
|
||||
|
||||
-- RefClk & Timing & Sync --
|
||||
RefClk : in std_logic;
|
||||
rPpsPulse : in std_logic;
|
||||
rGatedPulseToPin : inout std_logic; -- straight to pin
|
||||
sGatedPulseToPin : inout std_logic; -- straight to pin
|
||||
sPps : out std_logic;
|
||||
sPpsToIob : out std_logic;
|
||||
|
||||
-- White Rabbit Timing & Sync --
|
||||
WrRefClk : in std_logic;
|
||||
rWrPpsPulse : in std_logic;
|
||||
rWrGatedPulseToPin : inout std_logic; -- straight to pin
|
||||
sWrGatedPulseToPin : inout std_logic; -- straight to pin
|
||||
aPpsSfpSel : in std_logic_vector(1 downto 0);
|
||||
|
||||
|
||||
-- Debug for JESD
|
||||
sAdcSync : out std_logic;
|
||||
sDacSync : out std_logic;
|
||||
sSysRef : out std_logic;
|
||||
|
||||
-- Debug for Timing & Sync
|
||||
rRpTransfer : out std_logic;
|
||||
sSpTransfer : out std_logic;
|
||||
rWrRpTransfer : out std_logic;
|
||||
sWrSpTransfer : out std_logic
|
||||
);
|
||||
|
||||
end DbCore;
|
||||
|
||||
|
||||
architecture RTL of DbCore is
|
||||
|
||||
component Jesd204bXcvrCore
|
||||
port (
|
||||
bBusReset : in STD_LOGIC;
|
||||
BusClk : in STD_LOGIC;
|
||||
ReliableClk40 : in STD_LOGIC;
|
||||
FpgaClk1x : in STD_LOGIC;
|
||||
FpgaClk2x : in STD_LOGIC;
|
||||
bFpgaClksStable : in STD_LOGIC;
|
||||
bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0);
|
||||
bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0);
|
||||
aLmkSync : out STD_LOGIC;
|
||||
cSysRefFpgaLvds_p : in STD_LOGIC;
|
||||
cSysRefFpgaLvds_n : in STD_LOGIC;
|
||||
fSysRef : out STD_LOGIC;
|
||||
CaptureSysRefClk : in STD_LOGIC;
|
||||
JesdRefClk_p : in STD_LOGIC;
|
||||
JesdRefClk_n : in STD_LOGIC;
|
||||
bJesdRefClkPresent : out STD_LOGIC;
|
||||
aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0);
|
||||
aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0);
|
||||
aSyncAdcOut_n : out STD_LOGIC;
|
||||
aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0);
|
||||
aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0);
|
||||
aSyncDacIn_n : in STD_LOGIC;
|
||||
fAdc0DataFlat : out STD_LOGIC_VECTOR(31 downto 0);
|
||||
fAdc1DataFlat : out STD_LOGIC_VECTOR(31 downto 0);
|
||||
fDac0DataFlat : in STD_LOGIC_VECTOR(31 downto 0);
|
||||
fDac1DataFlat : in STD_LOGIC_VECTOR(31 downto 0);
|
||||
fAdcDataValid : out STD_LOGIC;
|
||||
fDacReadyForInput : out STD_LOGIC;
|
||||
aDacSync : out STD_LOGIC;
|
||||
aAdcSync : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
function to_Boolean (s : std_ulogic) return boolean is
|
||||
begin
|
||||
return (To_X01(s)='1');
|
||||
end to_Boolean;
|
||||
|
||||
function to_StdLogic(b : boolean) return std_ulogic is
|
||||
begin
|
||||
if b then
|
||||
return '1';
|
||||
else
|
||||
return '0';
|
||||
end if;
|
||||
end to_StdLogic;
|
||||
|
||||
--vhook_sigstart
|
||||
signal aAdcSync: STD_LOGIC;
|
||||
signal aDacSync: STD_LOGIC;
|
||||
signal bClockingRegPortOut: RegPortOut_t;
|
||||
signal bDbRegPortOut: RegPortOut_t;
|
||||
signal bFpgaClksStable: STD_LOGIC;
|
||||
signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0);
|
||||
signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0);
|
||||
signal bJesdRefClkPresent: STD_LOGIC;
|
||||
signal bRadioClk1xEnabled: std_logic;
|
||||
signal bRadioClk2xEnabled: std_logic;
|
||||
signal bRadioClk3xEnabled: std_logic;
|
||||
signal bRadioClkMmcmReset: std_logic;
|
||||
signal bRadioClksValid: std_logic;
|
||||
signal pPsDone: std_logic;
|
||||
signal pPsEn: std_logic;
|
||||
signal pPsInc: std_logic;
|
||||
signal PsClk: std_logic;
|
||||
signal sAdc0DataFlat: STD_LOGIC_VECTOR(31 downto 0);
|
||||
signal sAdc1DataFlat: STD_LOGIC_VECTOR(31 downto 0);
|
||||
signal SampleClk1xOutLcl: std_logic;
|
||||
signal sDac0DataFlat: STD_LOGIC_VECTOR(31 downto 0);
|
||||
signal sDac1DataFlat: STD_LOGIC_VECTOR(31 downto 0);
|
||||
signal sDacReadyForInputAsyncReset: STD_LOGIC;
|
||||
signal sRegPps: std_logic;
|
||||
signal sSysRefAsyncReset: STD_LOGIC;
|
||||
signal sWrPps: std_logic;
|
||||
--vhook_sigend
|
||||
|
||||
signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t;
|
||||
signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t;
|
||||
|
||||
signal sDacReadyForInput_ms, sDacReadyForInputLcl,
|
||||
sDacSync_ms, sDacSyncLcl,
|
||||
sAdcSync_ms, sAdcSyncLcl,
|
||||
sSysRef_ms, sSysRefLcl : std_logic := '0';
|
||||
|
||||
signal sAdc0Data, sAdc1Data : AdcData_t;
|
||||
signal sDac0Data, sDac1Data : DacData_t;
|
||||
|
||||
signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal sUseWrTdcPps : boolean := false;
|
||||
signal sPpsInt, sPpsMuxed : std_logic := '0';
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true";
|
||||
attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true";
|
||||
attribute ASYNC_REG of sDacSync_ms : signal is "true";
|
||||
attribute ASYNC_REG of sDacSyncLcl : signal is "true";
|
||||
attribute ASYNC_REG of sAdcSync_ms : signal is "true";
|
||||
attribute ASYNC_REG of sAdcSyncLcl : signal is "true";
|
||||
attribute ASYNC_REG of sSysRef_ms : signal is "true";
|
||||
attribute ASYNC_REG of sSysRefLcl : signal is "true";
|
||||
attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true";
|
||||
attribute ASYNC_REG of sPpsSfpSel : signal is "true";
|
||||
|
||||
begin
|
||||
|
||||
bRegPortOutFlat <= Flatten(bRegPortOut);
|
||||
bRegPortIn <= Unflatten(bRegPortInFlat);
|
||||
|
||||
|
||||
-- Combine return RegPorts.
|
||||
bRegPortOut <= bJesdRegPortOut
|
||||
+ bClockingRegPortOut
|
||||
+ bSyncRegPortOut + bWrSyncRegPortOut
|
||||
+ bDbRegPortOut;
|
||||
|
||||
|
||||
-- Clocking : -------------------------------------------------------------------------
|
||||
-- Automatically export the Sample Clocks and only use the incoming clocks in the
|
||||
-- remainder of the logic. For a single module, the clocks must be looped back
|
||||
-- in at a higher level!
|
||||
-- ------------------------------------------------------------------------------------
|
||||
|
||||
--vhook_e RadioClocking
|
||||
--vhook_a aReset false
|
||||
--vhook_a bReset to_boolean(bBusReset)
|
||||
--vhook_a RadioClk1x SampleClk1xOutLcl
|
||||
--vhook_a RadioClk2x SampleClk2xOut
|
||||
--vhook_a RadioClk3x open
|
||||
RadioClockingx: entity work.RadioClocking (rtl)
|
||||
port map (
|
||||
aReset => false, --in boolean
|
||||
bReset => to_boolean(bBusReset), --in boolean
|
||||
BusClk => BusClk, --in std_logic
|
||||
bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic
|
||||
bRadioClksValid => bRadioClksValid, --out std_logic
|
||||
bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic
|
||||
bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic
|
||||
bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic
|
||||
pPsInc => pPsInc, --in std_logic
|
||||
pPsEn => pPsEn, --in std_logic
|
||||
PsClk => PsClk, --in std_logic
|
||||
pPsDone => pPsDone, --out std_logic
|
||||
FpgaClk_n => FpgaClk_n, --in std_logic
|
||||
FpgaClk_p => FpgaClk_p, --in std_logic
|
||||
RadioClk1x => SampleClk1xOutLcl, --out std_logic
|
||||
RadioClk2x => SampleClk2xOut, --out std_logic
|
||||
RadioClk3x => open); --out std_logic
|
||||
|
||||
-- We need an internal copy of SampleClk1x for the TDC, since we don't want to try
|
||||
-- and align the other DB's clock accidentally.
|
||||
SampleClk1xOut <= SampleClk1xOutLcl;
|
||||
|
||||
--vhook_e ClockingRegs
|
||||
--vhook_a aReset false
|
||||
--vhook_a bReset to_boolean(bBusReset)
|
||||
--vhook_a bRegPortOut bClockingRegPortOut
|
||||
--vhook_a aRadioClksValid bRadioClksValid
|
||||
ClockingRegsx: entity work.ClockingRegs (RTL)
|
||||
port map (
|
||||
aReset => false, --in boolean
|
||||
bReset => to_boolean(bBusReset), --in boolean
|
||||
BusClk => BusClk, --in std_logic
|
||||
bRegPortOut => bClockingRegPortOut, --out RegPortOut_t
|
||||
bRegPortIn => bRegPortIn, --in RegPortIn_t
|
||||
pPsInc => pPsInc, --out std_logic
|
||||
pPsEn => pPsEn, --out std_logic
|
||||
pPsDone => pPsDone, --in std_logic
|
||||
PsClk => PsClk, --out std_logic
|
||||
bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic
|
||||
aRadioClksValid => bRadioClksValid, --in std_logic
|
||||
bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic
|
||||
bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic
|
||||
bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic
|
||||
bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic
|
||||
|
||||
|
||||
|
||||
-- JESD204B : -------------------------------------------------------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
|
||||
bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn,
|
||||
kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC
|
||||
|
||||
-- Expand/compress the RegPort for moving through the netlist boundary.
|
||||
bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat);
|
||||
bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp);
|
||||
|
||||
--vhook Jesd204bXcvrCore
|
||||
--vhook_a bRegPortInFlat bJesdCoreRegPortInFlat
|
||||
--vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat
|
||||
--vhook_a FpgaClk1x SampleClk1x
|
||||
--vhook_a FpgaClk2x SampleClk2x
|
||||
--vhook_a ReliableClk40 Clk40
|
||||
--vhook_a CaptureSysRefClk SampleClk1xOutLcl
|
||||
--vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p
|
||||
--vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n
|
||||
--vhook_a fSysRef sSysRefAsyncReset
|
||||
--vhook_a fDacReadyForInput sDacReadyForInputAsyncReset
|
||||
--vhook_a {^f(.*)} s$1
|
||||
Jesd204bXcvrCorex: Jesd204bXcvrCore
|
||||
port map (
|
||||
bBusReset => bBusReset, --in STD_LOGIC
|
||||
BusClk => BusClk, --in STD_LOGIC
|
||||
ReliableClk40 => Clk40, --in STD_LOGIC
|
||||
FpgaClk1x => SampleClk1x, --in STD_LOGIC
|
||||
FpgaClk2x => SampleClk2x, --in STD_LOGIC
|
||||
bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC
|
||||
bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0)
|
||||
bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0)
|
||||
aLmkSync => aLmkSync, --out STD_LOGIC
|
||||
cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC
|
||||
cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC
|
||||
fSysRef => sSysRefAsyncReset, --out STD_LOGIC
|
||||
CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC
|
||||
JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC
|
||||
JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC
|
||||
bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC
|
||||
aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0)
|
||||
aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0)
|
||||
aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC
|
||||
aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0)
|
||||
aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0)
|
||||
aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC
|
||||
fAdc0DataFlat => sAdc0DataFlat, --out STD_LOGIC_VECTOR(31:0)
|
||||
fAdc1DataFlat => sAdc1DataFlat, --out STD_LOGIC_VECTOR(31:0)
|
||||
fDac0DataFlat => sDac0DataFlat, --in STD_LOGIC_VECTOR(31:0)
|
||||
fDac1DataFlat => sDac1DataFlat, --in STD_LOGIC_VECTOR(31:0)
|
||||
fAdcDataValid => sAdcDataValid, --out STD_LOGIC
|
||||
fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC
|
||||
aDacSync => aDacSync, --out STD_LOGIC
|
||||
aAdcSync => aAdcSync); --out STD_LOGIC
|
||||
|
||||
JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x)
|
||||
begin
|
||||
if rising_edge(SampleClk1x) then
|
||||
sDacReadyForInput_ms <= sDacReadyForInputAsyncReset;
|
||||
sDacReadyForInputLcl <= sDacReadyForInput_ms;
|
||||
-- No clock crossing here -- just reset, although the prefix declares otherwise...
|
||||
sDacSync_ms <= aDacSync;
|
||||
sDacSyncLcl <= sDacSync_ms;
|
||||
sAdcSync_ms <= aAdcSync;
|
||||
sAdcSyncLcl <= sAdcSync_ms;
|
||||
sSysRef_ms <= sSysRefAsyncReset;
|
||||
sSysRefLcl <= sSysRef_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Locals to outputs.
|
||||
sDacReadyForInput <= sDacReadyForInputLcl;
|
||||
sDacSync <= sDacSyncLcl;
|
||||
sAdcSync <= sAdcSyncLcl;
|
||||
sSysRef <= sSysRefLcl;
|
||||
|
||||
-- Just combine the first two enables, since they're the ones that are used for JESD.
|
||||
-- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain
|
||||
-- and the MGTs directly.
|
||||
bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled;
|
||||
|
||||
-- Compress/expand the flat data types from the netlist and route to top level.
|
||||
sAdc0Data <= Unflatten(sAdc0DataFlat);
|
||||
sAdc1Data <= Unflatten(sAdc1DataFlat);
|
||||
sDac0DataFlat <= Flatten(sDac0Data);
|
||||
sDac1DataFlat <= Flatten(sDac1Data);
|
||||
|
||||
sAdcDataSamples0I <= sAdc0Data.I;
|
||||
sAdcDataSamples0Q <= sAdc0Data.Q;
|
||||
sAdcDataSamples1I <= sAdc1Data.I;
|
||||
sAdcDataSamples1Q <= sAdc1Data.Q;
|
||||
|
||||
sDac0Data.I <= sDacDataSamples0I;
|
||||
sDac0Data.Q <= sDacDataSamples0Q;
|
||||
sDac1Data.I <= sDacDataSamples1I;
|
||||
sDac1Data.Q <= sDacDataSamples1Q;
|
||||
|
||||
|
||||
-- Timing and Sync : ------------------------------------------------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
|
||||
bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn,
|
||||
kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200
|
||||
|
||||
--vhook_e TdcWrapper
|
||||
--vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the
|
||||
--vhook_# clock offset for this daughterboard, not the global SampleClock.
|
||||
--vhook_a SampleClk SampleClk1xOutLcl
|
||||
--vhook_a sPpsPulse sRegPps
|
||||
TdcWrapperx: entity work.TdcWrapper (struct)
|
||||
port map (
|
||||
BusClk => BusClk, --in std_logic
|
||||
bBusReset => bBusReset, --in std_logic
|
||||
RefClk => RefClk, --in std_logic
|
||||
SampleClk => SampleClk1xOutLcl, --in std_logic
|
||||
MeasClk => MeasClk, --in std_logic
|
||||
bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t
|
||||
bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t
|
||||
rPpsPulse => rPpsPulse, --in std_logic
|
||||
sPpsPulse => sRegPps, --out std_logic
|
||||
rRpTransfer => rRpTransfer, --out std_logic
|
||||
sSpTransfer => sSpTransfer, --out std_logic
|
||||
rGatedPulseToPin => rGatedPulseToPin, --inout std_logic
|
||||
sGatedPulseToPin => sGatedPulseToPin); --inout std_logic
|
||||
|
||||
WrTdcGen: if kInclWhiteRabbitTdc = '1' generate
|
||||
bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn,
|
||||
kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400
|
||||
|
||||
--vhook_e TdcWrapper WrTdcWrapperx
|
||||
--vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the
|
||||
--vhook_# clock offset for this daughterboard, not the global SampleClock.
|
||||
--vhook_a bSyncRegPortIn bWrSyncRegPortIn
|
||||
--vhook_a bSyncRegPortOut bWrSyncRegPortOut
|
||||
--vhook_a SampleClk SampleClk1xOutLcl
|
||||
--vhook_a RefClk WrRefClk
|
||||
--vhook_a rPpsPulse rWrPpsPulse
|
||||
--vhook_a sPpsPulse sWrPps
|
||||
--vhook_a rRpTransfer rWrRpTransfer
|
||||
--vhook_a sSpTransfer sWrSpTransfer
|
||||
--vhook_a rGatedPulseToPin rWrGatedPulseToPin
|
||||
--vhook_a sGatedPulseToPin sWrGatedPulseToPin
|
||||
WrTdcWrapperx: entity work.TdcWrapper (struct)
|
||||
port map (
|
||||
BusClk => BusClk, --in std_logic
|
||||
bBusReset => bBusReset, --in std_logic
|
||||
RefClk => WrRefClk, --in std_logic
|
||||
SampleClk => SampleClk1xOutLcl, --in std_logic
|
||||
MeasClk => MeasClk, --in std_logic
|
||||
bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t
|
||||
bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t
|
||||
rPpsPulse => rWrPpsPulse, --in std_logic
|
||||
sPpsPulse => sWrPps, --out std_logic
|
||||
rRpTransfer => rWrRpTransfer, --out std_logic
|
||||
sSpTransfer => sWrSpTransfer, --out std_logic
|
||||
rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic
|
||||
sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic
|
||||
end generate WrTdcGen;
|
||||
|
||||
WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate
|
||||
bWrSyncRegPortOut <= kRegPortOutZero;
|
||||
sWrPps <= '0';
|
||||
rWrRpTransfer <= '0';
|
||||
sWrSpTransfer <= '0';
|
||||
rWrGatedPulseToPin <= '0';
|
||||
sWrGatedPulseToPin <= '0';
|
||||
end generate WrTdcNotGen;
|
||||
|
||||
-- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero
|
||||
-- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time
|
||||
-- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent.
|
||||
-- '00': Use the PPS output from the "regular" TDC.
|
||||
-- '01': Use the PPS output from the "white rabbit" TDC.
|
||||
-- '10': Use the PPS output from the "white rabbit" TDC.
|
||||
PpsOutputMux : process (SampleClk1xOutLcl)
|
||||
begin
|
||||
if rising_edge(SampleClk1xOutLcl) then
|
||||
-- Double-sync the control bits to the Sample Clock domain.
|
||||
sPpsSfpSel_ms <= aPpsSfpSel;
|
||||
sPpsSfpSel <= sPpsSfpSel_ms;
|
||||
|
||||
-- OR the control bits together to produce a single override enable for the WR TDC.
|
||||
sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1));
|
||||
|
||||
-- Flop the outputs. One flop for the PPS output IOB, the other for use internally.
|
||||
sPpsInt <= sPpsMuxed;
|
||||
end if;
|
||||
end process PpsOutputMux;
|
||||
|
||||
sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps;
|
||||
sPps <= sPpsInt;
|
||||
sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module.
|
||||
|
||||
-- Daughterboard Control : ------------------------------------------------------------
|
||||
-- ------------------------------------------------------------------------------------
|
||||
|
||||
--vhook_e DaughterboardRegs
|
||||
--vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs.
|
||||
--vhook_a aReset false
|
||||
--vhook_a bReset to_boolean(bBusReset)
|
||||
--vhook_a bRegPortOut bDbRegPortOut
|
||||
--vhook_a kDbId std_logic_vector(to_unsigned(16#150#,16))
|
||||
DaughterboardRegsx: entity work.DaughterboardRegs (RTL)
|
||||
port map (
|
||||
aReset => false, --in boolean
|
||||
bReset => to_boolean(bBusReset), --in boolean
|
||||
BusClk => BusClk, --in std_logic
|
||||
bRegPortOut => bDbRegPortOut, --out RegPortOut_t
|
||||
bRegPortIn => bRegPortIn, --in RegPortIn_t
|
||||
kDbId => std_logic_vector(to_unsigned(16#150#,16)), --in std_logic_vector(15:0)
|
||||
kSlotId => kSlotId); --in std_logic
|
||||
|
||||
|
||||
end RTL;
|
||||
Binary file not shown.
@@ -0,0 +1,56 @@
|
||||
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
|
||||
-- Date : Wed Jan 10 10:53:33 2018
|
||||
-- Host : djepson-lt running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd
|
||||
-- Design : Jesd204bXcvrCore
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity Jesd204bXcvrCore is
|
||||
Port (
|
||||
bBusReset : in STD_LOGIC;
|
||||
BusClk : in STD_LOGIC;
|
||||
ReliableClk40 : in STD_LOGIC;
|
||||
FpgaClk1x : in STD_LOGIC;
|
||||
FpgaClk2x : in STD_LOGIC;
|
||||
bFpgaClksStable : in STD_LOGIC;
|
||||
bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 );
|
||||
bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 );
|
||||
aLmkSync : out STD_LOGIC;
|
||||
cSysRefFpgaLvds_p : in STD_LOGIC;
|
||||
cSysRefFpgaLvds_n : in STD_LOGIC;
|
||||
fSysRef : out STD_LOGIC;
|
||||
CaptureSysRefClk : in STD_LOGIC;
|
||||
JesdRefClk_p : in STD_LOGIC;
|
||||
JesdRefClk_n : in STD_LOGIC;
|
||||
bJesdRefClkPresent : out STD_LOGIC;
|
||||
aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
aSyncAdcOut_n : out STD_LOGIC;
|
||||
aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
aSyncDacIn_n : in STD_LOGIC;
|
||||
fAdc0DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
fAdc1DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
fDac0DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
fDac1DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
fAdcDataValid : out STD_LOGIC;
|
||||
fDacReadyForInput : out STD_LOGIC;
|
||||
aDacSync : out STD_LOGIC;
|
||||
aAdcSync : out STD_LOGIC
|
||||
);
|
||||
|
||||
end Jesd204bXcvrCore;
|
||||
|
||||
architecture stub of Jesd204bXcvrCore is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],aLmkSync,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,CaptureSysRefClk,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdc0DataFlat[31:0],fAdc1DataFlat[31:0],fDac0DataFlat[31:0],fDac1DataFlat[31:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,107 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: PkgClockingRegMap.vhd
|
||||
-- Author: Autogenerated by XmlParse
|
||||
-- Original Project: --
|
||||
-- Date: --
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2017 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
-- The constants in this file are autogenerated by XmlParse and should
|
||||
-- be used by testbench code to access specific register fields.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package PkgClockingRegMap is
|
||||
|
||||
--===============================================================================
|
||||
-- A numerically ordered list of registers and their VHDL source files
|
||||
--===============================================================================
|
||||
|
||||
-- RadioClkMmcm : 0x20 (ClockingRegs.vhd)
|
||||
-- PhaseShiftControl : 0x24 (ClockingRegs.vhd)
|
||||
-- RadioClkEnables : 0x28 (ClockingRegs.vhd)
|
||||
-- MgtRefClkStatus : 0x30 (ClockingRegs.vhd)
|
||||
|
||||
--===============================================================================
|
||||
-- RegTypes
|
||||
--===============================================================================
|
||||
|
||||
--===============================================================================
|
||||
-- Register Group ClockingRegs
|
||||
--===============================================================================
|
||||
|
||||
-- RadioClkMmcm Register (from ClockingRegs.vhd)
|
||||
constant kRadioClkMmcm : integer := 16#20#; -- Register Offset
|
||||
constant kRadioClkMmcmSize: integer := 32; -- register width in bits
|
||||
constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013";
|
||||
constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet
|
||||
constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet
|
||||
constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet
|
||||
constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear
|
||||
constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear
|
||||
constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear
|
||||
constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked
|
||||
constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked
|
||||
constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked
|
||||
|
||||
-- PhaseShiftControl Register (from ClockingRegs.vhd)
|
||||
constant kPhaseShiftControl : integer := 16#24#; -- Register Offset
|
||||
constant kPhaseShiftControlSize: integer := 32; -- register width in bits
|
||||
constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011";
|
||||
constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc
|
||||
constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc
|
||||
constant kPsInc : integer := 0; --PhaseShiftControl:PsInc
|
||||
constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec
|
||||
constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec
|
||||
constant kPsDec : integer := 4; --PhaseShiftControl:PsDec
|
||||
constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk
|
||||
constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk
|
||||
constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk
|
||||
constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone
|
||||
constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone
|
||||
constant kPsDone : integer := 28; --PhaseShiftControl:PsDone
|
||||
|
||||
-- RadioClkEnables Register (from ClockingRegs.vhd)
|
||||
constant kRadioClkEnables : integer := 16#28#; -- Register Offset
|
||||
constant kRadioClkEnablesSize: integer := 32; -- register width in bits
|
||||
constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111";
|
||||
constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled
|
||||
constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled
|
||||
constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled
|
||||
constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled
|
||||
constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled
|
||||
constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled
|
||||
constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled
|
||||
constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled
|
||||
constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled
|
||||
|
||||
-- MgtRefClkStatus Register (from ClockingRegs.vhd)
|
||||
constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset
|
||||
constant kMgtRefClkStatusSize: integer := 32; -- register width in bits
|
||||
constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001";
|
||||
constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent
|
||||
constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent
|
||||
constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent
|
||||
|
||||
end package;
|
||||
|
||||
package body PkgClockingRegMap is
|
||||
|
||||
-- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
-- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,56 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: PkgDaughterboardRegMap.vhd
|
||||
-- Author: Autogenerated by XmlParse
|
||||
-- Original Project: --
|
||||
-- Date: --
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2017 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
-- The constants in this file are autogenerated by XmlParse and should
|
||||
-- be used by testbench code to access specific register fields.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package PkgDaughterboardRegMap is
|
||||
|
||||
--===============================================================================
|
||||
-- A numerically ordered list of registers and their VHDL source files
|
||||
--===============================================================================
|
||||
|
||||
-- DaughterboardId : 0x630 (DaughterboardRegs.vhd)
|
||||
|
||||
--===============================================================================
|
||||
-- RegTypes
|
||||
--===============================================================================
|
||||
|
||||
--===============================================================================
|
||||
-- Register Group StaticControl
|
||||
--===============================================================================
|
||||
|
||||
-- DaughterboardId Register (from DaughterboardRegs.vhd)
|
||||
constant kDaughterboardId : integer := 16#630#; -- Register Offset
|
||||
constant kDaughterboardIdSize: integer := 32; -- register width in bits
|
||||
constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff";
|
||||
constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal
|
||||
constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal
|
||||
constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal
|
||||
constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal
|
||||
constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal
|
||||
constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal
|
||||
|
||||
end package;
|
||||
|
||||
package body PkgDaughterboardRegMap is
|
||||
|
||||
-- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t.
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,234 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: PkgJesdConfig.vhd
|
||||
-- Author: National Instruments
|
||||
-- Original Project: NI 5840
|
||||
-- Date: 11 March 2016
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2016-2018 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose: JESD204B setup constants and functions. These constants are shared
|
||||
-- between RX and TX JESD cores.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgRegs.all;
|
||||
|
||||
|
||||
package PkgJesdConfig is
|
||||
|
||||
-- "JESD" in ASCII - with the core number 0 or 1 on the LSb.
|
||||
constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344";
|
||||
|
||||
-- Register endpoints
|
||||
constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to
|
||||
kWidth => 16#0800#); -- 0x2FFF
|
||||
|
||||
-- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the
|
||||
-- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2
|
||||
-- frequency. This is a generalization, the clock ratio should be confirmed based on
|
||||
-- the transceiver configuration.
|
||||
-- The N310 transceivers use the single rate reference, hence = false.
|
||||
constant kDoubleRateUsrClk : boolean := false;
|
||||
|
||||
-- For the N310, all lanes are in one quad and we use the QPLL.
|
||||
constant kJesdUseQpll : boolean := true;
|
||||
|
||||
constant kAdcDataWidth : integer := 16; -- ADC data width in bits
|
||||
constant kDacDataWidth : integer := 16; -- DAC data width in bits
|
||||
constant kSamplesPerCycle : integer := 1; -- Number of samples per SampleClk1x
|
||||
|
||||
constant kGtxDrpAddrWidth : natural := 9;
|
||||
constant kQpllDrpAddrWidth : natural := 8;
|
||||
-- Max supported number of lanes
|
||||
constant kMaxNumLanes : natural := 4;
|
||||
-- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect
|
||||
-- the definitions to allow quad sharing)
|
||||
constant kMaxNumQuads : natural := 1;
|
||||
|
||||
|
||||
-- JESD shared setup - LMFS = 4421, HD = 0
|
||||
constant kNumLanes : natural := 4; -- L
|
||||
constant kNumConvs : positive := 4; -- M
|
||||
constant kOctetsPerFrame : natural := 2; -- F
|
||||
constant kDacJesdSamplesPerCycle : integer := 1; -- S
|
||||
constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide
|
||||
constant kNumQuads : natural := kNumLanes/4; -- 4 lanes per quad
|
||||
constant kHighDensity : boolean := false; -- HD
|
||||
constant kConvResBits : positive := kDacDataWidth-2; -- Converter resolution in bits
|
||||
constant kConvSampleBits : positive := kDacDataWidth; -- Sample Length in bits
|
||||
constant kInitLaneAlignCnt : positive := 4;
|
||||
constant kFramesPerMulti : natural := 20; -- K
|
||||
|
||||
-- In the N310 case we are one SPC, so this value is simply the number of frames
|
||||
-- (samples) per multiframe.
|
||||
constant kUserClksPerMulti : integer := kFramesPerMulti;
|
||||
|
||||
|
||||
type NaturalVector is array ( natural range <>) of natural;
|
||||
|
||||
-- The PCB connections are as follows:
|
||||
--
|
||||
-- Transceiver MGT Channel ADC Lane DAC Lane
|
||||
-- *********** *********** ******** ********
|
||||
-- GT0: X0Y8 0 0 0
|
||||
-- GT1: X0Y9 1 1 1
|
||||
-- GT2: X0Y10 2 2 2
|
||||
-- GT3: X0Y11 3 3 3
|
||||
constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) :=
|
||||
(
|
||||
-- MGT => ADC (in above table)
|
||||
0 => 0,
|
||||
1 => 1,
|
||||
2 => 2,
|
||||
3 => 3
|
||||
);
|
||||
|
||||
constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) :=
|
||||
(
|
||||
-- MGT => DAC lane
|
||||
0 => 0,
|
||||
1 => 1,
|
||||
2 => 2,
|
||||
3 => 3
|
||||
);
|
||||
|
||||
constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) :=
|
||||
(
|
||||
-- All lanes are in one quad
|
||||
0 => 0,
|
||||
1 => 0,
|
||||
2 => 0,
|
||||
3 => 0
|
||||
);
|
||||
|
||||
|
||||
-- The master transceiver channel for channel bonding. E(kMasterBondingChannel)
|
||||
-- must have the highest value decrementing to b"000" for that last channels to bond.
|
||||
constant kMasterBondingChannel : integer := 1;
|
||||
|
||||
-- Channel bonding occurs when a master detects a K-char sequence and aligns its
|
||||
-- internal FIFO to the start of this sequence. A signal is then generated to other
|
||||
-- slave transceivers that cause them to bond to the sequence - this bonding signal is
|
||||
-- cascaded from master to slave to slave to slave, etc where each slave must know how
|
||||
-- many levels to the master there are. The last slave to bond must be at level b"000"
|
||||
-- and the master is at the highest level; the number of levels in the sequence is
|
||||
-- governed by the size of the transceiver FIFO (see the Xilinx user guides for more
|
||||
-- information).
|
||||
type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0);
|
||||
constant kBondLevel : BondLevels_t := (
|
||||
0 => b"000", -- Control from 1
|
||||
1 => b"001", -- Master
|
||||
2 => b"000", -- Control from 1
|
||||
3 => b"000" -- Control from 1
|
||||
);
|
||||
|
||||
-- Option to pipeline stages to improve timing, if needed
|
||||
constant kPipelineDetectCharsStage : boolean := false;
|
||||
constant kPipelineCharReplStage : boolean := false;
|
||||
|
||||
|
||||
-- ADC & DAC Data Types
|
||||
--
|
||||
|
||||
-- ADC Words from JESD204B RX Core. The array is 4 elements wide to accommodate the
|
||||
-- I & Q elements from both RX channels.
|
||||
subtype AdcWord_t is std_logic_vector(kAdcDataWidth - 1 downto 0);
|
||||
type AdcWordArray_t is array(4 - 1 downto 0) of AdcWord_t;
|
||||
|
||||
-- Data types for manipulation and presentation to outside world.
|
||||
type AdcData_t is record
|
||||
I : std_logic_vector(kAdcDataWidth - 1 downto 0);
|
||||
Q : std_logic_vector(kAdcDataWidth - 1 downto 0);
|
||||
end record;
|
||||
|
||||
type DacData_t is record
|
||||
I : std_logic_vector(kDacDataWidth - 1 downto 0);
|
||||
Q : std_logic_vector(kDacDataWidth - 1 downto 0);
|
||||
end record;
|
||||
|
||||
|
||||
-- Flattened data types for passing into and out of pre-synthesized components.
|
||||
subtype AdcDataFlat_t is std_logic_vector(2*kAdcDataWidth - 1 downto 0);
|
||||
subtype DacDataFlat_t is std_logic_vector(2*kDacDataWidth - 1 downto 0);
|
||||
|
||||
-- Functions to convert to/from types defined above.
|
||||
function Flatten (AdcData : AdcData_t) return AdcDataFlat_t;
|
||||
function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t;
|
||||
|
||||
function Flatten (DacData : DacData_t) return DacDataFlat_t;
|
||||
function Unflatten(DacData : DacDataFlat_t) return DacData_t;
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
|
||||
package body PkgJesdConfig is
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- Flattens AdcData_t to AdcDataFlat_t
|
||||
function Flatten (AdcData : AdcData_t) return AdcDataFlat_t
|
||||
is
|
||||
variable ReturnVar : AdcDataFlat_t;
|
||||
begin
|
||||
ReturnVar := (others => '0');
|
||||
-- MSB is I
|
||||
ReturnVar := AdcData.I & AdcData.Q;
|
||||
return ReturnVar;
|
||||
end function Flatten;
|
||||
|
||||
|
||||
-- UnFlattens AdcDataFlat_t to AdcData_t
|
||||
function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t
|
||||
is
|
||||
variable ReturnVar : AdcData_t;
|
||||
begin
|
||||
ReturnVar := (others => (others => '0'));
|
||||
-- MSB is I
|
||||
ReturnVar.I := AdcData(2*kAdcDataWidth - 1 downto kAdcDataWidth);
|
||||
ReturnVar.Q := AdcData( kAdcDataWidth - 1 downto 0);
|
||||
return ReturnVar;
|
||||
end function Unflatten;
|
||||
|
||||
|
||||
|
||||
-- Flattens DacData_t to DacDataFlat_t
|
||||
function Flatten (DacData : DacData_t) return DacDataFlat_t
|
||||
is
|
||||
variable ReturnVar : DacDataFlat_t;
|
||||
begin
|
||||
ReturnVar := (others => '0');
|
||||
-- MSB is I
|
||||
ReturnVar := DacData.I & DacData.Q;
|
||||
return ReturnVar;
|
||||
end function Flatten;
|
||||
|
||||
|
||||
-- UnFlattens DacDataFlat_t to DacData_t
|
||||
function Unflatten(DacData : DacDataFlat_t) return DacData_t
|
||||
is
|
||||
variable ReturnVar : DacData_t;
|
||||
begin
|
||||
ReturnVar := (others => (others => '0'));
|
||||
-- MSB is I
|
||||
ReturnVar.I := DacData(2*kDacDataWidth - 1 downto kDacDataWidth);
|
||||
ReturnVar.Q := DacData( kDacDataWidth - 1 downto 0);
|
||||
return ReturnVar;
|
||||
end function Unflatten;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end package body;
|
||||
@@ -0,0 +1,61 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: PkgMgPersonality.vhd
|
||||
-- Author: National Instruments
|
||||
-- Original Project: N310
|
||||
-- Date: 13 April 2017
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2017 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose: This package contains constants and helpful functions that enable
|
||||
-- the FPGA to be compiled with different features.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgRegs.all;
|
||||
|
||||
|
||||
package PkgMgPersonality is
|
||||
|
||||
|
||||
-- RegPort Address Definitions : ------------------------------------------------------
|
||||
--
|
||||
-- DB Regs ...
|
||||
--
|
||||
-- Clocking Offset: 0x 000 Width: 0x 200
|
||||
-- Tdco0 Offset: 0x 200 Width: 0x 200
|
||||
-- Tdco1 Offset: 0x 400 Width: 0x 200
|
||||
-- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200
|
||||
-- Total: 0x2000
|
||||
-- JESD 2x - A Offset: 0x2000 Width: 0x1000
|
||||
-- JESD 2x - B Offset: 0x3000 Width: 0x1000
|
||||
-- Total: 0x4000
|
||||
-- Total: 0x8000 for two DBs
|
||||
-- ------------------------------------------------------------------------------------
|
||||
|
||||
-- A single RegPort runs to the JESD204B Core.
|
||||
constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to
|
||||
kWidth => 16#1000#); -- 0x2FFF
|
||||
|
||||
-- DB Regs : --------------------------------------------------------------------------
|
||||
constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to
|
||||
kWidth => 16#0200#); -- 0x01FF
|
||||
constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to
|
||||
kWidth => 16#0200#); -- 0x03FF
|
||||
constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to
|
||||
kWidth => 16#0200#); -- 0x05FF
|
||||
constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to
|
||||
kWidth => 16#0200#); -- 0x07FF
|
||||
|
||||
|
||||
|
||||
|
||||
end package PkgMgPersonality;
|
||||
@@ -0,0 +1,304 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: RadioClocking.vhd
|
||||
-- Author: Daniel Jepson
|
||||
-- Original Project: N310
|
||||
-- Date: 22 February 2016
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright 2016-2018 Ettus Research, A National Instruments Company
|
||||
-- SPDX-License-Identifier: LGPL-3.0
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock
|
||||
-- coming from the FPGA input pin. Handles all the buffering for the input clock.
|
||||
-- Additionally allows the clocks to be turned on and off, and phase shifted.
|
||||
--
|
||||
-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate!
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity RadioClocking is
|
||||
port (
|
||||
-- Async reset. Can be tied low if desired.
|
||||
aReset : in boolean;
|
||||
-- Sync reset... used in the same places as the async one.
|
||||
bReset : in boolean;
|
||||
|
||||
-- Should be a always-on clock
|
||||
BusClk : in std_logic;
|
||||
|
||||
-- Sync reset to the RadioClkMmcm.
|
||||
bRadioClkMmcmReset : in std_logic;
|
||||
|
||||
-- Locked indication from the RadioClkMmcm in BusClk and aReset domains.
|
||||
bRadioClksValid : out std_logic;
|
||||
|
||||
bRadioClk1xEnabled : in std_logic;
|
||||
bRadioClk2xEnabled : in std_logic;
|
||||
bRadioClk3xEnabled : in std_logic;
|
||||
|
||||
-- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz.
|
||||
pPsInc : in std_logic;
|
||||
pPsEn : in std_logic;
|
||||
PsClk : in std_logic;
|
||||
pPsDone : out std_logic;
|
||||
|
||||
-- Straight from pins. Buffer included in here.
|
||||
FpgaClk_n : in std_logic;
|
||||
FpgaClk_p : in std_logic;
|
||||
|
||||
RadioClk1x : out std_logic;
|
||||
RadioClk2x : out std_logic;
|
||||
RadioClk3x : out std_logic
|
||||
|
||||
);
|
||||
end RadioClocking;
|
||||
|
||||
|
||||
architecture rtl of RadioClocking is
|
||||
|
||||
--vhook_sigstart
|
||||
signal RadioClk1xLcl: std_logic;
|
||||
signal RadioClk1xPll: std_logic;
|
||||
signal RadioClk2xLcl: std_logic;
|
||||
signal RadioClk2xPll: std_logic;
|
||||
signal RadioClk3xLcl: std_logic;
|
||||
signal RadioClk3xPll: std_logic;
|
||||
--vhook_sigend
|
||||
|
||||
signal RadioClkMmcmFeedbackIn,
|
||||
RadioClkMmcmFeedbackOut,
|
||||
FpgaClkSE,
|
||||
aRadioClkMmcmLocked : std_logic;
|
||||
|
||||
signal bRadioClkMmcmLocked_ms,
|
||||
bRadioClkMmcmLocked,
|
||||
bEnableRadioClkBufgOutputs,
|
||||
bEnableRadioClk1xBufgOutput,
|
||||
bEnableRadioClk2xBufgOutput,
|
||||
bEnableRadioClk3xBufgOutput : std_logic := '0';
|
||||
|
||||
signal aRadioClkMmcmResetInternal : std_logic := '1';
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true";
|
||||
attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true";
|
||||
|
||||
begin
|
||||
|
||||
-- Radio Clock Buffering : ------------------------------------------------------------
|
||||
--
|
||||
-- ------------------------------------------------------------------------------------
|
||||
--vhook_i IBUFDS FpgaClkIbufg hidegeneric=true
|
||||
--vhook_a I FpgaClk_p
|
||||
--vhook_a IB FpgaClk_n
|
||||
--vhook_a O FpgaClkSE
|
||||
FpgaClkIbufg: IBUFDS
|
||||
port map (
|
||||
O => FpgaClkSE, --out std_ulogic
|
||||
I => FpgaClk_p, --in std_ulogic
|
||||
IB => FpgaClk_n); --in std_ulogic
|
||||
|
||||
ResetDelay : process(aReset, BusClk)
|
||||
begin
|
||||
if aReset then
|
||||
aRadioClkMmcmResetInternal <= '1';
|
||||
elsif rising_edge(BusClk) then
|
||||
if bReset then
|
||||
aRadioClkMmcmResetInternal <= '1';
|
||||
else
|
||||
-- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset.
|
||||
aRadioClkMmcmResetInternal <= bRadioClkMmcmReset;
|
||||
end if;
|
||||
end if;
|
||||
end process ResetDelay;
|
||||
|
||||
|
||||
RadioClkMmcm: MMCME2_ADV
|
||||
generic map(
|
||||
COMPENSATION => "ZHOLD",
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 6.000, -- Feedback
|
||||
CLKOUT0_DIVIDE_F => 6.000, -- Data Clock 1x, RadioClk1xPll
|
||||
CLKOUT1_DIVIDE => 3, -- Data Clock 2x, RadioClk2xPll
|
||||
CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll
|
||||
CLKOUT3_DIVIDE => 1, -- unused
|
||||
CLKOUT4_DIVIDE => 1, -- unused
|
||||
CLKOUT5_DIVIDE => 1, -- unused
|
||||
CLKOUT6_DIVIDE => 1, -- unused
|
||||
CLKFBOUT_PHASE => 0.000, -- Feedback
|
||||
CLKOUT0_PHASE => 0.000, -- Data Clock 1x
|
||||
CLKOUT1_PHASE => 0.000, -- Data Clock 2x
|
||||
CLKOUT2_PHASE => 0.000, -- Data Clock 3x
|
||||
CLKOUT3_PHASE => 0.000, -- unused
|
||||
CLKOUT4_PHASE => 0.000, -- unused
|
||||
CLKOUT5_PHASE => 0.000, -- unused
|
||||
CLKOUT6_PHASE => 0.000, -- unused
|
||||
CLKOUT0_DUTY_CYCLE => 0.500,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500,
|
||||
DIVCLK_DIVIDE => 1,
|
||||
REF_JITTER1 => 0.010,
|
||||
CLKIN1_PERIOD => 6.510, -- 153.6 MHz max
|
||||
CLKFBOUT_USE_FINE_PS => true,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
STARTUP_WAIT => false,
|
||||
CLKOUT4_CASCADE => false)
|
||||
port map (
|
||||
CLKINSEL => '1',
|
||||
CLKIN1 => FpgaClkSE,
|
||||
CLKIN2 => '0',
|
||||
CLKFBIN => RadioClkMmcmFeedbackIn,
|
||||
RST => aRadioClkMmcmResetInternal,
|
||||
PWRDWN => '0',
|
||||
DADDR => (others => '0'),
|
||||
DI => (others => '0'),
|
||||
DWE => '0',
|
||||
DEN => '0',
|
||||
DCLK => '0',
|
||||
DO => open,
|
||||
DRDY => open,
|
||||
PSINCDEC => pPsInc,
|
||||
PSEN => pPsEn,
|
||||
PSCLK => PsClk,
|
||||
PSDONE => pPsDone,
|
||||
CLKOUT0 => RadioClk1xPll,
|
||||
CLKOUT0B => open,
|
||||
CLKOUT1 => RadioClk2xPll,
|
||||
CLKOUT1B => open,
|
||||
CLKOUT2 => RadioClk3xPll,
|
||||
CLKOUT2B => open,
|
||||
CLKOUT3 => open,
|
||||
CLKOUT3B => open,
|
||||
CLKOUT4 => open,
|
||||
CLKOUT5 => open,
|
||||
CLKOUT6 => open,
|
||||
CLKFBOUT => RadioClkMmcmFeedbackOut,
|
||||
CLKFBOUTB => open,
|
||||
LOCKED => aRadioClkMmcmLocked,
|
||||
CLKINSTOPPED => open,
|
||||
CLKFBSTOPPED => open);
|
||||
|
||||
RadioClkMmcmFeedbackBufg: BUFG
|
||||
port map (
|
||||
I => RadioClkMmcmFeedbackOut,
|
||||
O => RadioClkMmcmFeedbackIn
|
||||
);
|
||||
|
||||
|
||||
-- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in
|
||||
-- reset, we turn off the clocks one cycle before the asynchronous version
|
||||
-- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent
|
||||
-- output glitches.
|
||||
CombineEnablesForBuffers : process(aReset, BusClk)
|
||||
begin
|
||||
if aReset then
|
||||
bRadioClkMmcmLocked_ms <= '0';
|
||||
bRadioClkMmcmLocked <= '0';
|
||||
bEnableRadioClk1xBufgOutput <= '0';
|
||||
bEnableRadioClk2xBufgOutput <= '0';
|
||||
bEnableRadioClk3xBufgOutput <= '0';
|
||||
bEnableRadioClkBufgOutputs <= '0';
|
||||
elsif rising_edge(BusClk) then
|
||||
if bReset then
|
||||
bRadioClkMmcmLocked_ms <= '0';
|
||||
bRadioClkMmcmLocked <= '0';
|
||||
bEnableRadioClk1xBufgOutput <= '0';
|
||||
bEnableRadioClk2xBufgOutput <= '0';
|
||||
bEnableRadioClk3xBufgOutput <= '0';
|
||||
bEnableRadioClkBufgOutputs <= '0';
|
||||
else
|
||||
bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked;
|
||||
bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms;
|
||||
|
||||
bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and
|
||||
not bRadioClkMmcmReset;
|
||||
bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs;
|
||||
bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs;
|
||||
bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs;
|
||||
end if;
|
||||
end if;
|
||||
end process CombineEnablesForBuffers;
|
||||
|
||||
bRadioClksValid <= bEnableRadioClkBufgOutputs;
|
||||
|
||||
--vhook_e WrapBufg RadioClk1xBuf
|
||||
--vhook_a kEnableByDefault false
|
||||
--vhook_a kIgnore false
|
||||
--vhook_a kEnableIsAsync true
|
||||
--vhook_a ClkIn RadioClk1xPll
|
||||
--vhook_a aCe bEnableRadioClk1xBufgOutput
|
||||
--vhook_a ClkOut RadioClk1xLcl
|
||||
RadioClk1xBuf: entity work.WrapBufg (rtl)
|
||||
generic map (
|
||||
kEnableByDefault => false, --boolean:=false
|
||||
kIgnore => false, --boolean:=false
|
||||
kEnableIsAsync => true) --boolean:=false
|
||||
port map (
|
||||
ClkIn => RadioClk1xPll, --in std_logic
|
||||
aCe => bEnableRadioClk1xBufgOutput, --in std_logic
|
||||
ClkOut => RadioClk1xLcl); --out std_logic
|
||||
|
||||
--vhook_e WrapBufg RadioClk2xBuf
|
||||
--vhook_a kEnableByDefault false
|
||||
--vhook_a kIgnore false
|
||||
--vhook_a kEnableIsAsync true
|
||||
--vhook_a ClkIn RadioClk2xPll
|
||||
--vhook_a aCe bEnableRadioClk2xBufgOutput
|
||||
--vhook_a ClkOut RadioClk2xLcl
|
||||
RadioClk2xBuf: entity work.WrapBufg (rtl)
|
||||
generic map (
|
||||
kEnableByDefault => false, --boolean:=false
|
||||
kIgnore => false, --boolean:=false
|
||||
kEnableIsAsync => true) --boolean:=false
|
||||
port map (
|
||||
ClkIn => RadioClk2xPll, --in std_logic
|
||||
aCe => bEnableRadioClk2xBufgOutput, --in std_logic
|
||||
ClkOut => RadioClk2xLcl); --out std_logic
|
||||
|
||||
--vhook_e WrapBufg RadioClk3xBuf
|
||||
--vhook_a kEnableByDefault false
|
||||
--vhook_a kIgnore false
|
||||
--vhook_a kEnableIsAsync true
|
||||
--vhook_a ClkIn RadioClk3xPll
|
||||
--vhook_a aCe bEnableRadioClk3xBufgOutput
|
||||
--vhook_a ClkOut RadioClk3xLcl
|
||||
RadioClk3xBuf: entity work.WrapBufg (rtl)
|
||||
generic map (
|
||||
kEnableByDefault => false, --boolean:=false
|
||||
kIgnore => false, --boolean:=false
|
||||
kEnableIsAsync => true) --boolean:=false
|
||||
port map (
|
||||
ClkIn => RadioClk3xPll, --in std_logic
|
||||
aCe => bEnableRadioClk3xBufgOutput, --in std_logic
|
||||
ClkOut => RadioClk3xLcl); --out std_logic
|
||||
|
||||
|
||||
-- Assign outputs from locals.
|
||||
RadioClk1x <= RadioClk1xLcl;
|
||||
RadioClk2x <= RadioClk2xLcl;
|
||||
RadioClk3x <= RadioClk3xLcl;
|
||||
|
||||
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,347 @@
|
||||
#
|
||||
# Copyright 2017 Ettus Research, A National Instruments Company
|
||||
# SPDX-License-Identifier: LGPL-3.0
|
||||
#
|
||||
# Timing analysis is performed in "/n3xx/dboards/mg/doc/mg_timing.xlsx". See
|
||||
# the spreadsheet for more details and explanations.
|
||||
|
||||
#*******************************************************************************
|
||||
## Daughterboard Clocks
|
||||
|
||||
# 122.88, 125, and 153.6 MHz Sample Clocks are allowable. Constrain the paths to the max
|
||||
# rate in order to support all rates in a single FPGA image.
|
||||
set SAMPLE_CLK_PERIOD 6.510
|
||||
create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P]
|
||||
create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P]
|
||||
create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_A_MGTCLK_P]
|
||||
create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_B_MGTCLK_P]
|
||||
|
||||
# The Radio Clocks coming from the DBs are synchronized together (at the ADCs) to a
|
||||
# typical value of less than 100ps. To give ourselves and Vivado some margin, we claim
|
||||
# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at
|
||||
# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the
|
||||
# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA).
|
||||
# There is one spot in the FPGA where we cross domains between the DB-A and
|
||||
# DB-B clock, so we must ensure that Vivado can analyze that path safely.
|
||||
set FPGA_CLK_EARLY -0.5
|
||||
set FPGA_CLK_LATE 0.5
|
||||
set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b]
|
||||
set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b]
|
||||
|
||||
# Virtual clocks for constraining I/O (used below)
|
||||
create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD
|
||||
create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD
|
||||
|
||||
# The set_clock_latency constraints set on fpga_clk_b are problematic when used with
|
||||
# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround
|
||||
# (used here) is to simply swap the early and late times for the virtual clock so that
|
||||
# it cancels out the source latency during analysis. I tested this by setting the
|
||||
# early and late numbers to zero and then their actual value, running timing reports
|
||||
# on each. The slack report matches for both cases, showing that the reversed early/late
|
||||
# numbers on the virtual clock zero out the latency effects on the actual clock.
|
||||
#
|
||||
# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply
|
||||
# it to fpga_clk_b_v.
|
||||
set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v]
|
||||
set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v]
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Aliases for auto-generated clocks
|
||||
|
||||
create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}]
|
||||
create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}]
|
||||
create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}]
|
||||
|
||||
create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}]
|
||||
create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}]
|
||||
create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}]
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Generated clocks for output busses to the daughterboard
|
||||
#
|
||||
# These clock definitions need to come above the set_clock_groups commands below to work!
|
||||
|
||||
# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are
|
||||
# set by SW at run-time. Divider values are 123, 125, or 154 based on what radio clock
|
||||
# rate is set. To be ultra-conservative (which still provides 10s of ns of slack), we
|
||||
# set an over-constrained divider value of 50.
|
||||
set PL_SPI_DIVIDE_VAL 50
|
||||
set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK]
|
||||
create_generated_clock -name pl_spi_clk_a \
|
||||
-source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \
|
||||
-divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A
|
||||
set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK]
|
||||
create_generated_clock -name pl_spi_clk_b \
|
||||
-source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \
|
||||
-divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B
|
||||
|
||||
# Define one of the outputs of each bus as a clock (even though it isn't a clock). This
|
||||
# allows us to constrain the overall bus skew with respect to one of the bus outputs.
|
||||
# See the remainder of this constraint below for more details.
|
||||
set DSA_CLK [get_ports {DBA_CH1_RX_DSA_DATA[0]}]
|
||||
create_generated_clock -name dsa_bus_clk \
|
||||
-source [get_pins [all_fanin -flat -only_cells -startpoints_only $DSA_CLK]/C] \
|
||||
-divide_by 2 $DSA_CLK
|
||||
|
||||
set ATR_CLK [get_ports DBA_ATR_RX_1]
|
||||
create_generated_clock -name atr_bus_clk \
|
||||
-source [get_pins [all_fanin -flat -only_cells -startpoints_only $ATR_CLK]/C] \
|
||||
-divide_by 2 $ATR_CLK
|
||||
|
||||
# Interface Unused
|
||||
# set MGPIO_CLK [get_ports DBA_MYK_GPIO_0]
|
||||
# create_generated_clock -name myk_gpio_bus_clk \
|
||||
# -source [get_pins [all_fanin -flat -only_cells -startpoints_only [get_ports $MGPIO_CLK]]/C] \
|
||||
# -divide_by 2 [get_ports $MGPIO_CLK]
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Asynchronous clock groups
|
||||
|
||||
# MGT reference clocks are also async to everything.
|
||||
set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks]
|
||||
set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks]
|
||||
|
||||
# fpga_clk_a and fpga_clk_b are related to one another after synchronization.
|
||||
# However, we do need to declare that these clocks (both a and b) and their children
|
||||
# are async to the remainder of the design. Use the wildcard at the end to grab the
|
||||
# virtual clock as well as the real ones.
|
||||
set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks]
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## PS SPI: since these lines all come from the PS and I don't have access to the
|
||||
# driving clock (or anything for that matter), I'm left with constraining the maximum
|
||||
# and minimum delay on these lines, per a Xilinx AR:
|
||||
# https://www.xilinx.com/support/answers/62122.html
|
||||
set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \
|
||||
DB*_CPLD_PS_SPI_SDI \
|
||||
DB*_CPLD_PS_SPI_LE \
|
||||
DB*_CPLD_PS_SPI_ADDR[0] \
|
||||
DB*_CPLD_PS_SPI_ADDR[1]}]
|
||||
|
||||
set_max_delay 12.0 -to $CPLD_SPI_OUTS
|
||||
set_min_delay 3.0 -to $CPLD_SPI_OUTS
|
||||
|
||||
set MYK_SPI_OUTS [get_ports {DB*_MYK_SPI_SCLK \
|
||||
DB*_MYK_SPI_SDIO \
|
||||
DB*_MYK_SPI_CS_n}]
|
||||
|
||||
set_max_delay 14.0 -to $MYK_SPI_OUTS
|
||||
set_min_delay 3.0 -to $MYK_SPI_OUTS
|
||||
|
||||
# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming
|
||||
# report_timing -to $MYK_SPI_OUTS -max_paths 20 -delay_type min_max -name MykSpiOutTiming
|
||||
|
||||
set MIN_IN_DELAY 2.0
|
||||
set MAX_IN_DELAY 10.0
|
||||
|
||||
set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}]
|
||||
set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}]
|
||||
|
||||
set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0
|
||||
set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0
|
||||
set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1
|
||||
set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1
|
||||
|
||||
# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming
|
||||
# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## PL SPI to the CPLD
|
||||
#
|
||||
# All of these lines are driven or received from flops in simple_spi_core. The CPLD
|
||||
# calculations assume the FPGA has less than 20 ns of skew between the SCK and
|
||||
# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition.
|
||||
# Do this for DBA and DBB independently.
|
||||
set MAX_SKEW 20.0
|
||||
set SETUP_SKEW [expr {$MAX_SKEW / 2}]
|
||||
set HOLD_SKEW [expr {$MAX_SKEW / 2}]
|
||||
# Do not set the output delay constraint on the clock line!
|
||||
set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_LE \
|
||||
DBA_CPLD_PL_SPI_SDI \
|
||||
DBA_CPLD_PL_SPI_ADDR[0] \
|
||||
DBA_CPLD_PL_SPI_ADDR[1]}]
|
||||
set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_LE \
|
||||
DBB_CPLD_PL_SPI_SDI \
|
||||
DBB_CPLD_PL_SPI_ADDR[0] \
|
||||
DBB_CPLD_PL_SPI_ADDR[1]}]
|
||||
# Then add the output delay on each of the ports.
|
||||
set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A
|
||||
set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A
|
||||
set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B
|
||||
set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B
|
||||
# Finally, make both the setup and hold checks use the same launching and latching edges.
|
||||
set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0
|
||||
set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1
|
||||
set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0
|
||||
set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1
|
||||
|
||||
# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround
|
||||
# time plus any board propagation delay.
|
||||
set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_SDO]
|
||||
set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_SDO]
|
||||
set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -max 68.041 $MISO_INPUT_A
|
||||
set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -min 12.218 $MISO_INPUT_A
|
||||
set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -max 68.041 $MISO_INPUT_B
|
||||
set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -min 12.218 $MISO_INPUT_B
|
||||
# Since the input delay span is clearly more than a period of the radio_clk, we need to
|
||||
# add a multicycle path here as well to define the clock divider ratio. The MISO data
|
||||
# is driven on the falling edge of the SPI clock and captured on the rising edge, so we
|
||||
# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK
|
||||
# as-is due to the delays in the CPLD and board.
|
||||
set SETUP_CYCLES [expr {$PL_SPI_DIVIDE_VAL / 2}]
|
||||
set HOLD_CYCLES 0
|
||||
set_multicycle_path -setup -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A \
|
||||
$SETUP_CYCLES
|
||||
set_multicycle_path -hold -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A -end \
|
||||
[expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}]
|
||||
set_multicycle_path -setup -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B \
|
||||
$SETUP_CYCLES
|
||||
set_multicycle_path -hold -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B -end \
|
||||
[expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}]
|
||||
|
||||
# One of the PL_SPI_ADDR lines is used instead for the LMK SYNC strobe. This line is
|
||||
# driven asynchronously.
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_CPLD_PL_SPI_ADDR[2]]
|
||||
set_max_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 50.000
|
||||
set_min_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 0.000
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## DSA Bus
|
||||
# The DSA controls are driven from the DB-A radio clock. Although they are received async
|
||||
# at the DSAs, they should be tightly constrained in the FPGA to arrive as closely as
|
||||
# possible. The best way to do this is a skew constraint across all the bits.
|
||||
set MAX_SKEW 2.5
|
||||
set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}]
|
||||
set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}]
|
||||
set PORT_LIST [get_ports {DB*_CH*_*X_DSA_DATA[*]}]
|
||||
# Then add the output delay on each of the ports.
|
||||
set_output_delay -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST
|
||||
set_output_delay -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST
|
||||
# Finally, make both the setup and hold checks use the same launching and latching edges.
|
||||
# The clock, which is essentially one of the data lines, should arrive at the pin
|
||||
# +/- MAX_DELAY compared to the other data lines, so setup and hold checks need to be
|
||||
# relative to the SAME edges for both the clock and the data.
|
||||
set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -start 0
|
||||
set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -1
|
||||
# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but
|
||||
# they aren't supported in XDC files... so we do it the old fashioned way.
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 $DSA_CLK
|
||||
set_max_delay -to $DSA_CLK 50.000
|
||||
set_min_delay -to $DSA_CLK 0.000
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## ATR Bus
|
||||
# The ATR bits are driven from the DB-A radio clock. Although they are received async in
|
||||
# the CPLD, they should be tightly constrained in the FPGA to avoid any race conditions.
|
||||
# The best way to do this is a skew constraint across all the bits.
|
||||
set MAX_SKEW 2.5
|
||||
set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}]
|
||||
set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}]
|
||||
set PORT_LIST [get_ports DB*_ATR_*X_*]
|
||||
# Then add the output delay on each of the ports.
|
||||
set_output_delay -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST
|
||||
set_output_delay -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST
|
||||
# Finally, make both the setup and hold checks use the same launching and latching edges.
|
||||
set_multicycle_path -setup -to [get_clocks atr_bus_clk] -start 0
|
||||
set_multicycle_path -hold -to [get_clocks atr_bus_clk] -1
|
||||
# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but
|
||||
# they aren't supported in XDC files... so we do it the old fashioned way.
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 $ATR_CLK
|
||||
set_max_delay -to $ATR_CLK 50.000
|
||||
set_min_delay -to $ATR_CLK 0.000
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Mykonos Ports
|
||||
# Mykonos GPIO is driven from the DB-A radio clock. Although they are received async in
|
||||
# Mykonos, they should be tightly constrained in the FPGA to avoid any race conditions.
|
||||
# The best way to do this is a skew constraint across all the bits.
|
||||
# set MAX_SKEW 2.5
|
||||
# set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}]
|
||||
# set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}]
|
||||
# set PORT_LIST [get_ports DB*_ATR_*X_*]
|
||||
# # Then add the output delay on each of the ports.
|
||||
# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST
|
||||
# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST
|
||||
# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST
|
||||
# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST
|
||||
# # Finally, make both the setup and hold checks use the same launching and latching edges.
|
||||
# set_multicycle_path -setup -to [get_clocks myk_gpio_bus_clk] -start 0
|
||||
# set_multicycle_path -hold -to [get_clocks myk_gpio_bus_clk] -1
|
||||
# # Remove analysis from the output "clock" pin. There are ways to do this using TCL, but
|
||||
# # they aren't supported in XDC files... so we do it the old fashioned way.
|
||||
# set_output_delay -clock [get_clocks async_out_clk] 0.000 $MGPIO_CLK
|
||||
# set_max_delay -to $MGPIO_CLK 50.000
|
||||
# set_min_delay -to $MGPIO_CLK 0.000
|
||||
|
||||
# Mykonos Interrupt is received asynchronously, and driven directly to the PS.
|
||||
set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_INTRQ]
|
||||
set_max_delay -from [get_ports DB*_MYK_INTRQ] 50.000
|
||||
set_min_delay -from [get_ports DB*_MYK_INTRQ] 0.000
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## SYSREF/SYNC JESD Timing
|
||||
#
|
||||
# SYNC is async, SYSREF is tightly timed.
|
||||
|
||||
# The SYNC output for both DBs is governed by the JESD cores, which are solely driven by
|
||||
# DB-A clock... but it is an asynchronous signal so we use the async_out_clk.
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_MYK_SYNC_IN_n]
|
||||
set_max_delay -to [get_ports DB*_MYK_SYNC_IN_n] 50.000
|
||||
set_min_delay -to [get_ports DB*_MYK_SYNC_IN_n] 0.000
|
||||
|
||||
# The SYNC input for both DBs is received by the DB-A clock inside the JESD cores... but
|
||||
# again, it is asynchronous and therefore uses the async_in_clk.
|
||||
set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_SYNC_OUT_n]
|
||||
set_max_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 50.000
|
||||
set_min_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 0.000
|
||||
|
||||
# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once
|
||||
# for the worst-case numbers across both DBs to produce one set of numbers for both DBs.
|
||||
# Since we easily meet setup and hold in Vivado, then this is an acceptable approach.
|
||||
# SYSREF is captured by the local clock from each DB, so we have two sets of constraints.
|
||||
set_input_delay -clock fpga_clk_a_v -min -0.906 [get_ports DBA_FPGA_SYSREF_*]
|
||||
set_input_delay -clock fpga_clk_a_v -max 0.646 [get_ports DBA_FPGA_SYSREF_*]
|
||||
|
||||
set_input_delay -clock fpga_clk_b_v -min -0.906 [get_ports DBB_FPGA_SYSREF_*]
|
||||
set_input_delay -clock fpga_clk_b_v -max 0.646 [get_ports DBB_FPGA_SYSREF_*]
|
||||
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## PPS Timing
|
||||
|
||||
# Due to the N3xx synchronization and clocking structure, the PPS output is driven from
|
||||
# the Sample Clock domain instead of the input Reference Clock. Constrain the output as
|
||||
# tightly as possible to accurately mimic the internal Sample Clock timing.
|
||||
set SETUP_SKEW 2.0
|
||||
set HOLD_SKEW -0.5
|
||||
set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT]
|
||||
set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT]
|
||||
set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0
|
||||
set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1
|
||||
@@ -0,0 +1,2 @@
|
||||
Timing closure of the CPLD design relies on the pre-set seed value. The build
|
||||
requires Quartus 16.1.2.
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user